v2012.07 Panda_ES Regression

[RobertCNelson]

Panda ES's hard lock with v2012.07 (doesn't effect older Panda's)

v3.2.x
v3.5.x (with v3.6 cpuidle patcheset)
v3.6-rc1 + top of tree

Usually:
[ 1.943298] voltdm_scale: No voltage scale API registered for vdd_mpu
[ 1.950073] platform mpu.0: omap_target: unable to scale voltage up.

Or it'll just crash... around there...

git bisect start

bad: [190649fb4309d1bc0fe7732fd0f951cb6440f935] Prepare v2012.07

git bisect bad 190649fb4309d1bc0fe7732fd0f951cb6440f935

good: [415d386877df49eb051b85ef74fa59a16dc17c7d] Prepare v2012.04.01

git bisect good 415d386877df49eb051b85ef74fa59a16dc17c7d

bad: [74b5b5dbc3345a8fad4bc798f8f88d07d2ef0008] Merge branch 'master' of git://git.denx.de/u-boot-avr32

git bisect bad 74b5b5dbc3345a8fad4bc798f8f88d07d2ef0008

bad: [f9f3e1b8df9804c98a2a3077d0acb24247e0e74b] tegra: Move ap20.h header into arch location

git bisect bad f9f3e1b8df9804c98a2a3077d0acb24247e0e74b

skip: [328aecaf3dbca4eea31632a5bfddf38b63204227] mmc: omap5evm: Add eMMC saveenv support

git bisect skip 328aecaf3dbca4eea31632a5bfddf38b63204227

good: [5056c8e068e30c73d3653f0b2cabbae46174a165] powerpc/corenet_ds: Slave core in holdoff when boot from SRIO

git bisect good 5056c8e068e30c73d3653f0b2cabbae46174a165

bad: [19a695f84bb15e1a9203121f9dd4d1787d9a7757] tools, config.mk: Add gcc-version.sh, cc-version test from Linux

git bisect bad 19a695f84bb15e1a9203121f9dd4d1787d9a7757

good: [e0f6a4e8b17afead8add6e528936a505367c091c] Merge branch 'master' of /home/wd/git/u-boot/custodians

git bisect good e0f6a4e8b17afead8add6e528936a505367c091c

skip: [f40107345cbcd6e0d1747eda45e76c4e2a6df0db] OMAP5: emif/ddr: Change emif settings as required for ES1.0 silicon.

git bisect skip f40107345cbcd6e0d1747eda45e76c4e2a6df0db

good: [e5841e12114fbc55dcc2b409ba5cd09081f33483] kirkwood: add NAS62x0 board support

git bisect good e5841e12114fbc55dcc2b409ba5cd09081f33483

skip: [c1fa3c37af7b99ba80f232a84f6b84e90f481f06] OMAP4/5: device: Add support to get the device type.

git bisect skip c1fa3c37af7b99ba80f232a84f6b84e90f481f06

bad: [03f69dc6fdc34e5e51f2c09373ff1bea7d16e36b] omap4+: Avoid using attribute ((packed))

git bisect bad 03f69dc6fdc34e5e51f2c09373ff1bea7d16e36b

skip: [002a2c0c66d2e1757b89ad6824b4a472dcef1076] OMAP4/5: Make the sysctrl structure common

git bisect skip 002a2c0c66d2e1757b89ad6824b4a472dcef1076

skip: [8de17f4617816919c4b73a3a1a377d5507596293] OMAP5: palmas: Configure nominal opp vdd values

git bisect skip 8de17f4617816919c4b73a3a1a377d5507596293

good: [a78274b2050dcacc29561f4e35bdc91b896578cd] OMAP3+: Introduce generic logic for OMAP voltage controller

git bisect good a78274b2050dcacc29561f4e35bdc91b896578cd

skip: [7a4bf209306346e30df18703b8c9af13e42fd10a] OMAP5: defconfig: Align the defconfig for 5430 ES1.0

git bisect skip 7a4bf209306346e30df18703b8c9af13e42fd10a

skip: [74236acacc27168102b2e3fbcac3a80e5ed82fe4] armv7: add appropriate headers for assembly functions

git bisect skip 74236acacc27168102b2e3fbcac3a80e5ed82fe4

skip: [aaec44874f607db3cb19985f0b977cc6f13fd11f] OMAP4/5: emif: Correct the emif power mgt shadow register bit fields.

git bisect skip aaec44874f607db3cb19985f0b977cc6f13fd11f

skip: [7245536d19aaf0a6dc1c2d4a8fa80adf2f2ae739] arm: adapt asm/linkage.h from Linux

git bisect skip 7245536d19aaf0a6dc1c2d4a8fa80adf2f2ae739

skip: [47c50143aad7676ffa513bc395c49eb254a2c191] OMAP5: SRAM: Change the SRAM base address.

git bisect skip 47c50143aad7676ffa513bc395c49eb254a2c191

bad: [5f14d9197edc5476d3453349651d295df2dcb8c3] OMAP5: clocks: Change clock settings as required for ES1.0 silicon.

git bisect bad 5f14d9197edc5476d3453349651d295df2dcb8c3

bad: [f2ae6c1a83e194dfd0fc93348efe598353f3c02d] OMAP4: scale voltage of core before MPU scales

git bisect bad f2ae6c1a83e194dfd0fc93348efe598353f3c02d

bad: [3acb553439e3ee9f62f022f96f949c21811f8bdf] OMAP4460: TPS Ensure SET1 is selected after voltage configuration

git bisect bad 3acb553439e3ee9f62f022f96f949c21811f8bdf

3acb553439e3ee9f62f022f96f949c21811f8bdf is the first bad commit
commit 3acb553439e3ee9f62f022f96f949c21811f8bdf
Author: Nishanth Menon nm@ti.com
Date: Thu Mar 1 14:17:38 2012 +0000

OMAP4460: TPS Ensure SET1 is selected after voltage configuration

TPS SET0/SET1 register is selected by a GPIO pin on OMAP4460 platforms.
Currently we control this pin with a mux configuration as part of
boot sequence.
Current configuration results in the following voltage waveform:
                           |---------------| (SET1 default 1.4V)
                           |               --------(programmed voltage)
                           | <- (This switch happens on mux7,pullup)
vdd_mpu(TPS)         -----/ (OPP boot voltage)
                                             --------- (programmed voltage)
vdd_core(TWL6030)    -----------------------/ (OPP boot voltage)
Problem 1)                |<----- Tx ------>|
   timing violation for a duration Tx close to few milliseconds.
Problem 2) voltage of MPU goes beyond spec for even the highest of MPU OPP.

By using GPIO as recommended as standard procedure by TI, the sequence
changes to:
                                  -------- (programmed voltage)
vdd_mpu(TPS)         ------------/ (Opp boot voltage)
                                   --------- (programmed voltage)
vdd_core(TWL6030)    -------------/ (OPP boot voltage)

NOTE: This does not attempt to address OMAP5 - Aneesh please confirm

Reported-by: Isabelle Gros <i-gros@ti.com>
Reported-by: Jerome Angeloni <j-angeloni@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>

:040000 040000 9858b75bf4a4af624dde3d7c41ebba610c9c6b9a 3a266225b36365cefc65da9ab21d94c12d19b981 M arch
:040000 040000 ebb9b5017bf692f92ce7df9de44a70d1a0553a75 146e564d9ebe258a2754574d75cceebdd67f394c M board

[RobertCNelson]

This seems fixed with v3.6.x...