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adreno.c
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adreno.c
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// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2002,2007-2021, The Linux Foundation. All rights reserved.
* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/of_fdt.h>
#include <linux/module.h>
#include <linux/msm_kgsl.h>
#include <linux/msm-bus.h>
#include <linux/regulator/consumer.h>
#include <linux/nvmem-consumer.h>
#include <soc/qcom/scm.h>
#include "adreno.h"
#include "adreno_a3xx.h"
#include "adreno_a5xx.h"
#include "adreno_a6xx.h"
#include "adreno_compat.h"
#include "adreno_iommu.h"
#include "adreno_llc.h"
#include "adreno_trace.h"
#include "kgsl_trace.h"
/* Include the master list of GPU cores that are supported */
#include "adreno-gpulist.h"
unsigned int is_gpu_overclocked = 0;
static int __init read_gpu_overclock_state(char *s)
{
if (s)
is_gpu_overclocked = simple_strtoul(s, NULL, 0);
return 1;
}
__setup("overclock.gpu=", read_gpu_overclock_state);
static void adreno_pwr_on_work(struct work_struct *work);
static unsigned int counter_delta(struct kgsl_device *device,
unsigned int reg, unsigned int *counter);
static struct devfreq_msm_adreno_tz_data adreno_tz_data = {
.bus = {
.max = 1200,
.floating = true,
},
.device_id = KGSL_DEVICE_3D0,
};
static const struct kgsl_functable adreno_functable;
static struct adreno_device device_3d0 = {
.dev = {
KGSL_DEVICE_COMMON_INIT(device_3d0.dev),
.pwrscale = KGSL_PWRSCALE_INIT(&adreno_tz_data),
.name = DEVICE_3D0_NAME,
.id = KGSL_DEVICE_3D0,
.pwrctrl = {
.irq_name = "kgsl_3d0_irq",
},
.iomemname = "kgsl_3d0_reg_memory",
.ftbl = &adreno_functable,
},
.ft_policy = KGSL_FT_DEFAULT_POLICY,
.ft_pf_policy = KGSL_FT_PAGEFAULT_DEFAULT_POLICY,
.long_ib_detect = 1,
.pwrctrl_flag = BIT(ADRENO_THROTTLING_CTRL) | BIT(ADRENO_HWCG_CTRL),
.profile.enabled = false,
.active_list = LIST_HEAD_INIT(device_3d0.active_list),
.active_list_lock = __SPIN_LOCK_UNLOCKED(device_3d0.active_list_lock),
.gpu_llc_slice_enable = true,
.gpuhtw_llc_slice_enable = true,
.preempt = {
.preempt_level = 1,
.skipsaverestore = 1,
.usesgmem = 1,
},
.pwr_on_work = __WORK_INITIALIZER(device_3d0.pwr_on_work,
adreno_pwr_on_work),
};
/* Ptr to array for the current set of fault detect registers */
unsigned int *adreno_ft_regs;
/* Total number of fault detect registers */
unsigned int adreno_ft_regs_num;
/* Ptr to array for the current fault detect registers values */
unsigned int *adreno_ft_regs_val;
/* Array of default fault detect registers */
static unsigned int adreno_ft_regs_default[] = {
ADRENO_REG_RBBM_STATUS,
ADRENO_REG_CP_RB_RPTR,
ADRENO_REG_CP_IB1_BASE,
ADRENO_REG_CP_IB1_BUFSZ,
ADRENO_REG_CP_IB2_BASE,
ADRENO_REG_CP_IB2_BUFSZ,
};
/* Nice level for the higher priority GPU start thread */
int adreno_wake_nice = -7;
void adreno_reglist_write(struct adreno_device *adreno_dev,
const struct adreno_reglist *list, u32 count)
{
int i;
for (i = 0; list && i < count; i++)
kgsl_regwrite(KGSL_DEVICE(adreno_dev),
list[i].offset, list[i].value);
}
/**
* adreno_readreg64() - Read a 64bit register by getting its offset from the
* offset array defined in gpudev node
* @adreno_dev: Pointer to the the adreno device
* @lo: lower 32bit register enum that is to be read
* @hi: higher 32bit register enum that is to be read
* @val: 64 bit Register value read is placed here
*/
void adreno_readreg64(struct adreno_device *adreno_dev,
enum adreno_regs lo, enum adreno_regs hi, uint64_t *val)
{
struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);
unsigned int val_lo = 0, val_hi = 0;
struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
if (adreno_checkreg_off(adreno_dev, lo))
kgsl_regread(device, gpudev->reg_offsets->offsets[lo], &val_lo);
if (adreno_checkreg_off(adreno_dev, hi))
kgsl_regread(device, gpudev->reg_offsets->offsets[hi], &val_hi);
*val = (val_lo | ((uint64_t)val_hi << 32));
}
/**
* adreno_writereg64() - Write a 64bit register by getting its offset from the
* offset array defined in gpudev node
* @adreno_dev: Pointer to the the adreno device
* @lo: lower 32bit register enum that is to be written
* @hi: higher 32bit register enum that is to be written
* @val: 64 bit value to write
*/
void adreno_writereg64(struct adreno_device *adreno_dev,
enum adreno_regs lo, enum adreno_regs hi, uint64_t val)
{
struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);
if (adreno_checkreg_off(adreno_dev, lo))
kgsl_regwrite(KGSL_DEVICE(adreno_dev),
gpudev->reg_offsets->offsets[lo], lower_32_bits(val));
if (adreno_checkreg_off(adreno_dev, hi))
kgsl_regwrite(KGSL_DEVICE(adreno_dev),
gpudev->reg_offsets->offsets[hi], upper_32_bits(val));
}
/**
* adreno_get_rptr() - Get the current ringbuffer read pointer
* @rb: Pointer the ringbuffer to query
*
* Get the latest rptr
*/
unsigned int adreno_get_rptr(struct adreno_ringbuffer *rb)
{
struct adreno_device *adreno_dev = ADRENO_RB_DEVICE(rb);
unsigned int rptr = 0;
if (adreno_is_a3xx(adreno_dev))
adreno_readreg(adreno_dev, ADRENO_REG_CP_RB_RPTR,
&rptr);
else {
struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
kgsl_sharedmem_readl(&device->scratch, &rptr,
SCRATCH_RPTR_OFFSET(rb->id));
}
return rptr;
}
/**
* adreno_of_read_property() - Adreno read property
* @node: Device node
*
* Read a u32 property.
*/
static inline int adreno_of_read_property(struct device *dev,
struct device_node *node, const char *prop, unsigned int *ptr)
{
int ret = of_property_read_u32(node, prop, ptr);
if (ret)
dev_err(dev, "%pOF: Unable to read '%s'\n", node, prop);
return ret;
}
static void __iomem *efuse_base;
static size_t efuse_len;
int adreno_efuse_map(struct adreno_device *adreno_dev)
{
struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
struct resource *res;
if (efuse_base != NULL)
return 0;
res = platform_get_resource_byname(device->pdev, IORESOURCE_MEM,
"qfprom_memory");
if (res == NULL)
return -ENODEV;
efuse_base = ioremap(res->start, resource_size(res));
if (efuse_base == NULL)
return -ENODEV;
efuse_len = resource_size(res);
return 0;
}
void adreno_efuse_unmap(struct adreno_device *adreno_dev)
{
if (efuse_base != NULL) {
iounmap(efuse_base);
efuse_base = NULL;
efuse_len = 0;
}
}
int adreno_efuse_read_u32(struct adreno_device *adreno_dev, unsigned int offset,
unsigned int *val)
{
if (efuse_base == NULL)
return -ENODEV;
if (offset >= efuse_len)
return -ERANGE;
if (val != NULL) {
*val = readl_relaxed(efuse_base + offset);
/* Make sure memory is updated before returning */
rmb();
}
return 0;
}
void adreno_efuse_speed_bin_array(struct adreno_device *adreno_dev)
{
struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
int ret, count, i = 0;
unsigned int val, vector_size = 3;
unsigned int *bin_vector;
/*
* Here count is no of 32 bit elements in the
* speed-bin-vector array. If there are two fuses
* i.e If no of fuses are 2 then no of elements will be
* 2 * 3 = 6(elements of 32 bit each).
*/
count = of_property_count_u32_elems(device->pdev->dev.of_node,
"qcom,gpu-speed-bin-vectors");
if ((count <= 0) || (count % vector_size))
return;
bin_vector = kmalloc_array(count, sizeof(unsigned int), GFP_KERNEL);
if (bin_vector == NULL)
return;
if (of_property_read_u32_array(device->pdev->dev.of_node,
"qcom,gpu-speed-bin-vectors",
bin_vector, count)) {
dev_err(device->dev,
"Speed-bin-vectors is invalid\n");
kfree(bin_vector);
return;
}
/*
* Final value of adreno_dev->speed_bin is the value formed by
* OR'ing the values read from all the fuses.
*/
while (i < count) {
ret = adreno_efuse_read_u32(adreno_dev, bin_vector[i], &val);
if (ret < 0)
break;
adreno_dev->speed_bin |= (val & bin_vector[i+1])
>> bin_vector[i+2];
i += vector_size;
}
kfree(bin_vector);
}
static int _get_counter(struct adreno_device *adreno_dev,
int group, int countable, unsigned int *lo,
unsigned int *hi)
{
int ret = 0;
if (*lo == 0) {
ret = adreno_perfcounter_get(adreno_dev, group, countable,
lo, hi, PERFCOUNTER_FLAG_KERNEL);
if (ret) {
dev_err(KGSL_DEVICE(adreno_dev)->dev,
"Unable to allocate fault detect performance counter %d/%d\n",
group, countable);
dev_err(KGSL_DEVICE(adreno_dev)->dev,
"GPU fault detect will be less reliable\n");
}
}
return ret;
}
static inline void _put_counter(struct adreno_device *adreno_dev,
int group, int countable, unsigned int *lo,
unsigned int *hi)
{
if (*lo != 0)
adreno_perfcounter_put(adreno_dev, group, countable,
PERFCOUNTER_FLAG_KERNEL);
*lo = 0;
*hi = 0;
}
/**
* adreno_fault_detect_start() - Allocate performance counters
* used for fast fault detection
* @adreno_dev: Pointer to an adreno_device structure
*
* Allocate the series of performance counters that should be periodically
* checked to verify that the GPU is still moving
*/
void adreno_fault_detect_start(struct adreno_device *adreno_dev)
{
struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);
unsigned int i, j = ARRAY_SIZE(adreno_ft_regs_default);
if (!test_bit(ADRENO_DEVICE_SOFT_FAULT_DETECT, &adreno_dev->priv))
return;
if (adreno_dev->fast_hang_detect == 1)
return;
for (i = 0; i < gpudev->ft_perf_counters_count; i++) {
_get_counter(adreno_dev, gpudev->ft_perf_counters[i].counter,
gpudev->ft_perf_counters[i].countable,
&adreno_ft_regs[j + (i * 2)],
&adreno_ft_regs[j + ((i * 2) + 1)]);
}
adreno_dev->fast_hang_detect = 1;
}
/**
* adreno_fault_detect_stop() - Release performance counters
* used for fast fault detection
* @adreno_dev: Pointer to an adreno_device structure
*
* Release the counters allocated in adreno_fault_detect_start
*/
void adreno_fault_detect_stop(struct adreno_device *adreno_dev)
{
struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);
unsigned int i, j = ARRAY_SIZE(adreno_ft_regs_default);
if (!test_bit(ADRENO_DEVICE_SOFT_FAULT_DETECT, &adreno_dev->priv))
return;
if (!adreno_dev->fast_hang_detect)
return;
for (i = 0; i < gpudev->ft_perf_counters_count; i++) {
_put_counter(adreno_dev, gpudev->ft_perf_counters[i].counter,
gpudev->ft_perf_counters[i].countable,
&adreno_ft_regs[j + (i * 2)],
&adreno_ft_regs[j + ((i * 2) + 1)]);
}
adreno_dev->fast_hang_detect = 0;
}
#define GMU_CM3_CFG_NONMASKINTR_SHIFT 9
/* Send an NMI to the GMU */
void adreno_gmu_send_nmi(struct adreno_device *adreno_dev)
{
u32 val;
/* Mask so there's no interrupt caused by NMI */
adreno_write_gmureg(adreno_dev,
ADRENO_REG_GMU_GMU2HOST_INTR_MASK, 0xFFFFFFFF);
/* Make sure the interrupt is masked before causing it */
wmb();
if (ADRENO_QUIRK(adreno_dev, ADRENO_QUIRK_HFI_USE_REG))
adreno_write_gmureg(adreno_dev,
ADRENO_REG_GMU_NMI_CONTROL_STATUS, 0);
adreno_read_gmureg(adreno_dev, ADRENO_REG_GMU_CM3_CFG, &val);
val |= 1 << GMU_CM3_CFG_NONMASKINTR_SHIFT;
adreno_write_gmureg(adreno_dev, ADRENO_REG_GMU_CM3_CFG, val);
/* Make sure the NMI is invoked before we proceed*/
wmb();
}
static void adreno_pwr_on_work(struct work_struct *work)
{
struct adreno_device *adreno_dev =
container_of(work, typeof(*adreno_dev), pwr_on_work);
struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
mutex_lock(&device->mutex);
kgsl_pwrctrl_change_state(device, KGSL_STATE_ACTIVE);
mutex_unlock(&device->mutex);
}
/*
* _soft_reset() - Soft reset GPU
* @adreno_dev: Pointer to adreno device
*
* Soft reset the GPU by doing a AHB write of value 1 to RBBM_SW_RESET
* register. This is used when we want to reset the GPU without
* turning off GFX power rail. The reset when asserted resets
* all the HW logic, restores GPU registers to default state and
* flushes out pending VBIF transactions.
*/
static int _soft_reset(struct adreno_device *adreno_dev)
{
struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);
unsigned int reg;
adreno_writereg(adreno_dev, ADRENO_REG_RBBM_SW_RESET_CMD, 1);
/*
* Do a dummy read to get a brief read cycle delay for the
* reset to take effect
*/
adreno_readreg(adreno_dev, ADRENO_REG_RBBM_SW_RESET_CMD, ®);
adreno_writereg(adreno_dev, ADRENO_REG_RBBM_SW_RESET_CMD, 0);
/* The SP/TP regulator gets turned off after a soft reset */
if (gpudev->regulator_enable)
gpudev->regulator_enable(adreno_dev);
return 0;
}
/**
* adreno_irqctrl() - Enables/disables the RBBM interrupt mask
* @adreno_dev: Pointer to an adreno_device
* @state: 1 for masked or 0 for unmasked
* Power: The caller of this function must make sure to use OOBs
* so that we know that the GPU is powered on
*/
void adreno_irqctrl(struct adreno_device *adreno_dev, int state)
{
struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);
unsigned int mask = state ? gpudev->irq->mask : 0;
adreno_writereg(adreno_dev, ADRENO_REG_RBBM_INT_0_MASK, mask);
}
/*
* adreno_hang_int_callback() - Isr for fatal interrupts that hang GPU
* @adreno_dev: Pointer to device
* @bit: Interrupt bit
*/
void adreno_hang_int_callback(struct adreno_device *adreno_dev, int bit)
{
dev_crit_ratelimited(KGSL_DEVICE(adreno_dev)->dev,
"MISC: GPU hang detected\n");
adreno_irqctrl(adreno_dev, 0);
/* Trigger a fault in the dispatcher - this will effect a restart */
adreno_set_gpu_fault(adreno_dev, ADRENO_HARD_FAULT);
adreno_dispatcher_schedule(KGSL_DEVICE(adreno_dev));
}
/*
* adreno_cp_callback() - CP interrupt handler
* @adreno_dev: Adreno device pointer
* @irq: irq number
*
* Handle the cp interrupt generated by GPU.
*/
void adreno_cp_callback(struct adreno_device *adreno_dev, int bit)
{
struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
adreno_dispatcher_schedule(device);
}
static irqreturn_t adreno_irq_handler(struct kgsl_device *device)
{
struct adreno_device *adreno_dev = ADRENO_DEVICE(device);
struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);
struct adreno_irq *irq_params = gpudev->irq;
irqreturn_t ret = IRQ_NONE;
unsigned int status = 0, fence = 0, fence_retries = 0, tmp, int_bit;
unsigned int shadow_status = 0;
int i;
u64 ts, ts1, ts2;
ts = gmu_core_dev_read_ao_counter(device);
atomic_inc(&adreno_dev->pending_irq_refcnt);
/* Ensure this increment is done before the IRQ status is updated */
smp_mb__after_atomic();
/*
* On A6xx, the GPU can power down once the INT_0_STATUS is read
* below. But there still might be some register reads required
* so force the GMU/GPU into KEEPALIVE mode until done with the ISR.
*/
if (gpudev->gpu_keepalive)
gpudev->gpu_keepalive(adreno_dev, true);
/*
* If the AHB fence is not in ALLOW mode when we receive an RBBM
* interrupt, something went wrong. This means that we cannot proceed
* since the IRQ status and clear registers are not accessible.
* This is usually harmless because the GMU will abort power collapse
* and change the fence back to ALLOW. Poll so that this can happen.
*/
if (gmu_core_isenabled(device)) {
adreno_readreg(adreno_dev,
ADRENO_REG_GMU_AO_AHB_FENCE_CTRL,
&fence);
while (fence != 0) {
ts1 = gmu_core_dev_read_ao_counter(device);
/* Wait for small time before trying again */
udelay(1);
adreno_readreg(adreno_dev,
ADRENO_REG_GMU_AO_AHB_FENCE_CTRL,
&fence);
if (fence_retries == FENCE_RETRY_MAX && fence != 0) {
ts2 = gmu_core_dev_read_ao_counter(device);
adreno_readreg(adreno_dev,
ADRENO_REG_GMU_RBBM_INT_UNMASKED_STATUS,
&shadow_status);
dev_crit_ratelimited(device->dev,
"Status=0x%x Unmasked status=0x%x Timestamps:%llx %llx %llx\n",
shadow_status & irq_params->mask,
shadow_status, ts, ts1, ts2);
adreno_set_gpu_fault(adreno_dev,
ADRENO_GMU_FAULT);
adreno_dispatcher_schedule(KGSL_DEVICE
(adreno_dev));
goto done;
}
fence_retries++;
}
}
adreno_readreg(adreno_dev, ADRENO_REG_RBBM_INT_0_STATUS, &status);
/*
* Clear all the interrupt bits but ADRENO_INT_RBBM_AHB_ERROR. Because
* even if we clear it here, it will stay high until it is cleared
* in its respective handler. Otherwise, the interrupt handler will
* fire again.
*/
int_bit = ADRENO_INT_BIT(adreno_dev, ADRENO_INT_RBBM_AHB_ERROR);
adreno_writereg(adreno_dev, ADRENO_REG_RBBM_INT_CLEAR_CMD,
status & ~int_bit);
/* Loop through all set interrupts and call respective handlers */
for (tmp = status; tmp != 0;) {
i = fls(tmp) - 1;
if (irq_params->funcs[i].func != NULL) {
if (irq_params->mask & BIT(i))
irq_params->funcs[i].func(adreno_dev, i);
} else
dev_crit_ratelimited(device->dev,
"Unhandled interrupt bit %x\n",
i);
ret = IRQ_HANDLED;
tmp &= ~BIT(i);
}
gpudev->irq_trace(adreno_dev, status);
/*
* Clear ADRENO_INT_RBBM_AHB_ERROR bit after this interrupt has been
* cleared in its respective handler
*/
if (status & int_bit)
adreno_writereg(adreno_dev, ADRENO_REG_RBBM_INT_CLEAR_CMD,
int_bit);
done:
/* Turn off the KEEPALIVE vote from earlier unless hard fault set */
if (gpudev->gpu_keepalive) {
/* If hard fault, then let snapshot turn off the keepalive */
if (!(adreno_gpu_fault(adreno_dev) & ADRENO_HARD_FAULT))
gpudev->gpu_keepalive(adreno_dev, false);
}
/* Make sure the regwrites are done before the decrement */
smp_mb__before_atomic();
atomic_dec(&adreno_dev->pending_irq_refcnt);
/* Ensure other CPUs see the decrement */
smp_mb__after_atomic();
return ret;
}
static inline bool _rev_match(unsigned int id, unsigned int entry)
{
return (entry == ANY_ID || entry == id);
}
static inline const struct adreno_gpu_core *_get_gpu_core(unsigned int chipid)
{
unsigned int core = ADRENO_CHIPID_CORE(chipid);
unsigned int major = ADRENO_CHIPID_MAJOR(chipid);
unsigned int minor = ADRENO_CHIPID_MINOR(chipid);
unsigned int patchid = ADRENO_CHIPID_PATCH(chipid);
int i;
for (i = 0; i < ARRAY_SIZE(adreno_gpulist); i++) {
if (core == adreno_gpulist[i]->core &&
_rev_match(major, adreno_gpulist[i]->major) &&
_rev_match(minor, adreno_gpulist[i]->minor) &&
_rev_match(patchid, adreno_gpulist[i]->patchid))
return adreno_gpulist[i];
}
return NULL;
}
static struct {
unsigned int quirk;
const char *prop;
} adreno_quirks[] = {
{ ADRENO_QUIRK_TWO_PASS_USE_WFI, "qcom,gpu-quirk-two-pass-use-wfi" },
{ ADRENO_QUIRK_IOMMU_SYNC, "qcom,gpu-quirk-iommu-sync" },
{ ADRENO_QUIRK_CRITICAL_PACKETS, "qcom,gpu-quirk-critical-packets" },
{ ADRENO_QUIRK_FAULT_DETECT_MASK, "qcom,gpu-quirk-fault-detect-mask" },
{ ADRENO_QUIRK_DISABLE_RB_DP2CLOCKGATING,
"qcom,gpu-quirk-dp2clockgating-disable" },
{ ADRENO_QUIRK_DISABLE_LMLOADKILL,
"qcom,gpu-quirk-lmloadkill-disable" },
{ ADRENO_QUIRK_HFI_USE_REG, "qcom,gpu-quirk-hfi-use-reg" },
{ ADRENO_QUIRK_SECVID_SET_ONCE, "qcom,gpu-quirk-secvid-set-once" },
{ ADRENO_QUIRK_LIMIT_UCHE_GBIF_RW,
"qcom,gpu-quirk-limit-uche-gbif-rw" },
{ ADRENO_QUIRK_MMU_SECURE_CB_ALT, "qcom,gpu-quirk-mmu-secure-cb-alt" },
{ ADRENO_QUIRK_CX_GDSC, "qcom,gpu-quirk-cx-gdsc" },
};
static struct device_node *
adreno_get_soc_hw_revision_node(struct adreno_device *adreno_dev,
struct platform_device *pdev)
{
struct device_node *node, *child;
unsigned int rev;
node = of_find_node_by_name(pdev->dev.of_node, "qcom,soc-hw-revisions");
if (node == NULL)
return NULL;
for_each_child_of_node(node, child) {
if (of_property_read_u32(child, "qcom,soc-hw-revision", &rev))
continue;
if (rev == adreno_dev->soc_hw_rev)
return child;
}
dev_warn(KGSL_DEVICE(adreno_dev)->dev,
"No matching SOC HW revision found for efused HW rev=%u\n",
adreno_dev->soc_hw_rev);
return NULL;
}
static void adreno_update_soc_hw_revision_quirks(
struct adreno_device *adreno_dev, struct platform_device *pdev)
{
struct device_node *node;
int i;
node = adreno_get_soc_hw_revision_node(adreno_dev, pdev);
if (node == NULL)
node = pdev->dev.of_node;
/* get chip id, fall back to parent if revision node does not have it */
if (of_property_read_u32(node, "qcom,chipid", &adreno_dev->chipid)) {
if (of_property_read_u32(pdev->dev.of_node,
"qcom,chipid", &adreno_dev->chipid)) {
dev_crit(KGSL_DEVICE(adreno_dev)->dev,
"No GPU chip ID was specified\n");
BUG();
return;
}
}
/* update quirk */
for (i = 0; i < ARRAY_SIZE(adreno_quirks); i++) {
if (of_property_read_bool(node, adreno_quirks[i].prop))
adreno_dev->quirks |= adreno_quirks[i].quirk;
}
}
static int adreno_identify_gpu(struct adreno_device *adreno_dev)
{
struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
const struct adreno_reg_offsets *reg_offsets;
struct adreno_gpudev *gpudev;
int i;
adreno_dev->gpucore = _get_gpu_core(adreno_dev->chipid);
if (adreno_dev->gpucore == NULL) {
dev_crit(&device->pdev->dev,
"Unknown GPU chip ID %8.8X\n", adreno_dev->chipid);
return -ENODEV;
}
/*
* Identify non-longer supported targets and spins and print a helpful
* message
*/
if (adreno_dev->gpucore->features & ADRENO_DEPRECATED) {
dev_err(&device->pdev->dev,
"Support for GPU %d.%d.%d.%d has been deprecated\n",
adreno_dev->gpucore->core,
adreno_dev->gpucore->major,
adreno_dev->gpucore->minor,
adreno_dev->gpucore->patchid);
return -ENODEV;
}
/*
* Some GPUs needs UCHE GMEM base address to be minimum 0x100000
* and 1MB aligned. Configure UCHE GMEM base based on GMEM size
* and align it one 1MB. This needs to be done based on GMEM size
* because setting it to minimum value 0x100000 will result in RB
* and UCHE GMEM range overlap for GPUs with GMEM size >1MB.
*/
if (!adreno_is_a650_family(adreno_dev))
adreno_dev->uche_gmem_base =
ALIGN(adreno_dev->gpucore->gmem_size, SZ_1M);
/*
* Initialize uninitialzed gpu registers, only needs to be done once
* Make all offsets that are not initialized to ADRENO_REG_UNUSED
*/
gpudev = ADRENO_GPU_DEVICE(adreno_dev);
reg_offsets = gpudev->reg_offsets;
for (i = 0; i < ADRENO_REG_REGISTER_MAX; i++) {
if (reg_offsets->offset_0 != i && !reg_offsets->offsets[i])
reg_offsets->offsets[i] = ADRENO_REG_UNUSED;
}
/* Do target specific identification */
if (gpudev->platform_setup != NULL)
gpudev->platform_setup(adreno_dev);
return 0;
}
static const struct platform_device_id adreno_id_table[] = {
{ DEVICE_3D0_NAME, (unsigned long) &device_3d0, },
{},
};
MODULE_DEVICE_TABLE(platform, adreno_id_table);
static const struct of_device_id adreno_match_table[] = {
{ .compatible = "qcom,kgsl-3d0", .data = &device_3d0 },
{}
};
static void adreno_of_get_ca_target_pwrlevel(struct adreno_device *adreno_dev,
struct device_node *node)
{
struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
unsigned int ca_target_pwrlevel = 1;
of_property_read_u32(node, "qcom,ca-target-pwrlevel",
&ca_target_pwrlevel);
if (ca_target_pwrlevel > device->pwrctrl.num_pwrlevels - 2)
ca_target_pwrlevel = 1;
device->pwrscale.ctxt_aware_target_pwrlevel = ca_target_pwrlevel;
}
static void adreno_of_get_ca_aware_properties(struct adreno_device *adreno_dev,
struct device_node *parent)
{
struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
struct kgsl_pwrscale *pwrscale = &device->pwrscale;
struct device_node *node, *child;
unsigned int bin = 0;
pwrscale->ctxt_aware_enable =
of_property_read_bool(parent, "qcom,enable-ca-jump");
if (pwrscale->ctxt_aware_enable) {
if (of_property_read_u32(parent, "qcom,ca-busy-penalty",
&pwrscale->ctxt_aware_busy_penalty))
pwrscale->ctxt_aware_busy_penalty = 12000;
if (is_gpu_overclocked > 0) {
node = of_find_node_by_name(parent, "qcom,gpu-pwrlevel-binsoc");
if (node == NULL)
node = of_find_node_by_name(parent, "qcom,gpu-pwrlevel-bins");
} else {
node = of_find_node_by_name(parent, "qcom,gpu-pwrlevel-bins");
}
if (node == NULL) {
adreno_of_get_ca_target_pwrlevel(adreno_dev, parent);
return;
}
for_each_child_of_node(node, child) {
if (of_property_read_u32(child, "qcom,speed-bin", &bin))
continue;
if (bin == adreno_dev->speed_bin) {
adreno_of_get_ca_target_pwrlevel(adreno_dev,
child);
return;
}
}
pwrscale->ctxt_aware_target_pwrlevel = 1;
}
}
static int adreno_of_parse_pwrlevels(struct adreno_device *adreno_dev,
struct device_node *node)
{
struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
struct kgsl_pwrctrl *pwr = &device->pwrctrl;
struct device_node *child;
int ret;
/* ADD the GPU OPP table if we define it */
if (of_find_property(device->pdev->dev.of_node,
"operating-points-v2", NULL)) {
ret = dev_pm_opp_of_add_table(&device->pdev->dev);
if (ret) {
dev_err(device->dev,
"Unable to set the GPU OPP table: %d\n", ret);
return ret;
}
}
pwr->num_pwrlevels = 0;
for_each_child_of_node(node, child) {
unsigned int index;
struct kgsl_pwrlevel *level;
if (adreno_of_read_property(device->dev, child, "reg", &index))
return -EINVAL;
if (index >= KGSL_MAX_PWRLEVELS) {
dev_err(device->dev,
"%pOF: Pwrlevel index %d is out of range\n",
child, index);
continue;
}
if (index >= pwr->num_pwrlevels)
pwr->num_pwrlevels = index + 1;
level = &pwr->pwrlevels[index];
if (adreno_of_read_property(device->dev, child, "qcom,gpu-freq",
&level->gpu_freq))
return -EINVAL;
of_property_read_u32(child, "qcom,acd-level",
&level->acd_level);
ret = kgsl_of_property_read_ddrtype(child,
"qcom,bus-freq", &level->bus_freq);
if (ret) {
dev_err(device->dev,
"%pOF: Couldn't read the bus frequency for power level %d\n",
child, index);
return ret;
}
level->bus_min = level->bus_freq;
kgsl_of_property_read_ddrtype(child,
"qcom,bus-min", &level->bus_min);
level->bus_max = level->bus_freq;
kgsl_of_property_read_ddrtype(child,
"qcom,bus-max", &level->bus_max);
}
return 0;
}
static void adreno_of_get_bimc_iface_clk(struct adreno_device *adreno_dev,
struct device_node *node)
{
struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
struct kgsl_pwrctrl *pwr = &device->pwrctrl;
/* Getting gfx-bimc-interface-clk frequency */
if (!of_property_read_u32(node, "qcom,gpu-bimc-interface-clk-freq",
&pwr->gpu_bimc_int_clk_freq)) {
pwr->gpu_bimc_int_clk = devm_clk_get(&device->pdev->dev,
"bimc_gpu_clk");
if (IS_ERR_OR_NULL(pwr->gpu_bimc_int_clk)) {
dev_err(&device->pdev->dev,
"dt: Couldn't get bimc_gpu_clk (%d)\n",
PTR_ERR(pwr->gpu_bimc_int_clk));
pwr->gpu_bimc_int_clk = NULL;
}
}
}
static void adreno_of_get_initial_pwrlevel(struct adreno_device *adreno_dev,
struct device_node *node)
{
struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
struct kgsl_pwrctrl *pwr = &device->pwrctrl;
int init_level = 1;
of_property_read_u32(node, "qcom,initial-pwrlevel", &init_level);
if (init_level < 0 || init_level > pwr->num_pwrlevels)
init_level = 1;
pwr->active_pwrlevel = init_level;
}
static void adreno_of_get_limits(struct adreno_device *adreno_dev,
struct device_node *node)
{
struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
struct kgsl_pwrctrl *pwrctrl = &device->pwrctrl;
unsigned int throttle_level;
if (!ADRENO_FEATURE(adreno_dev, ADRENO_LM) || of_property_read_u32(node,
"qcom,throttle-pwrlevel", &throttle_level))
return;
throttle_level = min(throttle_level, pwrctrl->num_pwrlevels - 1);
pwrctrl->throttle_mask = GENMASK(pwrctrl->num_pwrlevels - 1,
pwrctrl->num_pwrlevels - 1 - throttle_level);
set_bit(ADRENO_LM_CTRL, &adreno_dev->pwrctrl_flag);
}
static int adreno_of_get_legacy_pwrlevels(struct adreno_device *adreno_dev,
struct device_node *parent)
{
struct device_node *node;
int ret;
node = of_find_node_by_name(parent, "qcom,gpu-pwrlevels");
if (node == NULL) {
dev_err(KGSL_DEVICE(adreno_dev)->dev,
"Unable to find 'qcom,gpu-pwrlevels'\n");
return -EINVAL;
}
ret = adreno_of_parse_pwrlevels(adreno_dev, node);
if (ret)
return ret;
adreno_of_get_initial_pwrlevel(adreno_dev, parent);