forked from MiSTer-devel/MultiComp_MiSTer
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MultiComp-lite.srf
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MultiComp-lite.srf
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{ "" "" "" "Port \"extclk\" on the entity instantiation of \"cyclonev_pll\" is connected to a signal of width 1. The formal width of the signal in the module is 2. The extra bits will be left dangling without any fan-out logic." { } { } 0 12030 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "Ignored filter at sys_top.sdc(15): vip\|output_inst\|vid_clk could not be matched with a net" { } { } 0 332174 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "Ignored create_generated_clock at sys_top.sdc(14): Argument <targets> is an empty collection" { } { } 0 332049 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "Ignored filter at sys_top.sdc(32): VID_CLK could not be matched with a clock" { } { } 0 332174 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "altera_pll.v" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "altera_cyclonev_pll.v" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "altera_pll_reconfig_core.v" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "RST port on the PLL is not properly connected" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}