- Introduce combinatorial procedural blocks
always_comb. (video 1) - Explain how to define a literal value in system verilog. (video 2)
- Explain how to use if statements and case statements in a procedural block. (video 3)
- Using an
always_combblock make the outputqbe the bitwise OR of inputsa,b,c, andd.
- Assign the output
qto be42using a binary literal.
- Using a bitwise NOT operation -- create a MUX where all the odd signals are selected an inverted version of the corresponding input is sent to the output, apart from input
7which is always42. See the diagram above.