System clock configuration issue in STM32H573I-DK OEMiROT_Boot sample project

[CuriousSaman]

Hello,
It seems that there is an issue in the PLL1M configuration in Projects/STM32H573I-DK/Applications/ROT/OEMiROT_Boot/Src/system_stm32h5xx.c file SetSysClock() function. RCC_PLL1CFGR_PLL1M_Pos was used as the value.

STM32CubeH5/Projects/STM32H573I-DK/Applications/ROT/OEMiROT_Boot/Src/system_stm32h5xx.c

Line 298 in 3d723b2

MODIFY_REG(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1M, RCC_PLL1CFGR_PLL1M_Pos << RCC_PLL1CFGR_PLL1M_Pos);

Also, I think the values for reaching 250MHz should be like this:

• PLLM: 4 (RCC_PLL1CFGR_PLL1M_Pos will expand to 8)
• PLLN: 31 (it's 60 in the current code)
• PLLP: 2
• PLLQ: 2
• PLLR: 2
• PLLFRACN: 2048

Screenshot

Furthermore, it might be better to use:
RCC_PLL1_VCORANGE_WIDE instead of RCC_PLL1VCOWIDE
RCC_PLL1_VCIRANGE_2 instead of RCC_PLL1CFGR_PLL1SRC_1
RCC_SYSCLKSOURCE_PLLCLK instead of (RCC_CFGR1_SW_1 | RCC_CFGR1_SW_0)

STM32CubeH5/Projects/STM32H573I-DK/Applications/ROT/OEMiROT_Boot/Src/system_stm32h5xx.c

Line 297 in 3d723b2

MODIFY_REG(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1VCOSEL, RCC_PLL1VCOWIDE << RCC_PLL1CFGR_PLL1VCOSEL_Pos);

[HBOSTM]

ST Internal Reference: 158775