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stm32h7xx_hal_rcc.h
7973 lines (7155 loc) · 477 KB
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stm32h7xx_hal_rcc.h
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/**
******************************************************************************
* @file stm32h7xx_hal_rcc.h
* @author MCD Application Team
* @brief Header file of RCC HAL module.
******************************************************************************
* @attention
*
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32H7xx_HAL_RCC_H
#define STM32H7xx_HAL_RCC_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32h7xx_hal_def.h"
/** @addtogroup STM32H7xx_HAL_Driver
* @{
*/
/** @addtogroup RCC
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup RCC_Exported_Types RCC Exported Types
* @{
*/
/**
* @brief RCC PLL configuration structure definition
*/
typedef struct
{
uint32_t PLLState; /*!< The new state of the PLL.
This parameter can be a value of @ref RCC_PLL_Config */
uint32_t PLLSource; /*!< RCC_PLLSource: PLL entry clock source.
This parameter must be a value of @ref RCC_PLL_Clock_Source */
uint32_t PLLM; /*!< PLLM: Division factor for PLL VCO input clock.
This parameter must be a number between Min_Data = 1 and Max_Data = 63 */
uint32_t PLLN; /*!< PLLN: Multiplication factor for PLL VCO output clock.
This parameter must be a number between Min_Data = 4 and Max_Data = 512
or between Min_Data = 8 and Max_Data = 420(*)
(*) : For stm32h7a3xx and stm32h7b3xx family lines. */
uint32_t PLLP; /*!< PLLP: Division factor for system clock.
This parameter must be a number between Min_Data = 2 and Max_Data = 128
odd division factors are not allowed */
uint32_t PLLQ; /*!< PLLQ: Division factor for peripheral clocks.
This parameter must be a number between Min_Data = 1 and Max_Data = 128 */
uint32_t PLLR; /*!< PLLR: Division factor for peripheral clocks.
This parameter must be a number between Min_Data = 1 and Max_Data = 128 */
uint32_t PLLRGE; /*!<PLLRGE: PLL1 clock Input range
This parameter must be a value of @ref RCC_PLL1_VCI_Range */
uint32_t PLLVCOSEL; /*!<PLLVCOSEL: PLL1 clock Output range
This parameter must be a value of @ref RCC_PLL1_VCO_Range */
uint32_t PLLFRACN; /*!<PLLFRACN: Specifies Fractional Part Of The Multiplication Factor for
PLL1 VCO It should be a value between 0 and 8191 */
}RCC_PLLInitTypeDef;
/**
* @brief RCC Internal/External Oscillator (HSE, HSI, CSI, LSE and LSI) configuration structure definition
*/
typedef struct
{
uint32_t OscillatorType; /*!< The oscillators to be configured.
This parameter can be a value of @ref RCC_Oscillator_Type */
uint32_t HSEState; /*!< The new state of the HSE.
This parameter can be a value of @ref RCC_HSE_Config */
uint32_t LSEState; /*!< The new state of the LSE.
This parameter can be a value of @ref RCC_LSE_Config */
uint32_t HSIState; /*!< The new state of the HSI.
This parameter can be a value of @ref RCC_HSI_Config */
uint32_t HSICalibrationValue; /*!< The calibration trimming value.
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x3F for STM32H7 rev.Y
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F for STM32H7 rev.B and above */
uint32_t LSIState; /*!< The new state of the LSI.
This parameter can be a value of @ref RCC_LSI_Config */
uint32_t HSI48State; /*!< The new state of the HSI48.
This parameter can be a value of @ref RCC_HSI48_Config */
uint32_t CSIState; /*!< The new state of the CSI.
This parameter can be a value of @ref RCC_CSI_Config */
uint32_t CSICalibrationValue; /*!< The calibration trimming value.
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F for STM32H7 rev.Y
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x3F for STM32H7 rev.B and above */
RCC_PLLInitTypeDef PLL; /*!< PLL structure parameters */
}RCC_OscInitTypeDef;
/**
* @brief RCC System, AHB and APB busses clock configuration structure definition
*/
typedef struct
{
uint32_t ClockType; /*!< The clock to be configured.
This parameter can be a value of @ref RCC_System_Clock_Type */
uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock.
This parameter can be a value of @ref RCC_System_Clock_Source */
uint32_t SYSCLKDivider; /*!< The system clock divider. This parameter can be
a value of @ref RCC_SYS_Clock_Source */
uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
This parameter can be a value of @ref RCC_HCLK_Clock_Source */
uint32_t APB3CLKDivider; /*!< The APB3 clock (D1PCLK1) divider. This clock is derived from the AHB clock (HCLK).
This parameter can be a value of @ref RCC_APB3_Clock_Source */
uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
This parameter can be a value of @ref RCC_APB1_Clock_Source */
uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
This parameter can be a value of @ref RCC_APB2_Clock_Source */
uint32_t APB4CLKDivider; /*!< The APB4 clock (D3PCLK1) divider. This clock is derived from the AHB clock (HCLK).
This parameter can be a value of @ref RCC_APB4_Clock_Source */
}RCC_ClkInitTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup RCC_Exported_Constants RCC Exported Constants
* @{
*/
/** @defgroup RCC_Oscillator_Type RCC Oscillator Type
* @{
*/
#define RCC_OSCILLATORTYPE_NONE (0x00000000U)
#define RCC_OSCILLATORTYPE_HSE (0x00000001U)
#define RCC_OSCILLATORTYPE_HSI (0x00000002U)
#define RCC_OSCILLATORTYPE_LSE (0x00000004U)
#define RCC_OSCILLATORTYPE_LSI (0x00000008U)
#define RCC_OSCILLATORTYPE_CSI (0x00000010U)
#define RCC_OSCILLATORTYPE_HSI48 (0x00000020U)
/**
* @}
*/
/** @defgroup RCC_HSE_Config RCC HSE Config
* @{
*/
#define RCC_HSE_OFF (0x00000000U)
#define RCC_HSE_ON RCC_CR_HSEON
#define RCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON))
#if defined(RCC_CR_HSEEXT)
#define RCC_HSE_BYPASS_DIGITAL ((uint32_t)(RCC_CR_HSEEXT | RCC_CR_HSEBYP | RCC_CR_HSEON))
#endif /* RCC_CR_HSEEXT */
/**
* @}
*/
/** @defgroup RCC_LSE_Config RCC LSE Config
* @{
*/
#define RCC_LSE_OFF (0x00000000U)
#define RCC_LSE_ON RCC_BDCR_LSEON
#define RCC_LSE_BYPASS ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON))
#if defined(RCC_BDCR_LSEEXT)
#define RCC_LSE_BYPASS_DIGITAL ((uint32_t)(RCC_BDCR_LSEEXT | RCC_BDCR_LSEBYP | RCC_BDCR_LSEON))
#endif /* RCC_BDCR_LSEEXT */
/**
* @}
*/
/** @defgroup RCC_HSI_Config RCC HSI Config
* @{
*/
#define RCC_HSI_OFF (0x00000000U) /*!< HSI clock deactivation */
#define RCC_HSI_ON RCC_CR_HSION /*!< HSI clock activation */
#define RCC_HSI_DIV1 (RCC_CR_HSIDIV_1 | RCC_CR_HSION) /*!< HSI_DIV1 clock activation */
#define RCC_HSI_DIV2 (RCC_CR_HSIDIV_2 | RCC_CR_HSION) /*!< HSI_DIV2 clock activation */
#define RCC_HSI_DIV4 (RCC_CR_HSIDIV_4 | RCC_CR_HSION) /*!< HSI_DIV4 clock activation */
#define RCC_HSI_DIV8 (RCC_CR_HSIDIV | RCC_CR_HSION) /*!< HSI_DIV8 clock activation */
#if defined(RCC_HSICFGR_HSITRIM_6)
#define RCC_HSICALIBRATION_DEFAULT (0x40U) /* Default HSI calibration trimming value, for STM32H7 rev.V and above */
#else
#define RCC_HSICALIBRATION_DEFAULT (0x20U) /* Default HSI calibration trimming value, for STM32H7 rev.Y */
#endif
/**
* @}
*/
/** @defgroup RCC_HSI48_Config RCC HSI48 Config
* @{
*/
#define RCC_HSI48_OFF ((uint8_t)0x00)
#define RCC_HSI48_ON ((uint8_t)0x01)
/**
* @}
*/
/** @defgroup RCC_LSI_Config RCC LSI Config
* @{
*/
#define RCC_LSI_OFF (0x00000000U)
#define RCC_LSI_ON RCC_CSR_LSION
/**
* @}
*/
/** @defgroup RCC_CSI_Config RCC CSI Config
* @{
*/
#define RCC_CSI_OFF (0x00000000U)
#define RCC_CSI_ON RCC_CR_CSION
#if defined(RCC_CSICFGR_CSITRIM_5)
#define RCC_CSICALIBRATION_DEFAULT (0x20U) /* Default CSI calibration trimming value */
#else
#define RCC_CSICALIBRATION_DEFAULT (0x10U) /* Default CSI calibration trimming value */
#endif /* RCC_CSICFGR_CSITRIM_5 */
/**
* @}
*/
/** @defgroup RCC_PLL_Config RCC PLL Config
* @{
*/
#define RCC_PLL_NONE (0x00000000U)
#define RCC_PLL_OFF (0x00000001U)
#define RCC_PLL_ON (0x00000002U)
/**
* @}
*/
/** @defgroup RCC_PLL_Clock_Source RCC PLL Clock Source
* @{
*/
#define RCC_PLLSOURCE_HSI (0x00000000U)
#define RCC_PLLSOURCE_CSI (0x00000001U)
#define RCC_PLLSOURCE_HSE (0x00000002U)
#define RCC_PLLSOURCE_NONE (0x00000003U)
/**
* @}
*/
/** @defgroup RCC_PLL_Clock_Output RCC PLL Clock Output
* @{
*/
#define RCC_PLL1_DIVP RCC_PLLCFGR_DIVP1EN
#define RCC_PLL1_DIVQ RCC_PLLCFGR_DIVQ1EN
#define RCC_PLL1_DIVR RCC_PLLCFGR_DIVR1EN
/**
* @}
*/
/** @defgroup RCC_PLL1_VCI_Range RCC PLL1 VCI Range
* @{
*/
#define RCC_PLL1VCIRANGE_0 RCC_PLLCFGR_PLL1RGE_0 /*!< Clock range frequency between 1 and 2 MHz */
#define RCC_PLL1VCIRANGE_1 RCC_PLLCFGR_PLL1RGE_1 /*!< Clock range frequency between 2 and 4 MHz */
#define RCC_PLL1VCIRANGE_2 RCC_PLLCFGR_PLL1RGE_2 /*!< Clock range frequency between 4 and 8 MHz */
#define RCC_PLL1VCIRANGE_3 RCC_PLLCFGR_PLL1RGE_3 /*!< Clock range frequency between 8 and 16 MHz */
/**
* @}
*/
/** @defgroup RCC_PLL1_VCO_Range RCC PLL1 VCO Range
* @{
*/
#define RCC_PLL1VCOWIDE (0x00000000U)
#define RCC_PLL1VCOMEDIUM RCC_PLLCFGR_PLL1VCOSEL
/**
* @}
*/
/** @defgroup RCC_System_Clock_Type RCC System Clock Type
* @{
*/
#define RCC_CLOCKTYPE_SYSCLK (0x00000001U)
#define RCC_CLOCKTYPE_HCLK (0x00000002U)
#define RCC_CLOCKTYPE_D1PCLK1 (0x00000004U)
#define RCC_CLOCKTYPE_PCLK1 (0x00000008U)
#define RCC_CLOCKTYPE_PCLK2 (0x00000010U)
#define RCC_CLOCKTYPE_D3PCLK1 (0x00000020U)
/**
* @}
*/
/** @defgroup RCC_System_Clock_Source RCC System Clock Source
* @{
*/
#define RCC_SYSCLKSOURCE_CSI RCC_CFGR_SW_CSI
#define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI
#define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE
#define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL1
/**
* @}
*/
/** @defgroup RCC_System_Clock_Source_Status System Clock Source Status
* @{
*/
#define RCC_SYSCLKSOURCE_STATUS_CSI RCC_CFGR_SWS_CSI /*!< CSI used as system clock */
#define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */
#define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */
#define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL1 /*!< PLL1 used as system clock */
/**
* @}
*/
/** @defgroup RCC_SYS_Clock_Source RCC SYS Clock Source
* @{
*/
#if defined(RCC_D1CFGR_D1CPRE_DIV1)
#define RCC_SYSCLK_DIV1 RCC_D1CFGR_D1CPRE_DIV1
#define RCC_SYSCLK_DIV2 RCC_D1CFGR_D1CPRE_DIV2
#define RCC_SYSCLK_DIV4 RCC_D1CFGR_D1CPRE_DIV4
#define RCC_SYSCLK_DIV8 RCC_D1CFGR_D1CPRE_DIV8
#define RCC_SYSCLK_DIV16 RCC_D1CFGR_D1CPRE_DIV16
#define RCC_SYSCLK_DIV64 RCC_D1CFGR_D1CPRE_DIV64
#define RCC_SYSCLK_DIV128 RCC_D1CFGR_D1CPRE_DIV128
#define RCC_SYSCLK_DIV256 RCC_D1CFGR_D1CPRE_DIV256
#define RCC_SYSCLK_DIV512 RCC_D1CFGR_D1CPRE_DIV512
#else
#define RCC_SYSCLK_DIV1 RCC_CDCFGR1_CDCPRE_DIV1
#define RCC_SYSCLK_DIV2 RCC_CDCFGR1_CDCPRE_DIV2
#define RCC_SYSCLK_DIV4 RCC_CDCFGR1_CDCPRE_DIV4
#define RCC_SYSCLK_DIV8 RCC_CDCFGR1_CDCPRE_DIV8
#define RCC_SYSCLK_DIV16 RCC_CDCFGR1_CDCPRE_DIV16
#define RCC_SYSCLK_DIV64 RCC_CDCFGR1_CDCPRE_DIV64
#define RCC_SYSCLK_DIV128 RCC_CDCFGR1_CDCPRE_DIV128
#define RCC_SYSCLK_DIV256 RCC_CDCFGR1_CDCPRE_DIV256
#define RCC_SYSCLK_DIV512 RCC_CDCFGR1_CDCPRE_DIV512
#endif
/**
* @}
*/
/** @defgroup RCC_HCLK_Clock_Source RCC HCLK Clock Source
* @{
*/
#if defined(RCC_D1CFGR_HPRE_DIV1)
#define RCC_HCLK_DIV1 RCC_D1CFGR_HPRE_DIV1
#define RCC_HCLK_DIV2 RCC_D1CFGR_HPRE_DIV2
#define RCC_HCLK_DIV4 RCC_D1CFGR_HPRE_DIV4
#define RCC_HCLK_DIV8 RCC_D1CFGR_HPRE_DIV8
#define RCC_HCLK_DIV16 RCC_D1CFGR_HPRE_DIV16
#define RCC_HCLK_DIV64 RCC_D1CFGR_HPRE_DIV64
#define RCC_HCLK_DIV128 RCC_D1CFGR_HPRE_DIV128
#define RCC_HCLK_DIV256 RCC_D1CFGR_HPRE_DIV256
#define RCC_HCLK_DIV512 RCC_D1CFGR_HPRE_DIV512
#else
#define RCC_HCLK_DIV1 RCC_CDCFGR1_HPRE_DIV1
#define RCC_HCLK_DIV2 RCC_CDCFGR1_HPRE_DIV2
#define RCC_HCLK_DIV4 RCC_CDCFGR1_HPRE_DIV4
#define RCC_HCLK_DIV8 RCC_CDCFGR1_HPRE_DIV8
#define RCC_HCLK_DIV16 RCC_CDCFGR1_HPRE_DIV16
#define RCC_HCLK_DIV64 RCC_CDCFGR1_HPRE_DIV64
#define RCC_HCLK_DIV128 RCC_CDCFGR1_HPRE_DIV128
#define RCC_HCLK_DIV256 RCC_CDCFGR1_HPRE_DIV256
#define RCC_HCLK_DIV512 RCC_CDCFGR1_HPRE_DIV512
#endif
/**
* @}
*/
/** @defgroup RCC_APB3_Clock_Source RCC APB3 Clock Source
* @{
*/
#if defined (RCC_D1CFGR_D1PPRE_DIV1)
#define RCC_APB3_DIV1 RCC_D1CFGR_D1PPRE_DIV1
#define RCC_APB3_DIV2 RCC_D1CFGR_D1PPRE_DIV2
#define RCC_APB3_DIV4 RCC_D1CFGR_D1PPRE_DIV4
#define RCC_APB3_DIV8 RCC_D1CFGR_D1PPRE_DIV8
#define RCC_APB3_DIV16 RCC_D1CFGR_D1PPRE_DIV16
#else
#define RCC_APB3_DIV1 RCC_CDCFGR1_CDPPRE_DIV1
#define RCC_APB3_DIV2 RCC_CDCFGR1_CDPPRE_DIV2
#define RCC_APB3_DIV4 RCC_CDCFGR1_CDPPRE_DIV4
#define RCC_APB3_DIV8 RCC_CDCFGR1_CDPPRE_DIV8
#define RCC_APB3_DIV16 RCC_CDCFGR1_CDPPRE_DIV16
#endif
/**
* @}
*/
/** @defgroup RCC_APB1_Clock_Source RCC APB1 Clock Source
* @{
*/
#if defined (RCC_D2CFGR_D2PPRE1_DIV1)
#define RCC_APB1_DIV1 RCC_D2CFGR_D2PPRE1_DIV1
#define RCC_APB1_DIV2 RCC_D2CFGR_D2PPRE1_DIV2
#define RCC_APB1_DIV4 RCC_D2CFGR_D2PPRE1_DIV4
#define RCC_APB1_DIV8 RCC_D2CFGR_D2PPRE1_DIV8
#define RCC_APB1_DIV16 RCC_D2CFGR_D2PPRE1_DIV16
#else
#define RCC_APB1_DIV1 RCC_CDCFGR2_CDPPRE1_DIV1
#define RCC_APB1_DIV2 RCC_CDCFGR2_CDPPRE1_DIV2
#define RCC_APB1_DIV4 RCC_CDCFGR2_CDPPRE1_DIV4
#define RCC_APB1_DIV8 RCC_CDCFGR2_CDPPRE1_DIV8
#define RCC_APB1_DIV16 RCC_CDCFGR2_CDPPRE1_DIV16
#endif
/**
* @}
*/
/** @defgroup RCC_APB2_Clock_Source RCC APB2 Clock Source
* @{
*/
#if defined (RCC_D2CFGR_D2PPRE2_DIV1)
#define RCC_APB2_DIV1 RCC_D2CFGR_D2PPRE2_DIV1
#define RCC_APB2_DIV2 RCC_D2CFGR_D2PPRE2_DIV2
#define RCC_APB2_DIV4 RCC_D2CFGR_D2PPRE2_DIV4
#define RCC_APB2_DIV8 RCC_D2CFGR_D2PPRE2_DIV8
#define RCC_APB2_DIV16 RCC_D2CFGR_D2PPRE2_DIV16
#else
#define RCC_APB2_DIV1 RCC_CDCFGR2_CDPPRE2_DIV1
#define RCC_APB2_DIV2 RCC_CDCFGR2_CDPPRE2_DIV2
#define RCC_APB2_DIV4 RCC_CDCFGR2_CDPPRE2_DIV4
#define RCC_APB2_DIV8 RCC_CDCFGR2_CDPPRE2_DIV8
#define RCC_APB2_DIV16 RCC_CDCFGR2_CDPPRE2_DIV16
#endif
/**
* @}
*/
/** @defgroup RCC_APB4_Clock_Source RCC APB4 Clock Source
* @{
*/
#if defined(RCC_D3CFGR_D3PPRE_DIV1)
#define RCC_APB4_DIV1 RCC_D3CFGR_D3PPRE_DIV1
#define RCC_APB4_DIV2 RCC_D3CFGR_D3PPRE_DIV2
#define RCC_APB4_DIV4 RCC_D3CFGR_D3PPRE_DIV4
#define RCC_APB4_DIV8 RCC_D3CFGR_D3PPRE_DIV8
#define RCC_APB4_DIV16 RCC_D3CFGR_D3PPRE_DIV16
#else
#define RCC_APB4_DIV1 RCC_SRDCFGR_SRDPPRE_DIV1
#define RCC_APB4_DIV2 RCC_SRDCFGR_SRDPPRE_DIV2
#define RCC_APB4_DIV4 RCC_SRDCFGR_SRDPPRE_DIV4
#define RCC_APB4_DIV8 RCC_SRDCFGR_SRDPPRE_DIV8
#define RCC_APB4_DIV16 RCC_SRDCFGR_SRDPPRE_DIV16
#endif
/**
* @}
*/
/** @defgroup RCC_RTC_Clock_Source RCC RTC Clock Source
* @{
*/
#define RCC_RTCCLKSOURCE_NO_CLK (0x00000000U)
#define RCC_RTCCLKSOURCE_LSE (0x00000100U)
#define RCC_RTCCLKSOURCE_LSI (0x00000200U)
#define RCC_RTCCLKSOURCE_HSE_DIV2 (0x00002300U)
#define RCC_RTCCLKSOURCE_HSE_DIV3 (0x00003300U)
#define RCC_RTCCLKSOURCE_HSE_DIV4 (0x00004300U)
#define RCC_RTCCLKSOURCE_HSE_DIV5 (0x00005300U)
#define RCC_RTCCLKSOURCE_HSE_DIV6 (0x00006300U)
#define RCC_RTCCLKSOURCE_HSE_DIV7 (0x00007300U)
#define RCC_RTCCLKSOURCE_HSE_DIV8 (0x00008300U)
#define RCC_RTCCLKSOURCE_HSE_DIV9 (0x00009300U)
#define RCC_RTCCLKSOURCE_HSE_DIV10 (0x0000A300U)
#define RCC_RTCCLKSOURCE_HSE_DIV11 (0x0000B300U)
#define RCC_RTCCLKSOURCE_HSE_DIV12 (0x0000C300U)
#define RCC_RTCCLKSOURCE_HSE_DIV13 (0x0000D300U)
#define RCC_RTCCLKSOURCE_HSE_DIV14 (0x0000E300U)
#define RCC_RTCCLKSOURCE_HSE_DIV15 (0x0000F300U)
#define RCC_RTCCLKSOURCE_HSE_DIV16 (0x00010300U)
#define RCC_RTCCLKSOURCE_HSE_DIV17 (0x00011300U)
#define RCC_RTCCLKSOURCE_HSE_DIV18 (0x00012300U)
#define RCC_RTCCLKSOURCE_HSE_DIV19 (0x00013300U)
#define RCC_RTCCLKSOURCE_HSE_DIV20 (0x00014300U)
#define RCC_RTCCLKSOURCE_HSE_DIV21 (0x00015300U)
#define RCC_RTCCLKSOURCE_HSE_DIV22 (0x00016300U)
#define RCC_RTCCLKSOURCE_HSE_DIV23 (0x00017300U)
#define RCC_RTCCLKSOURCE_HSE_DIV24 (0x00018300U)
#define RCC_RTCCLKSOURCE_HSE_DIV25 (0x00019300U)
#define RCC_RTCCLKSOURCE_HSE_DIV26 (0x0001A300U)
#define RCC_RTCCLKSOURCE_HSE_DIV27 (0x0001B300U)
#define RCC_RTCCLKSOURCE_HSE_DIV28 (0x0001C300U)
#define RCC_RTCCLKSOURCE_HSE_DIV29 (0x0001D300U)
#define RCC_RTCCLKSOURCE_HSE_DIV30 (0x0001E300U)
#define RCC_RTCCLKSOURCE_HSE_DIV31 (0x0001F300U)
#define RCC_RTCCLKSOURCE_HSE_DIV32 (0x00020300U)
#define RCC_RTCCLKSOURCE_HSE_DIV33 (0x00021300U)
#define RCC_RTCCLKSOURCE_HSE_DIV34 (0x00022300U)
#define RCC_RTCCLKSOURCE_HSE_DIV35 (0x00023300U)
#define RCC_RTCCLKSOURCE_HSE_DIV36 (0x00024300U)
#define RCC_RTCCLKSOURCE_HSE_DIV37 (0x00025300U)
#define RCC_RTCCLKSOURCE_HSE_DIV38 (0x00026300U)
#define RCC_RTCCLKSOURCE_HSE_DIV39 (0x00027300U)
#define RCC_RTCCLKSOURCE_HSE_DIV40 (0x00028300U)
#define RCC_RTCCLKSOURCE_HSE_DIV41 (0x00029300U)
#define RCC_RTCCLKSOURCE_HSE_DIV42 (0x0002A300U)
#define RCC_RTCCLKSOURCE_HSE_DIV43 (0x0002B300U)
#define RCC_RTCCLKSOURCE_HSE_DIV44 (0x0002C300U)
#define RCC_RTCCLKSOURCE_HSE_DIV45 (0x0002D300U)
#define RCC_RTCCLKSOURCE_HSE_DIV46 (0x0002E300U)
#define RCC_RTCCLKSOURCE_HSE_DIV47 (0x0002F300U)
#define RCC_RTCCLKSOURCE_HSE_DIV48 (0x00030300U)
#define RCC_RTCCLKSOURCE_HSE_DIV49 (0x00031300U)
#define RCC_RTCCLKSOURCE_HSE_DIV50 (0x00032300U)
#define RCC_RTCCLKSOURCE_HSE_DIV51 (0x00033300U)
#define RCC_RTCCLKSOURCE_HSE_DIV52 (0x00034300U)
#define RCC_RTCCLKSOURCE_HSE_DIV53 (0x00035300U)
#define RCC_RTCCLKSOURCE_HSE_DIV54 (0x00036300U)
#define RCC_RTCCLKSOURCE_HSE_DIV55 (0x00037300U)
#define RCC_RTCCLKSOURCE_HSE_DIV56 (0x00038300U)
#define RCC_RTCCLKSOURCE_HSE_DIV57 (0x00039300U)
#define RCC_RTCCLKSOURCE_HSE_DIV58 (0x0003A300U)
#define RCC_RTCCLKSOURCE_HSE_DIV59 (0x0003B300U)
#define RCC_RTCCLKSOURCE_HSE_DIV60 (0x0003C300U)
#define RCC_RTCCLKSOURCE_HSE_DIV61 (0x0003D300U)
#define RCC_RTCCLKSOURCE_HSE_DIV62 (0x0003E300U)
#define RCC_RTCCLKSOURCE_HSE_DIV63 (0x0003F300U)
/**
* @}
*/
/** @defgroup RCC_MCO_Index RCC MCO Index
* @{
*/
#define RCC_MCO1 (0x00000000U)
#define RCC_MCO2 (0x00000001U)
/**
* @}
*/
/** @defgroup RCC_MCO1_Clock_Source RCC MCO1 Clock Source
* @{
*/
#define RCC_MCO1SOURCE_HSI (0x00000000U)
#define RCC_MCO1SOURCE_LSE RCC_CFGR_MCO1_0
#define RCC_MCO1SOURCE_HSE RCC_CFGR_MCO1_1
#define RCC_MCO1SOURCE_PLL1QCLK ((uint32_t)RCC_CFGR_MCO1_0 | RCC_CFGR_MCO1_1)
#define RCC_MCO1SOURCE_HSI48 RCC_CFGR_MCO1_2
/**
* @}
*/
/** @defgroup RCC_MCO2_Clock_Source RCC MCO2 Clock Source
* @{
*/
#define RCC_MCO2SOURCE_SYSCLK (0x00000000U)
#define RCC_MCO2SOURCE_PLL2PCLK RCC_CFGR_MCO2_0
#define RCC_MCO2SOURCE_HSE RCC_CFGR_MCO2_1
#define RCC_MCO2SOURCE_PLLCLK ((uint32_t)RCC_CFGR_MCO2_0 | RCC_CFGR_MCO2_1)
#define RCC_MCO2SOURCE_CSICLK RCC_CFGR_MCO2_2
#define RCC_MCO2SOURCE_LSICLK ((uint32_t)RCC_CFGR_MCO2_0 | RCC_CFGR_MCO2_2)
/**
* @}
*/
/** @defgroup RCC_MCOx_Clock_Prescaler RCC MCOx Clock Prescaler
* @{
*/
#define RCC_MCODIV_1 RCC_CFGR_MCO1PRE_0
#define RCC_MCODIV_2 RCC_CFGR_MCO1PRE_1
#define RCC_MCODIV_3 ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_1)
#define RCC_MCODIV_4 RCC_CFGR_MCO1PRE_2
#define RCC_MCODIV_5 ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2)
#define RCC_MCODIV_6 ((uint32_t)RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2)
#define RCC_MCODIV_7 ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2)
#define RCC_MCODIV_8 RCC_CFGR_MCO1PRE_3
#define RCC_MCODIV_9 ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_3)
#define RCC_MCODIV_10 ((uint32_t)RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_3)
#define RCC_MCODIV_11 ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_3)
#define RCC_MCODIV_12 ((uint32_t)RCC_CFGR_MCO1PRE_2 | RCC_CFGR_MCO1PRE_3)
#define RCC_MCODIV_13 ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2 | RCC_CFGR_MCO1PRE_3)
#define RCC_MCODIV_14 ((uint32_t)RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2 | RCC_CFGR_MCO1PRE_3)
#define RCC_MCODIV_15 RCC_CFGR_MCO1PRE
/**
* @}
*/
/** @defgroup RCC_Interrupt RCC Interrupt
* @{
*/
#define RCC_IT_LSIRDY (0x00000001U)
#define RCC_IT_LSERDY (0x00000002U)
#define RCC_IT_HSIRDY (0x00000004U)
#define RCC_IT_HSERDY (0x00000008U)
#define RCC_IT_CSIRDY (0x00000010U)
#define RCC_IT_HSI48RDY (0x00000020U)
#define RCC_IT_PLLRDY (0x00000040U)
#define RCC_IT_PLL2RDY (0x00000080U)
#define RCC_IT_PLL3RDY (0x00000100U)
#define RCC_IT_LSECSS (0x00000200U)
#define RCC_IT_CSS (0x00000400U)
/**
* @}
*/
/** @defgroup RCC_Flag RCC Flag
* Elements values convention: XXXYYYYYb
* - YYYYY : Flag position in the register
* - XXX : Register index
* - 001: CR register
* - 010: BDCR register
* - 011: CSR register
* - 100: RSR register
* @{
*/
/* Flags in the CR register */
#define RCC_FLAG_HSIRDY ((uint8_t)0x22)
#define RCC_FLAG_HSIDIV ((uint8_t)0x25)
#define RCC_FLAG_CSIRDY ((uint8_t)0x28)
#define RCC_FLAG_HSI48RDY ((uint8_t)0x2D)
#if defined(RCC_CR_D1CKRDY)
#define RCC_FLAG_D1CKRDY ((uint8_t)0x2E)
#else
#define RCC_FLAG_CPUCKRDY ((uint8_t)0x2E)
#define RCC_FLAG_D1CKRDY RCC_FLAG_CPUCKRDY /* alias */
#endif /* RCC_CR_D1CKRDY */
#if defined(RCC_CR_D2CKRDY)
#define RCC_FLAG_D2CKRDY ((uint8_t)0x2F)
#else
#define RCC_FLAG_CDCKRDY ((uint8_t)0x2F)
#define RCC_FLAG_D2CKRDY RCC_FLAG_CDCKRDY /* alias */
#endif /* RCC_CR_D2CKRDY */
#define RCC_FLAG_HSERDY ((uint8_t)0x31)
#define RCC_FLAG_PLLRDY ((uint8_t)0x39)
#define RCC_FLAG_PLL2RDY ((uint8_t)0x3B)
#define RCC_FLAG_PLL3RDY ((uint8_t)0x3D)
/* Flags in the BDCR register */
#define RCC_FLAG_LSERDY ((uint8_t)0x41)
/* Flags in the CSR register */
#define RCC_FLAG_LSIRDY ((uint8_t)0x61)
/* Flags in the RSR register */
#if defined(RCC_RSR_CPURSTF)
#define RCC_FLAG_CPURST ((uint8_t)0x91)
#endif /* RCC_RSR_CPURSTF */
#if defined(RCC_RSR_D1RSTF)
#define RCC_FLAG_D1RST ((uint8_t)0x93)
#else
#define RCC_FLAG_CDRST ((uint8_t)0x93)
#endif /* RCC_RSR_D1RSTF */
#if defined(RCC_RSR_D2RSTF)
#define RCC_FLAG_D2RST ((uint8_t)0x94)
#endif /* RCC_RSR_D2RSTF */
#define RCC_FLAG_BORRST ((uint8_t)0x95)
#define RCC_FLAG_PINRST ((uint8_t)0x96)
#define RCC_FLAG_PORRST ((uint8_t)0x97)
#define RCC_FLAG_SFTRST ((uint8_t)0x98)
#define RCC_FLAG_IWDG1RST ((uint8_t)0x9A)
#define RCC_FLAG_WWDG1RST ((uint8_t)0x9C)
#define RCC_FLAG_LPWR1RST ((uint8_t)0x9E)
#define RCC_FLAG_LPWR2RST ((uint8_t)0x9F)
#if defined(DUAL_CORE)
#define RCC_FLAG_C1RST (RCC_FLAG_CPURST)
#define RCC_FLAG_C2RST ((uint8_t)0x92)
#define RCC_FLAG_SFTR1ST (RCC_FLAG_SFTRST)
#define RCC_FLAG_SFTR2ST ((uint8_t)0x99)
#define RCC_FLAG_WWDG2RST ((uint8_t)0x9D)
#define RCC_FLAG_IWDG2RST ((uint8_t)0x9B)
#endif /*DUAL_CORE*/
/**
* @}
*/
/** @defgroup RCC_LSEDrive_Config LSE Drive Config
* @{
*/
#define RCC_LSEDRIVE_LOW (0x00000000U) /*!< LSE low drive capability */
#define RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_0 /*!< LSE medium low drive capability */
#define RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_1 /*!< LSE medium high drive capability */
#define RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV /*!< LSE high drive capability */
/**
* @}
*/
/** @defgroup RCC_Stop_WakeUpClock RCC Stop WakeUpClock
* @{
*/
#define RCC_STOP_WAKEUPCLOCK_HSI (0x00000000U)
#define RCC_STOP_WAKEUPCLOCK_CSI RCC_CFGR_STOPWUCK
/**
* @}
*/
/** @defgroup RCC_Stop_KernelWakeUpClock RCC Stop KernelWakeUpClock
* @{
*/
#define RCC_STOP_KERWAKEUPCLOCK_HSI (0x00000000U)
#define RCC_STOP_KERWAKEUPCLOCK_CSI RCC_CFGR_STOPKERWUCK
/**
* @}
*/
#if defined(RCC_VER_X)
#define HAL_RCC_REV_Y_HSITRIM_Pos (12U)
#define HAL_RCC_REV_Y_HSITRIM_Msk (0x3F000U)
#define HAL_RCC_REV_Y_CSITRIM_Pos (26U)
#define HAL_RCC_REV_Y_CSITRIM_Msk (0x7C000000U)
#endif /* RCC_VER_X */
/**
* @}
*/
/* Exported macros -----------------------------------------------------------*/
/** @defgroup RCC_Exported_Macros RCC Exported Macros
* @{
*/
/** @brief Enable or disable the AHB3 peripheral clock.
* @note After reset, the peripheral clock (used for registers read/write access)
* is disabled and the application software has to enable this clock before
* using it.
*/
#define __HAL_RCC_MDMA_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_MDMAEN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_MDMAEN);\
UNUSED(tmpreg); \
} while(0)
#define __HAL_RCC_DMA2D_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_DMA2DEN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_DMA2DEN);\
UNUSED(tmpreg); \
} while(0)
#if defined(JPEG)
#define __HAL_RCC_JPGDECEN_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_JPGDECEN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_JPGDECEN);\
UNUSED(tmpreg); \
} while(0)
#endif /* JPEG */
#define __HAL_RCC_FMC_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
UNUSED(tmpreg); \
} while(0)
#if defined(QUADSPI)
#define __HAL_RCC_QSPI_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
UNUSED(tmpreg); \
} while(0)
#endif /* QUADSPI */
#if defined(OCTOSPI1)
#define __HAL_RCC_OSPI1_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI1EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI1EN);\
UNUSED(tmpreg); \
} while(0)
#endif /* OCTOSPI1 */
#if defined(OCTOSPI2)
#define __HAL_RCC_OSPI2_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI2EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI2EN);\
UNUSED(tmpreg); \
} while(0)
#endif /* OCTOSPI2 */
#if defined(OCTOSPIM)
#define __HAL_RCC_OCTOSPIM_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_IOMNGREN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_IOMNGREN);\
UNUSED(tmpreg); \
} while(0)
#endif /* OCTOSPIM */
#if defined(OTFDEC1)
#define __HAL_RCC_OTFDEC1_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OTFDEC1EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OTFDEC1EN);\
UNUSED(tmpreg); \
} while(0)
#endif /* OTFDEC1 */
#if defined(OTFDEC2)
#define __HAL_RCC_OTFDEC2_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OTFDEC2EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OTFDEC2EN);\
UNUSED(tmpreg); \
} while(0)
#endif /* OTFDEC2 */
#if defined(GFXMMU)
#define __HAL_RCC_GFXMMU_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_GFXMMUEN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_GFXMMUEN);\
UNUSED(tmpreg); \
} while(0)
#endif /* GFXMMU */
#define __HAL_RCC_SDMMC1_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_SDMMC1EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_SDMMC1EN);\
UNUSED(tmpreg); \
} while(0)
#define __HAL_RCC_MDMA_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_MDMAEN))
#define __HAL_RCC_DMA2D_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_DMA2DEN))
#if defined(JPEG)
#define __HAL_RCC_JPGDECEN_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_JPGDECEN))
#endif /* JPEG */
#define __HAL_RCC_FMC_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_FMCEN))
#if defined(QUADSPI)
#define __HAL_RCC_QSPI_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_QSPIEN))
#endif /* QUADSPI */
#if defined(OCTOSPI1)
#define __HAL_RCC_OSPI1_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_OSPI1EN))
#endif /* OCTOSPII */
#if defined(OCTOSPI2)
#define __HAL_RCC_OSPI2_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_OSPI2EN))
#endif /* OCTOSPI2 */
#define __HAL_RCC_SDMMC1_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_SDMMC1EN))
#if defined(OCTOSPIM)
#define __HAL_RCC_OCTOSPIM_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_IOMNGREN))
#endif /* OCTOSPIM */
#if defined(OTFDEC1)
#define __HAL_RCC_OTFDEC1_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_OTFDEC1EN))
#endif /* OTOFDEC1 */
#if defined(OTFDEC2)
#define __HAL_RCC_OTFDEC2_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_OTFDEC2EN))
#endif /* OTOFDEC2 */
#if defined(GFXMMU)
#define __HAL_RCC_GFXMMU_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_GFXMMUEN))
#endif /* GFXMMU */
/** @brief Get the enable or disable status of the AHB3 peripheral clock
* @note After reset, the peripheral clock (used for registers read/write access)
* is disabled and the application software has to enable this clock before
* using it.
*/
#define __HAL_RCC_MDMA_IS_CLK_ENABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_MDMAEN) != 0U)
#define __HAL_RCC_DMA2D_IS_CLK_ENABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_DMA2DEN) != 0U)
#if defined(JPEG)
#define __HAL_RCC_JPGDECEN_IS_CLK_ENABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_JPGDECEN) != 0U)
#endif /* JPEG */
#define __HAL_RCC_FMC_IS_CLK_ENABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_FMCEN) != 0U)
#if defined (QUADSPI)
#define __HAL_RCC_QSPI_IS_CLK_ENABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_QSPIEN) != 0U)
#endif /* QUADSPI */
#if defined(OCTOSPI1)
#define __HAL_RCC_OSPI1_IS_CLK_ENABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_OSPI1EN) != 0U)
#endif /* OCTOSPII */
#if defined(OCTOSPI2)
#define __HAL_RCC_OSPI2_IS_CLK_ENABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_OSPI2EN) != 0U)
#endif /* OCTOSPI2 */
#define __HAL_RCC_SDMMC1_IS_CLK_ENABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_SDMMC1EN) != 0U)
#if defined(OCTOSPIM)
#define __HAL_RCC_OCTOSPIM_IS_CLK_ENABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_IOMNGREN) != 0U)
#endif /* OCTOSPIM */
#if defined(OTFDEC1)
#define __HAL_RCC_OTFDEC1_IS_CLK_ENABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_OTFDEC1EN) != 0U)
#endif /* OTOFDEC1 */
#if defined(OTFDEC2)
#define __HAL_RCC_OTFDEC2_IS_CLK_ENABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_OTFDEC2EN) != 0U)
#endif /* OTOFDEC2 */
#if defined(GFXMMU)
#define __HAL_RCC_GFXMMU_IS_CLK_ENABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_GFXMMUEN) != 0U)
#endif /* GFXMMU */
#define __HAL_RCC_MDMA_IS_CLK_DISABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_MDMAEN) == 0U)
#define __HAL_RCC_DMA2D_IS_CLK_DISABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_DMA2DEN) == 0U)
#if defined(JPEG)
#define __HAL_RCC_JPGDECEN_IS_CLK_DISABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_JPGDECEN) == 0U)
#endif /* JPEG */
#define __HAL_RCC_FMC_IS_CLK_DISABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_FMCEN) == 0U)
#if defined (QUADSPI)
#define __HAL_RCC_QSPI_IS_CLK_DISABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_QSPIEN) == 0U)
#endif /* QUADSPI */
#define __HAL_RCC_SDMMC1_IS_CLK_DISABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_SDMMC1EN) == 0U)
#if defined(OCTOSPI1)
#define __HAL_RCC_OSPI1_IS_CLK_DISABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_OSPI1EN) == 0U)
#endif
#if defined(OCTOSPI2)
#define __HAL_RCC_OSPI2_IS_CLK_DISABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_OSPI2EN) == 0U)
#endif
#if defined(OCTOSPIM)
#define __HAL_RCC_OCTOSPIM_IS_CLK_DISABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_IOMNGREN) == 0U)
#endif
#if defined(OTFDEC1)
#define __HAL_RCC_OTFDEC1_IS_CLK_DISABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_OTFDEC1EN) == 0U)
#endif
#if defined(OTFDEC2)
#define __HAL_RCC_OTFDEC2_IS_CLK_DISABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_OTFDEC2EN) == 0U)
#endif
#if defined(GFXMMU)
#define __HAL_RCC_GFXMMU_IS_CLK_DISABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_GFXMMUEN) == 0U)
#endif
/** @brief Enable or disable the AHB1 peripheral clock.
* @note After reset, the peripheral clock (used for registers read/write access)
* is disabled and the application software has to enable this clock before
* using it.
*/
#define __HAL_RCC_DMA1_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
UNUSED(tmpreg); \
} while(0)
#define __HAL_RCC_DMA2_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
UNUSED(tmpreg); \
} while(0)
#define __HAL_RCC_ADC12_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ADC12EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ADC12EN);\