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wm8994_reg.c
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wm8994_reg.c
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/**
******************************************************************************
* @file wm8994_reg.c
* @author MCD Application Team
* @brief This file provides unitary register function to control the WM8994
* Audio Codec driver.
******************************************************************************
* @attention
*
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "wm8994_reg.h"
/** @addtogroup BSP
* @{
*/
/** @addtogroup Components
* @{
*/
/** @addtogroup wm8994
* @brief This file provides a set of functions needed to drive the
* WM8994 audio codec.
* @{
*/
/************** Generic Function *******************/
/*******************************************************************************
* Function Name : wm8994_read_reg
* Description : Generic Reading function. It must be full-filled with either
* I2C or SPI reading functions
* Input : Register Address, length of buffer
* Output : data Read
*******************************************************************************/
int32_t wm8994_read_reg(wm8994_ctx_t *ctx, uint16_t reg, uint16_t* data, uint16_t length)
{
int32_t ret;
uint16_t tmp;
ret = ctx->ReadReg(ctx->handle, reg, (uint8_t *)data, length);
if(ret >= 0)
{
tmp = ((uint16_t)(*data >> 8) & 0x00FF);
tmp |= ((uint16_t)(*data << 8) & 0xFF00);
*data = tmp;
}
return ret;
}
/*******************************************************************************
* Function Name : wm8994_write_reg
* Description : Generic Writing function. It must be full-filled with either
* I2C or SPI writing function
* Input : Register Address, data to be written, length of buffer
* Output : None
*******************************************************************************/
int32_t wm8994_write_reg(wm8994_ctx_t *ctx, uint16_t reg, uint16_t *data, uint16_t length)
{
uint16_t tmp;
tmp = ((uint16_t)(*data >> 8) & 0x00FF);
tmp |= ((uint16_t)(*data << 8) & 0xFF00);
return ctx->WriteReg(ctx->handle, reg, (uint8_t *)&tmp, length);
}
/**************** Base Function *******************/
/*******************************************************************************
* Function Name : wm8994_register_set
* Description : Write value to a WM8994 register
* Input : uint16_t
* Output : None
* Return : Status [WM8994_ERROR, WM8994_OK]
*******************************************************************************/
int32_t wm8994_register_set(wm8994_ctx_t *ctx, uint16_t reg, uint16_t value)
{
return wm8994_write_reg(ctx, reg, &value, 2);
}
/*******************************************************************************
* Function Name : wm8994_sw_reset_w
* Description : Write Device Mode
* Input : uint16_t
* Output : None
* Return : Status [WM8994_ERROR, WM8994_OK]
*******************************************************************************/
int32_t wm8994_sw_reset_w(wm8994_ctx_t *ctx, uint16_t value)
{
return wm8994_write_reg(ctx, WM8994_SW_RESET, &value, 2);
}
/*******************************************************************************
* Function Name : wm8994_sw_reset_r
* Description : Read Device Mode
* Input : Pointer to uint8_t
* Output : None
* Return : Status [WM8994_ERROR, WM8994_OK]
*******************************************************************************/
int32_t wm8994_sw_reset_r(wm8994_ctx_t *ctx, uint16_t *value)
{
return wm8994_read_reg(ctx, WM8994_SW_RESET, value, 2);
}
/*******************************************************************************
* Function Name : wm8994_pwr_mgmt_1_bias_en
* Description : Bias enable
* Input : uint16_t
* Output : None
* Return : Status [WM8994_ERROR, WM8994_OK]
*******************************************************************************/
int32_t wm8994_pwr_mgmt_1_bias_en(wm8994_ctx_t *ctx, uint16_t value)
{
int32_t ret;
uint16_t tmp = 0;
ret = wm8994_read_reg(ctx, WM8994_PWR_MANAGEMENT_1, &tmp, 2);
if(ret == 0)
{
tmp &= ~WM8994_PWR_MGMT_1_BIAS_EN_MASK;
tmp |= value << WM8994_PWR_MGMT_1_BIAS_EN_POSITION;
ret = wm8994_write_reg(ctx, WM8994_PWR_MANAGEMENT_1, &tmp, 2);
}
return ret;
}
/*******************************************************************************
* Function Name : wm8994_pwr_mgmt_1_vmid_sel
* Description : VMID Divider Enable and Select
* Input : uint16_t
* Output : None
* Return : Status [WM8994_ERROR, WM8994_OK]
*******************************************************************************/
int32_t wm8994_pwr_mgmt_1_vmid_sel(wm8994_ctx_t *ctx, uint16_t value)
{
int32_t ret;
uint16_t tmp = 0;
ret = wm8994_read_reg(ctx, WM8994_PWR_MANAGEMENT_1, &tmp, 2);
if(ret == 0)
{
tmp &= ~WM8994_PWR_MGMT_1_VMID_SEL_MASK;
tmp |= value << WM8994_PWR_MGMT_1_VMID_SEL_POSITION;
ret = wm8994_write_reg(ctx, WM8994_PWR_MANAGEMENT_1, &tmp, 2);
}
return ret;
}
/*******************************************************************************
* Function Name : wm8994_pwr_mgmt_1_micb1_ena
* Description : Microphone Bias 1 Enable
* Input : uint16_t
* Output : None
* Return : Status [WM8994_ERROR, WM8994_OK]
*******************************************************************************/
int32_t wm8994_pwr_mgmt_1_micb1_ena(wm8994_ctx_t *ctx, uint16_t value)
{
int32_t ret;
uint16_t tmp = 0;
ret = wm8994_read_reg(ctx, WM8994_PWR_MANAGEMENT_1, &tmp, 2);
if(ret == 0)
{
tmp &= ~WM8994_PWR_MGMT_1_MICB1_ENA_MASK;
tmp |= value << WM8994_PWR_MGMT_1_MICB1_ENA_POSITION;
ret = wm8994_write_reg(ctx, WM8994_PWR_MANAGEMENT_1, &tmp, 2);
}
return ret;
}
/*******************************************************************************
* Function Name : wm8994_pwr_mgmt_1_micb2_ena
* Description : Microphone Bias 2 Enable
* Input : uint16_t
* Output : None
* Return : Status [WM8994_ERROR, WM8994_OK]
*******************************************************************************/
int32_t wm8994_pwr_mgmt_1_micb2_ena(wm8994_ctx_t *ctx, uint16_t value)
{
int32_t ret;
uint16_t tmp = 0;
ret = wm8994_read_reg(ctx, WM8994_PWR_MANAGEMENT_1, &tmp, 2);
if(ret == 0)
{
tmp &= ~WM8994_PWR_MGMT_1_MICB2_ENA_MASK;
tmp |= value << WM8994_PWR_MGMT_1_MICB2_ENA_POSITION;
ret = wm8994_write_reg(ctx, WM8994_PWR_MANAGEMENT_1, &tmp, 2);
}
return ret;
}
/*******************************************************************************
* Function Name : wm8994_pwr_mgmt_1_hpout1r_ena
* Description : Enables HPOUT1R input stage
* Input : uint16_t
* Output : None
* Return : Status [WM8994_ERROR, WM8994_OK]
*******************************************************************************/
int32_t wm8994_pwr_mgmt_1_hpout1r_ena(wm8994_ctx_t *ctx, uint16_t value)
{
int32_t ret;
uint16_t tmp = 0;
ret = wm8994_read_reg(ctx, WM8994_PWR_MANAGEMENT_1, &tmp, 2);
if(ret == 0)
{
tmp &= ~WM8994_PWR_MGMT_1_HPOUT1R_ENA_MASK;
tmp |= value << WM8994_PWR_MGMT_1_HPOUT1R_ENA_POSITION;
ret = wm8994_write_reg(ctx, WM8994_PWR_MANAGEMENT_1, &tmp, 2);
}
return ret;
}
/*******************************************************************************
* Function Name : wm8994_pwr_mgmt_1_hpout1l_ena
* Description : Enables HPOUT1L input stage
* Input : uint16_t
* Output : None
* Return : Status [WM8994_ERROR, WM8994_OK]
*******************************************************************************/
int32_t wm8994_pwr_mgmt_1_hpout1l_ena(wm8994_ctx_t *ctx, uint16_t value)
{
int32_t ret;
uint16_t tmp = 0;
ret = wm8994_read_reg(ctx, WM8994_PWR_MANAGEMENT_1, &tmp, 2);
if(ret == 0)
{
tmp &= ~WM8994_PWR_MGMT_1_HPOUT1L_ENA_MASK;
tmp |= value << WM8994_PWR_MGMT_1_HPOUT1L_ENA_POSITION;
ret = wm8994_write_reg(ctx, WM8994_PWR_MANAGEMENT_1, &tmp, 2);
}
return ret;
}
/*******************************************************************************
* Function Name : wm8994_pwr_mgmt_1_hpout2_ena
* Description : HPOUT2 Output Stage Enable
* Input : uint16_t
* Output : None
* Return : Status [WM8994_ERROR, WM8994_OK]
*******************************************************************************/
int32_t wm8994_pwr_mgmt_1_hpout2_ena(wm8994_ctx_t *ctx, uint16_t value)
{
int32_t ret;
uint16_t tmp = 0;
ret = wm8994_read_reg(ctx, WM8994_PWR_MANAGEMENT_1, &tmp, 2);
if(ret == 0)
{
tmp &= ~WM8994_PWR_MGMT_1_HPOUT2_ENA_MASK;
tmp |= value << WM8994_PWR_MGMT_1_HPOUT2_ENA_POSITION;
ret = wm8994_write_reg(ctx, WM8994_PWR_MANAGEMENT_1, &tmp, 2);
}
return ret;
}
/*******************************************************************************
* Function Name : wm8994_pwr_mgmt_1_spkoutl_ena
* Description : SPKMIXL Mixer, SPKLVOL PGA and SPKOUTL Output Enable
* Input : uint16_t
* Output : None
* Return : Status [WM8994_ERROR, WM8994_OK]
*******************************************************************************/
int32_t wm8994_pwr_mgmt_1_spkoutl_ena(wm8994_ctx_t *ctx, uint16_t value)
{
int32_t ret;
uint16_t tmp = 0;
ret = wm8994_read_reg(ctx, WM8994_PWR_MANAGEMENT_1, &tmp, 2);
if(ret == 0)
{
tmp &= ~WM8994_PWR_MGMT_1_SPKOUTL_ENA_MASK;
tmp |= value << WM8994_PWR_MGMT_1_SPKOUTL_ENA_POSITION;
ret = wm8994_write_reg(ctx, WM8994_PWR_MANAGEMENT_1, &tmp, 2);
}
return ret;
}
/*******************************************************************************
* Function Name : wm8994_pwr_mgmt_1_spkoutr_ena
* Description : SPKMIXR Mixer, SPKRVOL PGA and SPKOUTR Output Enable
* Input : uint16_t
* Output : None
* Return : Status [WM8994_ERROR, WM8994_OK]
*******************************************************************************/
int32_t wm8994_pwr_mgmt_1_spkoutr_ena(wm8994_ctx_t *ctx, uint16_t value)
{
int32_t ret;
uint16_t tmp = 0;
ret = wm8994_read_reg(ctx, WM8994_PWR_MANAGEMENT_1, &tmp, 2);
if(ret == 0)
{
tmp &= ~WM8994_PWR_MGMT_1_SPKOUTR_ENA_MASK;
tmp |= value << WM8994_PWR_MGMT_1_SPKOUTR_ENA_POSITION;
ret = wm8994_write_reg(ctx, WM8994_PWR_MANAGEMENT_1, &tmp, 2);
}
return ret;
}
/*******************************************************************************
* Function Name : wm8994_pwr_mgmt_2_in1r_ena
* Description : IN1R Input PGA Enable
* Input : uint16_t
* Output : None
* Return : Status [WM8994_ERROR, WM8994_OK]
*******************************************************************************/
int32_t wm8994_pwr_mgmt_2_in1r_ena(wm8994_ctx_t *ctx, uint16_t value)
{
int32_t ret;
uint16_t tmp = 0;
ret = wm8994_read_reg(ctx, WM8994_PWR_MANAGEMENT_2, &tmp, 2);
if(ret == 0)
{
tmp &= ~WM8994_PWR_MGMT_2_IN1R_ENA_MASK;
tmp |= value << WM8994_PWR_MGMT_2_IN1R_ENA_POSITION;
ret = wm8994_write_reg(ctx, WM8994_PWR_MANAGEMENT_2, &tmp, 2);
}
return ret;
}
/*******************************************************************************
* Function Name : wm8994_pwr_mgmt_2_in2r_ena
* Description : IN2R Input PGA Enable
* Input : uint16_t
* Output : None
* Return : Status [WM8994_ERROR, WM8994_OK]
*******************************************************************************/
int32_t wm8994_pwr_mgmt_2_in2r_ena(wm8994_ctx_t *ctx, uint16_t value)
{
int32_t ret;
uint16_t tmp = 0;
ret = wm8994_read_reg(ctx, WM8994_PWR_MANAGEMENT_2, &tmp, 2);
if(ret == 0)
{
tmp &= ~WM8994_PWR_MGMT_2_IN2R_ENA_MASK;
tmp |= value << WM8994_PWR_MGMT_2_IN2R_ENA_POSITION;
ret = wm8994_write_reg(ctx, WM8994_PWR_MANAGEMENT_2, &tmp, 2);
}
return ret;
}
/*******************************************************************************
* Function Name : wm8994_pwr_mgmt_2_in1l_ena
* Description : IN1L Input PGA Enable
* Input : uint16_t
* Output : None
* Return : Status [WM8994_ERROR, WM8994_OK]
*******************************************************************************/
int32_t wm8994_pwr_mgmt_2_in1l_ena(wm8994_ctx_t *ctx, uint16_t value)
{
int32_t ret;
uint16_t tmp = 0;
ret = wm8994_read_reg(ctx, WM8994_PWR_MANAGEMENT_2, &tmp, 2);
if(ret == 0)
{
tmp &= ~WM8994_PWR_MGMT_2_IN1L_ENA_MASK;
tmp |= value << WM8994_PWR_MGMT_2_IN1L_ENA_POSITION;
ret = wm8994_write_reg(ctx, WM8994_PWR_MANAGEMENT_2, &tmp, 2);
}
return ret;
}
/*******************************************************************************
* Function Name : wm8994_pwr_mgmt_2_in2l_ena
* Description : IN2L Input PGA Enable
* Input : uint16_t
* Output : None
* Return : Status [WM8994_ERROR, WM8994_OK]
*******************************************************************************/
int32_t wm8994_pwr_mgmt_2_in2l_ena(wm8994_ctx_t *ctx, uint16_t value)
{
int32_t ret;
uint16_t tmp = 0;
ret = wm8994_read_reg(ctx, WM8994_PWR_MANAGEMENT_2, &tmp, 2);
if(ret == 0)
{
tmp &= ~WM8994_PWR_MGMT_2_IN2L_ENA_MASK;
tmp |= value << WM8994_PWR_MGMT_2_IN2L_ENA_POSITION;
ret = wm8994_write_reg(ctx, WM8994_PWR_MANAGEMENT_2, &tmp, 2);
}
return ret;
}
/*******************************************************************************
* Function Name : wm8994_pwr_mgmt_2_mixinr_ena
* Description : Right Input Mixer Enable
* Input : uint16_t
* Output : None
* Return : Status [WM8994_ERROR, WM8994_OK]
*******************************************************************************/
int32_t wm8994_pwr_mgmt_2_mixinr_ena(wm8994_ctx_t *ctx, uint16_t value)
{
int32_t ret;
uint16_t tmp = 0;
ret = wm8994_read_reg(ctx, WM8994_PWR_MANAGEMENT_2, &tmp, 2);
if(ret == 0)
{
tmp &= ~WM8994_PWR_MGMT_2_MIXINR_ENA_MASK;
tmp |= value << WM8994_PWR_MGMT_2_MIXINR_ENA_POSITION;
ret = wm8994_write_reg(ctx, WM8994_PWR_MANAGEMENT_2, &tmp, 2);
}
return ret;
}
/*******************************************************************************
* Function Name : wm8994_pwr_mgmt_2_mixinl_ena
* Description : Left Input Mixer Enable
* Input : uint16_t
* Output : None
* Return : Status [WM8994_ERROR, WM8994_OK]
*******************************************************************************/
int32_t wm8994_pwr_mgmt_2_mixinl_ena(wm8994_ctx_t *ctx, uint16_t value)
{
int32_t ret;
uint16_t tmp = 0;
ret = wm8994_read_reg(ctx, WM8994_PWR_MANAGEMENT_2, &tmp, 2);
if(ret == 0)
{
tmp &= ~WM8994_PWR_MGMT_2_MIXINL_ENA_MASK;
tmp |= value << WM8994_PWR_MGMT_2_MIXINL_ENA_POSITION;
ret = wm8994_write_reg(ctx, WM8994_PWR_MANAGEMENT_2, &tmp, 2);
}
return ret;
}
/*******************************************************************************
* Function Name : wm8994_pwr_mgmt_2_opclk_ena
* Description : GPIO Clock Output (OPCLK) Enable
* Input : uint16_t
* Output : None
* Return : Status [WM8994_ERROR, WM8994_OK]
*******************************************************************************/
int32_t wm8994_pwr_mgmt_2_opclk_ena(wm8994_ctx_t *ctx, uint16_t value)
{
int32_t ret;
uint16_t tmp = 0;
ret = wm8994_read_reg(ctx, WM8994_PWR_MANAGEMENT_2, &tmp, 2);
if(ret == 0)
{
tmp &= ~WM8994_PWR_MGMT_2_OPCLK_ENA_MASK;
tmp |= value << WM8994_PWR_MGMT_2_OPCLK_ENA_POSITION;
ret = wm8994_write_reg(ctx, WM8994_PWR_MANAGEMENT_2, &tmp, 2);
}
return ret;
}
/*******************************************************************************
* Function Name : wm8994_pwr_mgmt_2_tshut_opdis
* Description : Thermal shutdown control
* Input : uint16_t
* Output : None
* Return : Status [WM8994_ERROR, WM8994_OK]
*******************************************************************************/
int32_t wm8994_pwr_mgmt_2_tshut_opdis(wm8994_ctx_t *ctx, uint16_t value)
{
int32_t ret;
uint16_t tmp = 0;
ret = wm8994_read_reg(ctx, WM8994_PWR_MANAGEMENT_2, &tmp, 2);
if(ret == 0)
{
tmp &= ~WM8994_PWR_MGMT_2_TSHUT_OPDIS_MASK;
tmp |= value << WM8994_PWR_MGMT_2_TSHUT_OPDIS_POSITION;
ret = wm8994_write_reg(ctx, WM8994_PWR_MANAGEMENT_2, &tmp, 2);
}
return ret;
}
/*******************************************************************************
* Function Name : wm8994_pwr_mgmt_2_tshut_ena
* Description : Thermal sensor enable
* Input : uint16_t
* Output : None
* Return : Status [WM8994_ERROR, WM8994_OK]
*******************************************************************************/
int32_t wm8994_pwr_mgmt_2_tshut_ena(wm8994_ctx_t *ctx, uint16_t value)
{
int32_t ret;
uint16_t tmp = 0;
ret = wm8994_read_reg(ctx, WM8994_PWR_MANAGEMENT_2, &tmp, 2);
if(ret == 0)
{
tmp &= ~WM8994_PWR_MGMT_2_TSHUT_ENA_MASK;
tmp |= value << WM8994_PWR_MGMT_2_TSHUT_ENA_POSITION;
ret = wm8994_write_reg(ctx, WM8994_PWR_MANAGEMENT_2, &tmp, 2);
}
return ret;
}
/*******************************************************************************
* Function Name : wm8994_pwr_mgmt_3_mixoutr_ena
* Description : MIXOUTR Right Output Mixer Enable
* Input : uint16_t
* Output : None
* Return : Status [WM8994_ERROR, WM8994_OK]
*******************************************************************************/
int32_t wm8994_pwr_mgmt_3_mixoutr_ena(wm8994_ctx_t *ctx, uint16_t value)
{
int32_t ret;
uint16_t tmp = 0;
ret = wm8994_read_reg(ctx, WM8994_PWR_MANAGEMENT_3, &tmp, 2);
if(ret == 0)
{
tmp &= ~WM8994_PWR_MGMT_3_MIXOUTR_ENA_MASK;
tmp |= value << WM8994_PWR_MGMT_3_MIXOUTR_ENA_POSITION;
ret = wm8994_write_reg(ctx, WM8994_PWR_MANAGEMENT_3, &tmp, 2);
}
return ret;
}
/*******************************************************************************
* Function Name : wm8994_pwr_mgmt_3_mixoutl_ena
* Description : MIXOUTL Left Output Mixer Enable
* Input : uint16_t
* Output : None
* Return : Status [WM8994_ERROR, WM8994_OK]
*******************************************************************************/
int32_t wm8994_pwr_mgmt_3_mixoutl_ena(wm8994_ctx_t *ctx, uint16_t value)
{
int32_t ret;
uint16_t tmp = 0;
ret = wm8994_read_reg(ctx, WM8994_PWR_MANAGEMENT_3, &tmp, 2);
if(ret == 0)
{
tmp &= ~WM8994_PWR_MGMT_3_MIXOUTL_ENA_MASK;
tmp |= value << WM8994_PWR_MGMT_3_MIXOUTL_ENA_POSITION;
ret = wm8994_write_reg(ctx, WM8994_PWR_MANAGEMENT_3, &tmp, 2);
}
return ret;
}
/*******************************************************************************
* Function Name : wm8994_pwr_mgmt_3_mixoutrvol_ena
* Description : MIXOUTL Right Volume Control Enable
* Input : uint16_t
* Output : None
* Return : Status [WM8994_ERROR, WM8994_OK]
*******************************************************************************/
int32_t wm8994_pwr_mgmt_3_mixoutrvol_ena(wm8994_ctx_t *ctx, uint16_t value)
{
int32_t ret;
uint16_t tmp = 0;
ret = wm8994_read_reg(ctx, WM8994_PWR_MANAGEMENT_3, &tmp, 2);
if(ret == 0)
{
tmp &= ~WM8994_PWR_MGMT_3_MIXOUTRVOL_ENA_MASK;
tmp |= value << WM8994_PWR_MGMT_3_MIXOUTRVOL_ENA_POSITION;
ret = wm8994_write_reg(ctx, WM8994_PWR_MANAGEMENT_3, &tmp, 2);
}
return ret;
}
/*******************************************************************************
* Function Name : wm8994_pwr_mgmt_3_mixoutlvol_ena
* Description : MIXOUTL Left Volume Control Enable
* Input : uint16_t
* Output : None
* Return : Status [WM8994_ERROR, WM8994_OK]
*******************************************************************************/
int32_t wm8994_pwr_mgmt_3_mixoutlvol_ena(wm8994_ctx_t *ctx, uint16_t value)
{
int32_t ret;
uint16_t tmp = 0;
ret = wm8994_read_reg(ctx, WM8994_PWR_MANAGEMENT_3, &tmp, 2);
if(ret == 0)
{
tmp &= ~WM8994_PWR_MGMT_3_MIXOUTLVOL_ENA_MASK;
tmp |= value << WM8994_PWR_MGMT_3_MIXOUTLVOL_ENA_POSITION;
ret = wm8994_write_reg(ctx, WM8994_PWR_MANAGEMENT_3, &tmp, 2);
}
return ret;
}
/*******************************************************************************
* Function Name : wm8994_pwr_mgmt_3_spklvol_ena
* Description : SPKMIXL Mixer and SPKRVOL PGA Enable
* Input : uint16_t
* Output : None
* Return : Status [WM8994_ERROR, WM8994_OK]
*******************************************************************************/
int32_t wm8994_pwr_mgmt_3_spklvol_ena(wm8994_ctx_t *ctx, uint16_t value)
{
int32_t ret;
uint16_t tmp = 0;
ret = wm8994_read_reg(ctx, WM8994_PWR_MANAGEMENT_3, &tmp, 2);
if(ret == 0)
{
tmp &= ~WM8994_PWR_MGMT_3_SPKLVOL_ENA_MASK;
tmp |= value << WM8994_PWR_MGMT_3_SPKLVOL_ENA_POSITION;
ret = wm8994_write_reg(ctx, WM8994_PWR_MANAGEMENT_3, &tmp, 2);
}
return ret;
}
/*******************************************************************************
* Function Name : wm8994_pwr_mgmt_3_spkrvol_ena
* Description : SPKMIXR Mixer and SPKRVOL PGA Enable
* Input : uint16_t
* Output : None
* Return : Status [WM8994_ERROR, WM8994_OK]
*******************************************************************************/
int32_t wm8994_pwr_mgmt_3_spkrvol_ena(wm8994_ctx_t *ctx, uint16_t value)
{
int32_t ret;
uint16_t tmp = 0;
ret = wm8994_read_reg(ctx, WM8994_PWR_MANAGEMENT_3, &tmp, 2);
if(ret == 0)
{
tmp &= ~WM8994_PWR_MGMT_3_SPKRVOL_ENA_MASK;
tmp |= value << WM8994_PWR_MGMT_3_SPKRVOL_ENA_POSITION;
ret = wm8994_write_reg(ctx, WM8994_PWR_MANAGEMENT_3, &tmp, 2);
}
return ret;
}
/*******************************************************************************
* Function Name : wm8994_pwr_mgmt_3_lineout2p_ena
* Description : LINEOUT2P Line Out and LINEOUT2PMIX Enable
* Input : uint16_t
* Output : None
* Return : Status [WM8994_ERROR, WM8994_OK]
*******************************************************************************/
int32_t wm8994_pwr_mgmt_3_lineout2p_ena(wm8994_ctx_t *ctx, uint16_t value)
{
int32_t ret;
uint16_t tmp = 0;
ret = wm8994_read_reg(ctx, WM8994_PWR_MANAGEMENT_3, &tmp, 2);
if(ret == 0)
{
tmp &= ~WM8994_PWR_MGMT_3_LINEOUT2P_ENA_MASK;
tmp |= value << WM8994_PWR_MGMT_3_LINEOUT2P_ENA_POSITION;
ret = wm8994_write_reg(ctx, WM8994_PWR_MANAGEMENT_3, &tmp, 2);
}
return ret;
}
/*******************************************************************************
* Function Name : wm8994_pwr_mgmt_3_lineout2n_ena
* Description : LINEOUT2N Line Out and LINEOUT2NMIX Enable
* Input : uint16_t
* Output : None
* Return : Status [WM8994_ERROR, WM8994_OK]
*******************************************************************************/
int32_t wm8994_pwr_mgmt_3_lineout2n_ena(wm8994_ctx_t *ctx, uint16_t value)
{
int32_t ret;
uint16_t tmp = 0;
ret = wm8994_read_reg(ctx, WM8994_PWR_MANAGEMENT_3, &tmp, 2);
if(ret == 0)
{
tmp &= ~WM8994_PWR_MGMT_3_LINEOUT2N_ENA_MASK;
tmp |= value << WM8994_PWR_MGMT_3_LINEOUT2N_ENA_POSITION;
ret = wm8994_write_reg(ctx, WM8994_PWR_MANAGEMENT_3, &tmp, 2);
}
return ret;
}
/*******************************************************************************
* Function Name : wm8994_pwr_mgmt_3_lineout1p_ena
* Description : LINEOUT1P Line Out and LINEOUT1PMIX Enable
* Input : uint16_t
* Output : None
* Return : Status [WM8994_ERROR, WM8994_OK]
*******************************************************************************/
int32_t wm8994_pwr_mgmt_3_lineout1p_ena(wm8994_ctx_t *ctx, uint16_t value)
{
int32_t ret;
uint16_t tmp = 0;
ret = wm8994_read_reg(ctx, WM8994_PWR_MANAGEMENT_3, &tmp, 2);
if(ret == 0)
{
tmp &= ~WM8994_PWR_MGMT_3_LINEOUT1P_ENA_MASK;
tmp |= value << WM8994_PWR_MGMT_3_LINEOUT1P_ENA_POSITION;
ret = wm8994_write_reg(ctx, WM8994_PWR_MANAGEMENT_3, &tmp, 2);
}
return ret;
}
/*******************************************************************************
* Function Name : wm8994_pwr_mgmt_3_lineout1n_ena
* Description : LINEOUT1N Line Out and LINEOUT1NMIX Enable
* Input : uint16_t
* Output : None
* Return : Status [WM8994_ERROR, WM8994_OK]
*******************************************************************************/
int32_t wm8994_pwr_mgmt_3_lineout1n_ena(wm8994_ctx_t *ctx, uint16_t value)
{
int32_t ret;
uint16_t tmp = 0;
ret = wm8994_read_reg(ctx, WM8994_PWR_MANAGEMENT_3, &tmp, 2);
if(ret == 0)
{
tmp &= ~WM8994_PWR_MGMT_3_LINEOUT1N_ENA_MASK;
tmp |= value << WM8994_PWR_MGMT_3_LINEOUT1N_ENA_POSITION;
ret = wm8994_write_reg(ctx, WM8994_PWR_MANAGEMENT_3, &tmp, 2);
}
return ret;
}
/*******************************************************************************
* Function Name : wm8994_pwr_mgmt_4_adcr_ena
* Description : Right ADC Enable
* Input : uint16_t
* Output : None
* Return : Status [WM8994_ERROR, WM8994_OK]
*******************************************************************************/
int32_t wm8994_pwr_mgmt_4_adcr_ena(wm8994_ctx_t *ctx, uint16_t value)
{
int32_t ret;
uint16_t tmp = 0;
ret = wm8994_read_reg(ctx, WM8994_PWR_MANAGEMENT_4, &tmp, 2);
if(ret == 0)
{
tmp &= ~WM8994_PWR_MGMT_4_ADCR_ENA_MASK;
tmp |= value << WM8994_PWR_MGMT_4_ADCR_ENA_POSITION;
ret = wm8994_write_reg(ctx, WM8994_PWR_MANAGEMENT_4, &tmp, 2);
}
return ret;
}
/*******************************************************************************
* Function Name : wm8994_pwr_mgmt_4_adcl_ena
* Description : Left ADC Enable
* Input : uint16_t
* Output : None
* Return : Status [WM8994_ERROR, WM8994_OK]
*******************************************************************************/
int32_t wm8994_pwr_mgmt_4_adcl_ena(wm8994_ctx_t *ctx, uint16_t value)
{
int32_t ret;
uint16_t tmp = 0;
ret = wm8994_read_reg(ctx, WM8994_PWR_MANAGEMENT_4, &tmp, 2);
if(ret == 0)
{
tmp &= ~WM8994_PWR_MGMT_4_ADCL_ENA_MASK;
tmp |= value << WM8994_PWR_MGMT_4_ADCL_ENA_POSITION;
ret = wm8994_write_reg(ctx, WM8994_PWR_MANAGEMENT_4, &tmp, 2);
}
return ret;
}
/*******************************************************************************
* Function Name : wm8994_pwr_mgmt_4_dmic1r_ena
* Description : Digital microphone DMICDAT1 Right channel enable
* Input : uint16_t
* Output : None
* Return : Status [WM8994_ERROR, WM8994_OK]
*******************************************************************************/
int32_t wm8994_pwr_mgmt_4_dmic1r_ena(wm8994_ctx_t *ctx, uint16_t value)
{
int32_t ret;
uint16_t tmp = 0;
ret = wm8994_read_reg(ctx, WM8994_PWR_MANAGEMENT_4, &tmp, 2);
if(ret == 0)
{
tmp &= ~WM8994_PWR_MGMT_4_DMIC1R_ENA_MASK;
tmp |= value << WM8994_PWR_MGMT_4_DMIC1R_ENA_POSITION;
ret = wm8994_write_reg(ctx, WM8994_PWR_MANAGEMENT_4, &tmp, 2);
}
return ret;
}
/*******************************************************************************
* Function Name : wm8994_pwr_mgmt_4_dmic1l_ena
* Description : Digital microphone DMICDAT1 Left channel enable
* Input : uint16_t
* Output : None
* Return : Status [WM8994_ERROR, WM8994_OK]
*******************************************************************************/
int32_t wm8994_pwr_mgmt_4_dmic1l_ena(wm8994_ctx_t *ctx, uint16_t value)
{
int32_t ret;
uint16_t tmp = 0;
ret = wm8994_read_reg(ctx, WM8994_PWR_MANAGEMENT_4, &tmp, 2);
if(ret == 0)
{
tmp &= ~WM8994_PWR_MGMT_4_DMIC1L_ENA_MASK;
tmp |= value << WM8994_PWR_MGMT_4_DMIC1L_ENA_POSITION;
ret = wm8994_write_reg(ctx, WM8994_PWR_MANAGEMENT_4, &tmp, 2);
}
return ret;
}
/*******************************************************************************
* Function Name : wm8994_pwr_mgmt_4_dmic2r_ena
* Description : Digital microphone DMICDAT2 Right channel enable
* Input : uint16_t
* Output : None
* Return : Status [WM8994_ERROR, WM8994_OK]
*******************************************************************************/
int32_t wm8994_pwr_mgmt_4_dmic2r_ena(wm8994_ctx_t *ctx, uint16_t value)
{
int32_t ret;
uint16_t tmp = 0;
ret = wm8994_read_reg(ctx, WM8994_PWR_MANAGEMENT_4, &tmp, 2);
if(ret == 0)
{
tmp &= ~WM8994_PWR_MGMT_4_DMIC2R_ENA_MASK;
tmp |= value << WM8994_PWR_MGMT_4_DMIC2R_ENA_POSITION;
ret = wm8994_write_reg(ctx, WM8994_PWR_MANAGEMENT_4, &tmp, 2);
}
return ret;
}
/*******************************************************************************
* Function Name : wm8994_pwr_mgmt_4_dmic2l_ena
* Description : Digital microphone DMICDAT2 Left channel enable
* Input : uint16_t
* Output : None
* Return : Status [WM8994_ERROR, WM8994_OK]
*******************************************************************************/
int32_t wm8994_pwr_mgmt_4_dmic2l_ena(wm8994_ctx_t *ctx, uint16_t value)
{
int32_t ret;
uint16_t tmp = 0;
ret = wm8994_read_reg(ctx, WM8994_PWR_MANAGEMENT_4, &tmp, 2);
if(ret == 0)
{
tmp &= ~WM8994_PWR_MGMT_4_DMIC2L_ENA_MASK;
tmp |= value << WM8994_PWR_MGMT_4_DMIC2L_ENA_POSITION;
ret = wm8994_write_reg(ctx, WM8994_PWR_MANAGEMENT_4, &tmp, 2);
}
return ret;
}
/*******************************************************************************
* Function Name : wm8994_pwr_mgmt_4_aif1adc1r_ena
* Description : Enable AIF1ADC1 (Right) output path (AIF1, Timeslot0)
* Input : uint16_t
* Output : None
* Return : Status [WM8994_ERROR, WM8994_OK]
*******************************************************************************/
int32_t wm8994_pwr_mgmt_4_aif1adc1r_ena(wm8994_ctx_t *ctx, uint16_t value)
{
int32_t ret;
uint16_t tmp = 0;
ret = wm8994_read_reg(ctx, WM8994_PWR_MANAGEMENT_4, &tmp, 2);
if(ret == 0)
{
tmp &= ~WM8994_PWR_MGMT_4_AIF1ADC1R_ENA_MASK;
tmp |= value << WM8994_PWR_MGMT_4_AIF1ADC1R_ENA_POSITION;
ret = wm8994_write_reg(ctx, WM8994_PWR_MANAGEMENT_4, &tmp, 2);
}
return ret;
}
/*******************************************************************************
* Function Name : wm8994_pwr_mgmt_4_aif1adc1l_ena
* Description : Enable AIF1ADC1 (Left) output path (AIF1, Timeslot 0)
* Input : uint16_t
* Output : None
* Return : Status [WM8994_ERROR, WM8994_OK]
*******************************************************************************/
int32_t wm8994_pwr_mgmt_4_aif1adc1l_ena(wm8994_ctx_t *ctx, uint16_t value)
{
int32_t ret;