/
stm32h7xx_hal_rcc_ex.c
3935 lines (3368 loc) · 126 KB
/
stm32h7xx_hal_rcc_ex.c
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
/**
******************************************************************************
* @file stm32h7xx_hal_rcc_ex.c
* @author MCD Application Team
* @brief Extended RCC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities RCC extension peripheral:
* + Extended Peripheral Control functions
*
******************************************************************************
* @attention
*
* Copyright (c) 2017 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file in
* the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32h7xx_hal.h"
/** @addtogroup STM32H7xx_HAL_Driver
* @{
*/
/** @defgroup RCCEx RCCEx
* @brief RCC HAL module driver
* @{
*/
#ifdef HAL_RCC_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
/* Private defines -----------------------------------------------------------*/
/** @defgroup RCCEx_Private_defines RCCEx Private Defines
* @{
*/
#define PLL2_TIMEOUT_VALUE PLL_TIMEOUT_VALUE /* 2 ms */
#define PLL3_TIMEOUT_VALUE PLL_TIMEOUT_VALUE /* 2 ms */
#define DIVIDER_P_UPDATE 0U
#define DIVIDER_Q_UPDATE 1U
#define DIVIDER_R_UPDATE 2U
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup RCCEx_Private_Macros RCCEx Private Macros
* @{
*/
/**
* @}
*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
static HAL_StatusTypeDef RCCEx_PLL2_Config(RCC_PLL2InitTypeDef *pll2, uint32_t Divider);
static HAL_StatusTypeDef RCCEx_PLL3_Config(RCC_PLL3InitTypeDef *pll3, uint32_t Divider);
/* Exported functions --------------------------------------------------------*/
/** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions
* @{
*/
/** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions
* @brief Extended Peripheral Control functions
*
@verbatim
===============================================================================
##### Extended Peripheral Control functions #####
===============================================================================
[..]
This subsection provides a set of functions allowing to control the RCC Clocks
frequencies.
[..]
(@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to
select the RTC clock source; in this case the Backup domain will be reset in
order to modify the RTC Clock source, as consequence RTC registers (including
the backup registers) and RCC_BDCR register are set to their reset values.
@endverbatim
* @{
*/
/**
* @brief Initializes the RCC extended peripherals clocks according to the specified
* parameters in the RCC_PeriphCLKInitTypeDef.
* @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
* contains the configuration information for the Extended Peripherals
* clocks (SDMMC, CKPER, FMC, QSPI*, OSPI*, DSI, SPI45, SPDIF, DFSDM1, DFSDM2*, FDCAN, SWPMI, SAI23*,SAI2A*, SAI2B*, SAI1, SPI123,
* USART234578, USART16 (USART16910*), RNG, HRTIM1*, I2C123 (I2C1235*), USB, CEC, LPTIM1, LPUART1, I2C4, LPTIM2, LPTIM345, ADC,
* SAI4A*, SAI4B*, SPI6, RTC).
* @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select
* the RTC clock source; in this case the Backup domain will be reset in
* order to modify the RTC Clock source, as consequence RTC registers (including
* the backup registers) are set to their reset values.
*
* (*) : Available on some STM32H7 lines only.
*
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
{
uint32_t tmpreg;
uint32_t tickstart;
HAL_StatusTypeDef ret = HAL_OK; /* Intermediate status */
HAL_StatusTypeDef status = HAL_OK; /* Final status */
/*---------------------------- SPDIFRX configuration -------------------------------*/
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX)
{
switch (PeriphClkInit->SpdifrxClockSelection)
{
case RCC_SPDIFRXCLKSOURCE_PLL: /* PLL is used as clock source for SPDIFRX*/
/* Enable PLL1Q Clock output generated form System PLL . */
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
/* SPDIFRX clock source configuration done later after clock selection check */
break;
case RCC_SPDIFRXCLKSOURCE_PLL2: /* PLL2 is used as clock source for SPDIFRX*/
ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_R_UPDATE);
/* SPDIFRX clock source configuration done later after clock selection check */
break;
case RCC_SPDIFRXCLKSOURCE_PLL3: /* PLL3 is used as clock source for SPDIFRX*/
ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE);
/* SPDIFRX clock source configuration done later after clock selection check */
break;
case RCC_SPDIFRXCLKSOURCE_HSI:
/* Internal OSC clock is used as source of SPDIFRX clock*/
/* SPDIFRX clock source configuration done later after clock selection check */
break;
default:
ret = HAL_ERROR;
break;
}
if (ret == HAL_OK)
{
/* Set the source of SPDIFRX clock*/
__HAL_RCC_SPDIFRX_CONFIG(PeriphClkInit->SpdifrxClockSelection);
}
else
{
/* set overall return value */
status = ret;
}
}
/*---------------------------- SAI1 configuration -------------------------------*/
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1)
{
switch (PeriphClkInit->Sai1ClockSelection)
{
case RCC_SAI1CLKSOURCE_PLL: /* PLL is used as clock source for SAI1*/
/* Enable SAI Clock output generated form System PLL . */
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
/* SAI1 clock source configuration done later after clock selection check */
break;
case RCC_SAI1CLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI1*/
ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE);
/* SAI1 clock source configuration done later after clock selection check */
break;
case RCC_SAI1CLKSOURCE_PLL3: /* PLL3 is used as clock source for SAI1*/
ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE);
/* SAI1 clock source configuration done later after clock selection check */
break;
case RCC_SAI1CLKSOURCE_PIN:
/* External clock is used as source of SAI1 clock*/
/* SAI1 clock source configuration done later after clock selection check */
break;
case RCC_SAI1CLKSOURCE_CLKP:
/* HSI, HSE, or CSI oscillator is used as source of SAI1 clock */
/* SAI1 clock source configuration done later after clock selection check */
break;
default:
ret = HAL_ERROR;
break;
}
if (ret == HAL_OK)
{
/* Set the source of SAI1 clock*/
__HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection);
}
else
{
/* set overall return value */
status = ret;
}
}
#if defined(SAI3)
/*---------------------------- SAI2/3 configuration -------------------------------*/
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI23) == RCC_PERIPHCLK_SAI23)
{
switch (PeriphClkInit->Sai23ClockSelection)
{
case RCC_SAI23CLKSOURCE_PLL: /* PLL is used as clock source for SAI2/3 */
/* Enable SAI Clock output generated form System PLL . */
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
/* SAI2/3 clock source configuration done later after clock selection check */
break;
case RCC_SAI23CLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2/3 */
ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE);
/* SAI2/3 clock source configuration done later after clock selection check */
break;
case RCC_SAI23CLKSOURCE_PLL3: /* PLL3 is used as clock source for SAI2/3 */
ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE);
/* SAI2/3 clock source configuration done later after clock selection check */
break;
case RCC_SAI23CLKSOURCE_PIN:
/* External clock is used as source of SAI2/3 clock*/
/* SAI2/3 clock source configuration done later after clock selection check */
break;
case RCC_SAI23CLKSOURCE_CLKP:
/* HSI, HSE, or CSI oscillator is used as source of SAI2/3 clock */
/* SAI2/3 clock source configuration done later after clock selection check */
break;
default:
ret = HAL_ERROR;
break;
}
if (ret == HAL_OK)
{
/* Set the source of SAI2/3 clock*/
__HAL_RCC_SAI23_CONFIG(PeriphClkInit->Sai23ClockSelection);
}
else
{
/* set overall return value */
status = ret;
}
}
#endif /* SAI3 */
#if defined(RCC_CDCCIP1R_SAI2ASEL)
/*---------------------------- SAI2A configuration -------------------------------*/
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2A) == RCC_PERIPHCLK_SAI2A)
{
switch (PeriphClkInit->Sai2AClockSelection)
{
case RCC_SAI2ACLKSOURCE_PLL: /* PLL is used as clock source for SAI2A */
/* Enable SAI2A Clock output generated form System PLL . */
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
/* SAI2A clock source configuration done later after clock selection check */
break;
case RCC_SAI2ACLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2A */
ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE);
/* SAI2A clock source configuration done later after clock selection check */
break;
case RCC_SAI2ACLKSOURCE_PLL3: /* PLL3 is used as clock source for SAI2A */
ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE);
/* SAI2A clock source configuration done later after clock selection check */
break;
case RCC_SAI2ACLKSOURCE_PIN:
/* External clock is used as source of SAI2A clock*/
/* SAI2A clock source configuration done later after clock selection check */
break;
case RCC_SAI2ACLKSOURCE_CLKP:
/* HSI, HSE, or CSI oscillator is used as source of SAI2A clock */
/* SAI2A clock source configuration done later after clock selection check */
break;
case RCC_SAI2ACLKSOURCE_SPDIF:
/* SPDIF clock is used as source of SAI2A clock */
/* SAI2A clock source configuration done later after clock selection check */
break;
default:
ret = HAL_ERROR;
break;
}
if (ret == HAL_OK)
{
/* Set the source of SAI2A clock*/
__HAL_RCC_SAI2A_CONFIG(PeriphClkInit->Sai2AClockSelection);
}
else
{
/* set overall return value */
status = ret;
}
}
#endif /*SAI2A*/
#if defined(RCC_CDCCIP1R_SAI2BSEL)
/*---------------------------- SAI2B configuration -------------------------------*/
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2B) == RCC_PERIPHCLK_SAI2B)
{
switch (PeriphClkInit->Sai2BClockSelection)
{
case RCC_SAI2BCLKSOURCE_PLL: /* PLL is used as clock source for SAI2B */
/* Enable SAI Clock output generated form System PLL . */
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
/* SAI2B clock source configuration done later after clock selection check */
break;
case RCC_SAI2BCLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2B */
ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE);
/* SAI2B clock source configuration done later after clock selection check */
break;
case RCC_SAI2BCLKSOURCE_PLL3: /* PLL3 is used as clock source for SAI2B */
ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE);
/* SAI2B clock source configuration done later after clock selection check */
break;
case RCC_SAI2BCLKSOURCE_PIN:
/* External clock is used as source of SAI2B clock*/
/* SAI2B clock source configuration done later after clock selection check */
break;
case RCC_SAI2BCLKSOURCE_CLKP:
/* HSI, HSE, or CSI oscillator is used as source of SAI2B clock */
/* SAI2B clock source configuration done later after clock selection check */
break;
case RCC_SAI2BCLKSOURCE_SPDIF:
/* SPDIF clock is used as source of SAI2B clock */
/* SAI2B clock source configuration done later after clock selection check */
break;
default:
ret = HAL_ERROR;
break;
}
if (ret == HAL_OK)
{
/* Set the source of SAI2B clock*/
__HAL_RCC_SAI2B_CONFIG(PeriphClkInit->Sai2BClockSelection);
}
else
{
/* set overall return value */
status = ret;
}
}
#endif /*SAI2B*/
#if defined(SAI4)
/*---------------------------- SAI4A configuration -------------------------------*/
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI4A) == RCC_PERIPHCLK_SAI4A)
{
switch (PeriphClkInit->Sai4AClockSelection)
{
case RCC_SAI4ACLKSOURCE_PLL: /* PLL is used as clock source for SAI2*/
/* Enable SAI Clock output generated form System PLL . */
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
/* SAI1 clock source configuration done later after clock selection check */
break;
case RCC_SAI4ACLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2*/
ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE);
/* SAI2 clock source configuration done later after clock selection check */
break;
case RCC_SAI4ACLKSOURCE_PLL3: /* PLL3 is used as clock source for SAI2*/
ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE);
/* SAI1 clock source configuration done later after clock selection check */
break;
case RCC_SAI4ACLKSOURCE_PIN:
/* External clock is used as source of SAI2 clock*/
/* SAI2 clock source configuration done later after clock selection check */
break;
case RCC_SAI4ACLKSOURCE_CLKP:
/* HSI, HSE, or CSI oscillator is used as source of SAI2 clock */
/* SAI1 clock source configuration done later after clock selection check */
break;
#if defined(RCC_VER_3_0)
case RCC_SAI4ACLKSOURCE_SPDIF:
/* SPDIF clock is used as source of SAI4A clock */
/* SAI4A clock source configuration done later after clock selection check */
break;
#endif /* RCC_VER_3_0 */
default:
ret = HAL_ERROR;
break;
}
if (ret == HAL_OK)
{
/* Set the source of SAI4A clock*/
__HAL_RCC_SAI4A_CONFIG(PeriphClkInit->Sai4AClockSelection);
}
else
{
/* set overall return value */
status = ret;
}
}
/*---------------------------- SAI4B configuration -------------------------------*/
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI4B) == RCC_PERIPHCLK_SAI4B)
{
switch (PeriphClkInit->Sai4BClockSelection)
{
case RCC_SAI4BCLKSOURCE_PLL: /* PLL is used as clock source for SAI2*/
/* Enable SAI Clock output generated form System PLL . */
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
/* SAI1 clock source configuration done later after clock selection check */
break;
case RCC_SAI4BCLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2*/
ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE);
/* SAI2 clock source configuration done later after clock selection check */
break;
case RCC_SAI4BCLKSOURCE_PLL3: /* PLL3 is used as clock source for SAI2*/
ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE);
/* SAI1 clock source configuration done later after clock selection check */
break;
case RCC_SAI4BCLKSOURCE_PIN:
/* External clock is used as source of SAI2 clock*/
/* SAI2 clock source configuration done later after clock selection check */
break;
case RCC_SAI4BCLKSOURCE_CLKP:
/* HSI, HSE, or CSI oscillator is used as source of SAI2 clock */
/* SAI1 clock source configuration done later after clock selection check */
break;
#if defined(RCC_VER_3_0)
case RCC_SAI4BCLKSOURCE_SPDIF:
/* SPDIF clock is used as source of SAI4B clock */
/* SAI4B clock source configuration done later after clock selection check */
break;
#endif /* RCC_VER_3_0 */
default:
ret = HAL_ERROR;
break;
}
if (ret == HAL_OK)
{
/* Set the source of SAI4B clock*/
__HAL_RCC_SAI4B_CONFIG(PeriphClkInit->Sai4BClockSelection);
}
else
{
/* set overall return value */
status = ret;
}
}
#endif /*SAI4*/
#if defined(QUADSPI)
/*---------------------------- QSPI configuration -------------------------------*/
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_QSPI) == RCC_PERIPHCLK_QSPI)
{
switch (PeriphClkInit->QspiClockSelection)
{
case RCC_QSPICLKSOURCE_PLL: /* PLL is used as clock source for QSPI*/
/* Enable QSPI Clock output generated form System PLL . */
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
/* QSPI clock source configuration done later after clock selection check */
break;
case RCC_QSPICLKSOURCE_PLL2: /* PLL2 is used as clock source for QSPI*/
ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_R_UPDATE);
/* QSPI clock source configuration done later after clock selection check */
break;
case RCC_QSPICLKSOURCE_CLKP:
/* HSI, HSE, or CSI oscillator is used as source of QSPI clock */
/* QSPI clock source configuration done later after clock selection check */
break;
case RCC_QSPICLKSOURCE_D1HCLK:
/* Domain1 HCLK clock selected as QSPI kernel peripheral clock */
break;
default:
ret = HAL_ERROR;
break;
}
if (ret == HAL_OK)
{
/* Set the source of QSPI clock*/
__HAL_RCC_QSPI_CONFIG(PeriphClkInit->QspiClockSelection);
}
else
{
/* set overall return value */
status = ret;
}
}
#endif /*QUADSPI*/
#if defined(OCTOSPI1) || defined(OCTOSPI2)
/*---------------------------- OCTOSPI configuration -------------------------------*/
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_OSPI) == RCC_PERIPHCLK_OSPI)
{
switch (PeriphClkInit->OspiClockSelection)
{
case RCC_OSPICLKSOURCE_PLL: /* PLL is used as clock source for OSPI*/
/* Enable OSPI Clock output generated form System PLL . */
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
/* OSPI clock source configuration done later after clock selection check */
break;
case RCC_OSPICLKSOURCE_PLL2: /* PLL2 is used as clock source for OSPI*/
ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_R_UPDATE);
/* OSPI clock source configuration done later after clock selection check */
break;
case RCC_OSPICLKSOURCE_CLKP:
/* HSI, HSE, or CSI oscillator is used as source of OSPI clock */
/* OSPI clock source configuration done later after clock selection check */
break;
case RCC_OSPICLKSOURCE_HCLK:
/* HCLK clock selected as OSPI kernel peripheral clock */
break;
default:
ret = HAL_ERROR;
break;
}
if (ret == HAL_OK)
{
/* Set the source of OSPI clock*/
__HAL_RCC_OSPI_CONFIG(PeriphClkInit->OspiClockSelection);
}
else
{
/* set overall return value */
status = ret;
}
}
#endif /*OCTOSPI*/
/*---------------------------- SPI1/2/3 configuration -------------------------------*/
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI123) == RCC_PERIPHCLK_SPI123)
{
switch (PeriphClkInit->Spi123ClockSelection)
{
case RCC_SPI123CLKSOURCE_PLL: /* PLL is used as clock source for SPI1/2/3 */
/* Enable SPI Clock output generated form System PLL . */
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
/* SPI1/2/3 clock source configuration done later after clock selection check */
break;
case RCC_SPI123CLKSOURCE_PLL2: /* PLL2 is used as clock source for SPI1/2/3 */
ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE);
/* SPI1/2/3 clock source configuration done later after clock selection check */
break;
case RCC_SPI123CLKSOURCE_PLL3: /* PLL3 is used as clock source for SPI1/2/3 */
ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE);
/* SPI1/2/3 clock source configuration done later after clock selection check */
break;
case RCC_SPI123CLKSOURCE_PIN:
/* External clock is used as source of SPI1/2/3 clock*/
/* SPI1/2/3 clock source configuration done later after clock selection check */
break;
case RCC_SPI123CLKSOURCE_CLKP:
/* HSI, HSE, or CSI oscillator is used as source of SPI1/2/3 clock */
/* SPI1/2/3 clock source configuration done later after clock selection check */
break;
default:
ret = HAL_ERROR;
break;
}
if (ret == HAL_OK)
{
/* Set the source of SPI1/2/3 clock*/
__HAL_RCC_SPI123_CONFIG(PeriphClkInit->Spi123ClockSelection);
}
else
{
/* set overall return value */
status = ret;
}
}
/*---------------------------- SPI4/5 configuration -------------------------------*/
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI45) == RCC_PERIPHCLK_SPI45)
{
switch (PeriphClkInit->Spi45ClockSelection)
{
case RCC_SPI45CLKSOURCE_PCLK2: /* CD/D2 PCLK2 as clock source for SPI4/5 */
/* SPI4/5 clock source configuration done later after clock selection check */
break;
case RCC_SPI45CLKSOURCE_PLL2: /* PLL2 is used as clock source for SPI4/5 */
ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE);
/* SPI4/5 clock source configuration done later after clock selection check */
break;
case RCC_SPI45CLKSOURCE_PLL3: /* PLL3 is used as clock source for SPI4/5 */
ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE);
/* SPI4/5 clock source configuration done later after clock selection check */
break;
case RCC_SPI45CLKSOURCE_HSI:
/* HSI oscillator clock is used as source of SPI4/5 clock*/
/* SPI4/5 clock source configuration done later after clock selection check */
break;
case RCC_SPI45CLKSOURCE_CSI:
/* CSI oscillator clock is used as source of SPI4/5 clock */
/* SPI4/5 clock source configuration done later after clock selection check */
break;
case RCC_SPI45CLKSOURCE_HSE:
/* HSE, oscillator is used as source of SPI4/5 clock */
/* SPI4/5 clock source configuration done later after clock selection check */
break;
default:
ret = HAL_ERROR;
break;
}
if (ret == HAL_OK)
{
/* Set the source of SPI4/5 clock*/
__HAL_RCC_SPI45_CONFIG(PeriphClkInit->Spi45ClockSelection);
}
else
{
/* set overall return value */
status = ret;
}
}
/*---------------------------- SPI6 configuration -------------------------------*/
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI6) == RCC_PERIPHCLK_SPI6)
{
switch (PeriphClkInit->Spi6ClockSelection)
{
case RCC_SPI6CLKSOURCE_PCLK4: /* SRD/D3 PCLK1 (PCLK4) as clock source for SPI6*/
/* SPI6 clock source configuration done later after clock selection check */
break;
case RCC_SPI6CLKSOURCE_PLL2: /* PLL2 is used as clock source for SPI6*/
ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE);
/* SPI6 clock source configuration done later after clock selection check */
break;
case RCC_SPI6CLKSOURCE_PLL3: /* PLL3 is used as clock source for SPI6*/
ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE);
/* SPI6 clock source configuration done later after clock selection check */
break;
case RCC_SPI6CLKSOURCE_HSI:
/* HSI oscillator clock is used as source of SPI6 clock*/
/* SPI6 clock source configuration done later after clock selection check */
break;
case RCC_SPI6CLKSOURCE_CSI:
/* CSI oscillator clock is used as source of SPI6 clock */
/* SPI6 clock source configuration done later after clock selection check */
break;
case RCC_SPI6CLKSOURCE_HSE:
/* HSE, oscillator is used as source of SPI6 clock */
/* SPI6 clock source configuration done later after clock selection check */
break;
#if defined(RCC_SPI6CLKSOURCE_PIN)
case RCC_SPI6CLKSOURCE_PIN:
/* 2S_CKIN is used as source of SPI6 clock */
/* SPI6 clock source configuration done later after clock selection check */
break;
#endif
default:
ret = HAL_ERROR;
break;
}
if (ret == HAL_OK)
{
/* Set the source of SPI6 clock*/
__HAL_RCC_SPI6_CONFIG(PeriphClkInit->Spi6ClockSelection);
}
else
{
/* set overall return value */
status = ret;
}
}
#if defined(DSI)
/*---------------------------- DSI configuration -------------------------------*/
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DSI) == RCC_PERIPHCLK_DSI)
{
switch (PeriphClkInit->DsiClockSelection)
{
case RCC_DSICLKSOURCE_PLL2: /* PLL2 is used as clock source for DSI*/
ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE);
/* DSI clock source configuration done later after clock selection check */
break;
case RCC_DSICLKSOURCE_PHY:
/* PHY is used as clock source for DSI*/
/* DSI clock source configuration done later after clock selection check */
break;
default:
ret = HAL_ERROR;
break;
}
if (ret == HAL_OK)
{
/* Set the source of DSI clock*/
__HAL_RCC_DSI_CONFIG(PeriphClkInit->DsiClockSelection);
}
else
{
/* set overall return value */
status = ret;
}
}
#endif /*DSI*/
#if defined(FDCAN1) || defined(FDCAN2)
/*---------------------------- FDCAN configuration -------------------------------*/
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN)
{
switch (PeriphClkInit->FdcanClockSelection)
{
case RCC_FDCANCLKSOURCE_PLL: /* PLL is used as clock source for FDCAN*/
/* Enable FDCAN Clock output generated form System PLL . */
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
/* FDCAN clock source configuration done later after clock selection check */
break;
case RCC_FDCANCLKSOURCE_PLL2: /* PLL2 is used as clock source for FDCAN*/
ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE);
/* FDCAN clock source configuration done later after clock selection check */
break;
case RCC_FDCANCLKSOURCE_HSE:
/* HSE is used as clock source for FDCAN*/
/* FDCAN clock source configuration done later after clock selection check */
break;
default:
ret = HAL_ERROR;
break;
}
if (ret == HAL_OK)
{
/* Set the source of FDCAN clock*/
__HAL_RCC_FDCAN_CONFIG(PeriphClkInit->FdcanClockSelection);
}
else
{
/* set overall return value */
status = ret;
}
}
#endif /*FDCAN1 || FDCAN2*/
/*---------------------------- FMC configuration -------------------------------*/
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FMC) == RCC_PERIPHCLK_FMC)
{
switch (PeriphClkInit->FmcClockSelection)
{
case RCC_FMCCLKSOURCE_PLL: /* PLL is used as clock source for FMC*/
/* Enable FMC Clock output generated form System PLL . */
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
/* FMC clock source configuration done later after clock selection check */
break;
case RCC_FMCCLKSOURCE_PLL2: /* PLL2 is used as clock source for FMC*/
ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_R_UPDATE);
/* FMC clock source configuration done later after clock selection check */
break;
case RCC_FMCCLKSOURCE_CLKP:
/* HSI, HSE, or CSI oscillator is used as source of FMC clock */
/* FMC clock source configuration done later after clock selection check */
break;
case RCC_FMCCLKSOURCE_HCLK:
/* D1/CD HCLK clock selected as FMC kernel peripheral clock */
break;
default:
ret = HAL_ERROR;
break;
}
if (ret == HAL_OK)
{
/* Set the source of FMC clock*/
__HAL_RCC_FMC_CONFIG(PeriphClkInit->FmcClockSelection);
}
else
{
/* set overall return value */
status = ret;
}
}
/*---------------------------- RTC configuration -------------------------------*/
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)
{
/* check for RTC Parameters used to output RTCCLK */
assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
/* Enable write access to Backup domain */
SET_BIT(PWR->CR1, PWR_CR1_DBP);
/* Wait for Backup domain Write protection disable */
tickstart = HAL_GetTick();
while ((PWR->CR1 & PWR_CR1_DBP) == 0U)
{
if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
{
ret = HAL_TIMEOUT;
break;
}
}
if (ret == HAL_OK)
{
/* Reset the Backup domain only if the RTC Clock source selection is modified */
if ((RCC->BDCR & RCC_BDCR_RTCSEL) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))
{
/* Store the content of BDCR register before the reset of Backup Domain */
tmpreg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
/* RTC Clock selection can be changed only if the Backup Domain is reset */
__HAL_RCC_BACKUPRESET_FORCE();
__HAL_RCC_BACKUPRESET_RELEASE();
/* Restore the Content of BDCR register */
RCC->BDCR = tmpreg;
}
/* If LSE is selected as RTC clock source (and enabled prior to Backup Domain reset), wait for LSE reactivation */
if (PeriphClkInit->RTCClockSelection == RCC_RTCCLKSOURCE_LSE)
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
/* Wait till LSE is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U)
{
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
{
ret = HAL_TIMEOUT;
break;
}
}
}
if (ret == HAL_OK)
{
__HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
}
else
{
/* set overall return value */
status = ret;
}
}
else
{
/* set overall return value */
status = ret;
}
}
/*-------------------------- USART1/6 configuration --------------------------*/
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART16) == RCC_PERIPHCLK_USART16)
{
switch (PeriphClkInit->Usart16ClockSelection)
{
case RCC_USART16CLKSOURCE_PCLK2: /* CD/D2 PCLK2 as clock source for USART1/6 */
/* USART1/6 clock source configuration done later after clock selection check */
break;
case RCC_USART16CLKSOURCE_PLL2: /* PLL2 is used as clock source for USART1/6 */
ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE);
/* USART1/6 clock source configuration done later after clock selection check */
break;
case RCC_USART16CLKSOURCE_PLL3: /* PLL3 is used as clock source for USART1/6 */
ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE);
/* USART1/6 clock source configuration done later after clock selection check */
break;
case RCC_USART16CLKSOURCE_HSI:
/* HSI oscillator clock is used as source of USART1/6 clock */
/* USART1/6 clock source configuration done later after clock selection check */
break;
case RCC_USART16CLKSOURCE_CSI:
/* CSI oscillator clock is used as source of USART1/6 clock */
/* USART1/6 clock source configuration done later after clock selection check */
break;
case RCC_USART16CLKSOURCE_LSE:
/* LSE, oscillator is used as source of USART1/6 clock */
/* USART1/6 clock source configuration done later after clock selection check */
break;
default:
ret = HAL_ERROR;
break;
}
if (ret == HAL_OK)
{
/* Set the source of USART1/6 clock */