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stm32mp1: Add STMicroelectronics proprietary SMC for PWR
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Add proprietary SMC to access to secure PWR resource provided
or protected by secure world, OP-TEE or TF-A SP-MIN.

File alignment with TF-A plat/st/stm32mp1/include/stm32mp1_smc.h.

NOT_UPSTREAMABLE

Change-Id: I9f54d8f1e560b3a7077f515d0f0f28bd3c346e6d
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/173696
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/271393
Reviewed-by: CITOOLS <MDG-smet-aci-reviews@list.st.com>
Reviewed-by: CIBUILD <MDG-smet-aci-builds@list.st.com>
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patrickdelaunay committed Apr 20, 2023
1 parent 3015567 commit d64e125
Showing 1 changed file with 33 additions and 5 deletions.
38 changes: 33 additions & 5 deletions arch/arm/mach-stm32mp/include/mach/stm32mp1_smc.h
Original file line number Diff line number Diff line change
Expand Up @@ -15,11 +15,39 @@
* for SiP (silicon Partner)
* http://infocenter.arm.com/help/topic/com.arm.doc.den0028a/index.html
*/
#define STM32_SMC_VERSION 0x82000000

/* Secure Service access from Non-secure */

/*
* STM32_SMC_PWR call API
*
* Argument a0: (input) SMCC ID.
* (output) Status return code.
* Argument a1: (input) Service ID (STM32_SMC_REG_xxx).
* Argument a2: (input) Register offset or physical address.
* (output) Register read value, if applicable.
* Argument a3: (input) Register target value if applicable.
*/
#define STM32_SMC_PWR 0x82001001

/*
* STM32_SMC_BSEC call API
*
* Argument a0: (input) SMCC ID
* (output) status return code
* Argument a1: (input) Service ID (STM32_SMC_BSEC_xxx)
* Argument a2: (input) OTP index
* (output) OTP read value, if applicable
* Argument a3: (input) OTP value if applicable
*/
#define STM32_SMC_BSEC 0x82001003

/* Service ID for STM32_SMC_PWR */
#define STM32_SMC_REG_READ 0x0
#define STM32_SMC_REG_WRITE 0x1
#define STM32_SMC_REG_SET 0x2
#define STM32_SMC_REG_CLEAR 0x3

/* Service for BSEC */
#define STM32_SMC_READ_SHADOW 0x01
#define STM32_SMC_PROG_OTP 0x02
Expand All @@ -30,10 +58,10 @@
#define STM32_SMC_WRLOCK_OTP 0x07

/* SMC error codes */
#define STM32_SMC_OK 0x0
#define STM32_SMC_NOT_SUPPORTED -1
#define STM32_SMC_FAILED -2
#define STM32_SMC_INVALID_PARAMS -3
#define STM32_SMC_OK 0x00000000U
#define STM32_SMC_NOT_SUPPORTED 0xffffffffU
#define STM32_SMC_FAILED 0xfffffffeU
#define STM32_SMC_INVALID_PARAMS 0xfffffffdU

#define stm32_smc_exec(svc, op, data1, data2) \
stm32_smc(svc, op, data1, data2, NULL)
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