/
oss-cad-suite-nightly.json
31 lines (31 loc) 路 1.23 KB
/
oss-cad-suite-nightly.json
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{
"version": "2024-05-02",
"description": "Open source digital design and verification tools. Includes tools for RTL synthesis, formal hardware verification, place & route, FPGA programming, and testing with support for HDLs like Verilog, Migen and Amaranth.",
"homepage": "https://github.com/YosysHQ/oss-cad-suite-build",
"license": "ISC",
"architecture": {
"64bit": {
"url": "https://github.com/YosysHQ/oss-cad-suite-build/releases/download/2024-05-02/oss-cad-suite-windows-x64-20240502.exe#/dl.7z",
"hash": "0a391d6eddf9796bb62b12326e487a1a1e2f62dc0b3aaa90818cbfa3f1307984"
}
},
"extract_dir": "oss-cad-suite",
"pre_install": "Set-Content -Path \"$dir\\start.bat\" -Value \"@cmd /k $dir\\environment.bat\"",
"bin": [
[
"start.bat",
"oss-cad"
]
],
"checkver": {
"url": "https://github.com/YosysHQ/oss-cad-suite-build/releases",
"regex": "tree\\/([\\d-]+)"
},
"autoupdate": {
"architecture": {
"64bit": {
"url": "https://github.com/YosysHQ/oss-cad-suite-build/releases/download/$version/oss-cad-suite-windows-x64-$cleanVersion.exe#/dl.7z"
}
}
}
}