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Add more SystemRDL examples and resulting SystemVerilog #6

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Silicon1602 opened this issue Oct 24, 2021 · 0 comments
Open
6 tasks done

Add more SystemRDL examples and resulting SystemVerilog #6

Silicon1602 opened this issue Oct 24, 2021 · 0 comments
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documentation Improvements or additions to documentation

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Silicon1602 commented Oct 24, 2021 •
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The examples directory is meant to show off certain SystemRDL constructs and what SystemVerilog will be created

  • Counters
  • Hierarchical Interrupts
  • Enums
  • Aliases (including external registers)
  • Interrupts (elaborate example from spec)
  • Parameters
@Silicon1602 Silicon1602 added the documentation Improvements or additions to documentation label Oct 24, 2021
@Silicon1602 Silicon1602 self-assigned this Oct 24, 2021
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