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Splittig UART packages #13

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silver-kuusik opened this issue Aug 9, 2021 · 1 comment
Open

Splittig UART packages #13

silver-kuusik opened this issue Aug 9, 2021 · 1 comment
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@silver-kuusik
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Hi, wondering about when one HDLC frame is in two UART packages or if 2 HDLC frames are in 1 UART package. Should we implement splitting and concatenating UART packages (HDLC frames) ourself or should this be part of this library ?

In this example, I have to send the same frame twice as it is not recognized, because it is in 2 UART packages:

send data: b'~\xff\x10\x08\x01"!\x10\x00\x1a\x15\x08\x00\x10\x00\x18\x00"\x05extra*\x06gitrev"\x06\x08\x00\x10\x00\x18\x00\x1dU~' of len: 43
read data: b'~\xff\x01\x0e\xe1~~\xff\x10\x08\x01".\x10\x86' of len: 15
read data: b'\x12\x1a\x16\x08\x00\x10\x04\x18\x00"\x04-rc1*\x084354d098"\x11\x08\xb2\x80\xd0\x02\x10\xac\xc4\xaa\x93\x06\x18\xee\xd8\x91\xe3\x06\\\xa9~' of len: 47
send data: b'~\xff\x10\x08\x01"!\x10\x00\x1a\x15\x08\x00\x10\x00\x18\x00"\x05extra*\x06gitrev"\x06\x08\x00\x10\x00\x18\x00\x1dU~' of len: 43
read data: b'~\xff\x01\x0e\xe1~~' of len: 7
read data: b'\xff\x10\x08\x01".\x10\x86\x12\x1a\x16\x08\x00\x10\x04\x18\x00"\x04-rc1*\x084354d098"\x11\x08\xb2\x80\xd0\x02\x10\xac\xc4\xaa\x93\x06\x18\xee\xd8\x91\xe3\x06\\\xa9~' of len: 55
send data: b'~\xff!\x0c\xc0~' of len: 6
@silver-kuusik
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silver-kuusik commented Aug 11, 2021

Currently how I solved it is by changing the HDLC read callback function and setting the read timeout of serial to 0:

# Callback function for HDLC
def read_uart():
    global uart_data

    uart_data += uart.read()

    if len(uart_data) > 1 and uart_data.endswith(b'~'):
        print("read data:", uart_data, "of len:", len(uart_data))
        ret_data = uart_data
        uart_data = b''
        return ret_data

    return b''

@SkypLabs SkypLabs added the question Question label Sep 1, 2021
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