Documentation / example usage for Axi4ReadOnlyMasterAgent and Axi4WriteOnlyMasterAgent

[KireinaHoro]

I'm trying to write a simulation bench for an AXI slave DUT. It seems like one should extend these abstract classes and override genAddress, mappingAllocate and mappingFree and then call genCmd to initiate a bus transfer (which would call these overriden callbacks), but it is a bit confusing on how one would implement a simple bus reader / writer in this way. Is there an example on how these classes should be used?

[KireinaHoro]

It seems like a lot of data are hard-coded to random; for example:

SpinalHDL/lib/src/main/scala/spinal/lib/bus/amba4/axi/sim/Agent.scala

Lines 116 to 122 in 4d2f814

	wQueue.enqueue { () =>
	w.data.randomize()
	val bytesInBeat = sizeByte - (beatOffsetCache % sizeByte)
	if(busConfig.useStrb) w.strb #= ((BigInt(bytesInBeat, simRandom)) << beatOffsetCache) & ((BigInt(1) << size)-1)
	if(busConfig.useWUser) w.user.randomize()
	if(busConfig.useLast) w.last #= beat == len
	}

The write channel StreamDriver always write a randomized data beat with no way to change it to anything meaningful.

[Readon]

There are some in the lib's tester

[Readon]

It seems like a lot of data are hard-coded to random; for example:

SpinalHDL/lib/src/main/scala/spinal/lib/bus/amba4/axi/sim/Agent.scala

Lines 116 to 122 in 4d2f814

	wQueue.enqueue { () =>
	w.data.randomize()
	val bytesInBeat = sizeByte - (beatOffsetCache % sizeByte)
	if(busConfig.useStrb) w.strb #= ((BigInt(bytesInBeat, simRandom)) << beatOffsetCache) & ((BigInt(1) << size)-1)
	if(busConfig.useWUser) w.user.randomize()
	if(busConfig.useLast) w.last #= beat == len
	}

The write channel StreamDriver always write a randomized data beat with no way to change it to anything meaningful.

Yes, this is normally adopted policy of simulation framework.

[KireinaHoro]

@Readon thanks for the explanation! I see that the intended use case is to have the master generate the commands (in case of writes, with random data) and then have a separate monitor to record the data into something like a scoreboard for comparison with the downstream bus master's behavior.

IMO this model does not work very well with modules that are not a bus adapter (e.g. to another bus protocol / memory interface). For example it couldn't drive a slave that behaves like the following:

• the master reads from a memory address to get a token
• the master does something based on the token
• the master returns the token back to the slave by writing it to a memory address

I can think of overriding (and copying most of) genCmd to allow for a user-defined data packet, but I'm not sure if that's the way to go here.

[andreasWallner]

I'm not sure that the current MasterAgent is going to help you much here as it is: as far as I can tell it was mainly built for verification of the AXI infrastructure, and the components that would need more targeted reads/writes (like the SlaveFactory) are still being tested with the original cocotb test cases.

Note on genCmd: you normally don't need to call it, the Stream drivers that drive the streams that comprise the bus will take care of that (e.g. Agent.scala@137).

For other busses there are master agents that allow for much more freedom, for AXI there currently isn't.