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timing: Adding a basic cell timing fuzzer
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Signed-off-by: David Shah <dave@ds0.me>
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gatecat committed Oct 28, 2018
1 parent 8fed66c commit 40bd1fe
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Showing 7 changed files with 33 additions and 11 deletions.
2 changes: 1 addition & 1 deletion environment.sh
Expand Up @@ -13,7 +13,7 @@ fi
SCRIPT_PATH=$(readlink -f "${BASH_SOURCE:-$0}")
SCRIPT_DIR=$(dirname "$SCRIPT_PATH")
LIBTRELLIS_DIR="${SCRIPT_DIR}/libtrellis"
PYTHONLIBS_DIR="${SCRIPT_DIR}/util:${SCRIPT_DIR}/util/common:${SCRIPT_DIR}/util/fuzz"
PYTHONLIBS_DIR="${SCRIPT_DIR}/util:${SCRIPT_DIR}/util/common:${SCRIPT_DIR}/util/fuzz:${SCRIPT_DIR}/timing/util"
export PYTHONPATH="${LIBTRELLIS_DIR}:${PYTHONLIBS_DIR}:${PYTHONPATH}"

USER_ENV="${SCRIPT_DIR}/user_environment.sh"
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1 change: 1 addition & 0 deletions timing/fuzzers/.gitignore
@@ -0,0 +1 @@
work/
9 changes: 9 additions & 0 deletions timing/fuzzers/010-basic-cells/fuzzer.py
@@ -0,0 +1,9 @@
import cell_fuzzers


def main():
cell_fuzzers.build_and_add(["../../resource/picorv32_large.v", "../../resource/distributed_ram.v"])


if __name__ == "__main__":
main()
6 changes: 3 additions & 3 deletions timing/resource/distributed_ram.v
Expand Up @@ -6,14 +6,14 @@ module top(
input [3:0] wad,
output [3:0] q,
input rck,
output [3:0] qq
output reg [3:0] qq
);
DPR16X4C ram_0 (
.DI0(di[0]), .DI1(di[1]), .DI2(di[2]), .DI3(di[3]),
.WCK(wck), .WRE(wre0),
.RAD0(rad[0]), .RAD1(rad[1]), .RAD2(rad[2]), .RAD3(rad[3]),
.WAD0(rad[0]), .WAD1(rad[1]), .WAD2(rad[2]), .WAD3(rad[3]),
.Q0(q[0]), .Q1(q[1]), .Q2(q[2]), .Q3(q[3])
.DO0(q[0]), .DO1(q[1]), .DO2(q[2]), .DO3(q[3])
);

wire [3:0] qp;
Expand All @@ -22,7 +22,7 @@ module top(
.WCK(wck), .WRE(wre1),
.RAD0(rad[0]), .RAD1(rad[1]), .RAD2(rad[2]), .RAD3(rad[3]),
.WAD0(rad[0]), .WAD1(rad[1]), .WAD2(rad[2]), .WAD3(rad[3]),
.Q0(qp[0]), .Q1(qp[1]), .Q2(qp[2]), .Q3(qp[3])
.DO0(qp[0]), .DO1(qp[1]), .DO2(qp[2]), .DO3(qp[3])
);

always @(posedge rck)
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4 changes: 2 additions & 2 deletions timing/util/cell_fuzzers.py
Expand Up @@ -30,12 +30,12 @@ def build_and_add(designs, density="45"):
def per_job(job):
grade, cfg = job
cfg.setup(skip_specimen=True)
bitf = cfg.build_design(cfg.ncl, {}, backanno=True)
bitf = cfg.build_design(cfg.ncl, {}, backanno=True, substitute=False)
sdf = bitf.replace(".bit", ".sdf")
sdfs[grade].append(sdf)

fuzzloops.parallel_foreach(jobs, per_job)
for grade in sdfs.keys():
db = timing_dbs.cells_db_path("ECP5", grade)
for sdf in sdfs["grade"]:
for sdf in sdfs[grade]:
cell_timings.add_sdf_to_database(db, sdf)
10 changes: 8 additions & 2 deletions timing/util/timing_dbs.py
@@ -1,6 +1,12 @@
import database
from os import path

import os

def cells_db_path(family, speedgrade):
return path.join(database.get_db_root(), family, "timing", "speed_{}".format(speedgrade), "cells.json")
tmgroot = path.join(database.get_db_root(), family, "timing")
if not path.exists(tmgroot):
os.mkdir(tmgroot)
sgroot = path.join(tmgroot, "speed_{}".format(speedgrade))
if not path.exists(sgroot):
os.mkdir(sgroot)
return path.join(sgroot, "cells.json")
12 changes: 9 additions & 3 deletions util/fuzz/fuzzconfig.py
Expand Up @@ -40,7 +40,7 @@ def setup(self, skip_specimen=False):
if not skip_specimen:
self.build_design(self.ncl, {})

def build_design(self, des_template, substitutions, prefix="", no_trce=True, backanno=False):
def build_design(self, des_template, substitutions, prefix="", no_trce=True, backanno=False, substitute=True):
"""
Run Diamond on a given design template, applying a map of substitutions, plus some standard substitutions
if not overriden.
Expand Down Expand Up @@ -69,11 +69,17 @@ def build_design(self, des_template, substitutions, prefix="", no_trce=True, bac
os.remove(bitfile)
with open(des_template, "r") as inf:
with open(desfile, "w") as ouf:
ouf.write(Template(inf.read()).substitute(**subst))
if substitute:
ouf.write(Template(inf.read()).substitute(**subst))
else:
ouf.write(inf.read())
if path.exists(lpf_template):
with open(lpf_template, "r") as inf:
with open(lpffile, "w") as ouf:
ouf.write(Template(inf.read()).substitute(**subst))
if substitute:
ouf.write(Template(inf.read()).substitute(**subst))
else:
ouf.write(inf.read())
if path.exists(prf_template):
with open(prf_template, "r") as inf:
with open(prffile, "w") as ouf:
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