WIP techmap IBUF/OBUF primitives

Commented portions don't work yet: Error 1: Type: Packing File: /build/source/vpr/src/pack/cluster.cpp Line: 2058 Message: Can not find any logic block that can implement molecule. Atom inbuf (INBUF_VPR)
f4pga · Sep 13, 2019 · b3e8226 · b3e8226
1 parent ad4560c
commit b3e8226
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Showing 8 changed files with 81 additions and 32 deletions.
diff --git a/common/wire.eblif b/common/wire.eblif
@@ -1,6 +1,11 @@
 .model top
 .inputs di
 .outputs do
+# .subckt INBUF_VPR OUT=di_buf PAD=di INTERMDISABLE=$true IBUFDISABLE=$true DIFFI_IN=$true
+# .cname inbuf
+# .subckt OUTBUF_VPR IN=do_buf OUT=do TRI=$true
+# .cname outbuf
+# .names di_buf do_buf
 .names di do
 1 1
 .end
diff --git a/xc7/primitives/ilogice3/ilogice3.pb_type.xml b/xc7/primitives/ilogice3/ilogice3.pb_type.xml
@@ -30,15 +30,8 @@
   <output name="Q8" num_pins="1"/>
   <output name="SHIFTOUT1" num_pins="1"/>
   <output name="SHIFTOUT2" num_pins="1"/>
-  <pb_type name="inpad" blif_model=".input" num_pb="1">
-    <output name="inpad" num_pins="1"/>
-    <metadata>
-      <meta name="type">bel</meta>
-      <meta name="subtype">input</meta>
-    </metadata>
-  </pb_type>
   <interconnect>
-    <direct name="D_O" input="inpad.inpad" output="ILOGICE3.O"/>
+    <direct name="D_O" input="ILOGICE3.D" output="ILOGICE3.O"/>
   </interconnect>
   <!-- TODO -->
 </pb_type>
diff --git a/xc7/primitives/iob33m/iob33m.model.xml b/xc7/primitives/iob33m/iob33m.model.xml
@@ -1,22 +1,24 @@
 <models xmlns:xi="http://www.w3.org/2001/XInclude">
-  <model name="OUTBUF">
+  <!--
+  <model name="OUTBUF_VPR">
     <input_ports>
-      <port name="IN"/>
+      <port name="IN" combinational_sink_ports="OUT"/>
       <port name="TRI"/>
     </input_ports>
     <output_ports>
       <port name="OUT"/>
     </output_ports>
   </model>
-  <model name="INBUF">
+  <model name="INBUF_VPR">
     <input_ports>
       <port name="DIFFI_IN"/>
       <port name="IBUFDISABLE"/>
       <port name="INTERMDISABLE"/>
-      <port name="PAD"/>
+      <port name="PAD" combinational_sink_ports="OUT"/>
     </input_ports>
     <output_ports>
       <port name="OUT"/>
     </output_ports>
   </model>
+  -->
 </models>
diff --git a/xc7/primitives/iob33m/iob33m.pb_type.xml b/xc7/primitives/iob33m/iob33m.pb_type.xml
@@ -13,19 +13,22 @@
   <input name="PU_INT_EN" num_pins="1"/>
   <input name="T" num_pins="1"/>
   <output name="T_OUT" num_pins="1"/>
-  <pb_type name="INBUF" blif_model=".subckt INBUF" num_pb="1">
+  <!--
+  <pb_type name="INBUF_VPR" blif_model=".subckt INBUF_VPR" num_pb="1">
     <input name="DIFFI_IN" num_pins="1"/>
     <input name="IBUFDISABLE" num_pins="1"/>
     <input name="INTERMDISABLE" num_pins="1"/>
     <input name="PAD" num_pins="1"/>
     <output name="OUT" num_pins="1"/>
+    <delay_constant max="10e-12" in_port="PAD"  out_port="OUT"/>
   </pb_type>
-  <pb_type name="OUTBUF" blif_model=".subckt OUTBUF" num_pb="1">
+  <pb_type name="OUTBUF_VPR" blif_model=".subckt OUTBUF_VPR" num_pb="1">
     <input name="IN" num_pins="1"/>
     <input name="TRI" num_pins="1"/>
     <output name="OUT" num_pins="1"/>
+    <delay_constant max="10e-12" in_port="IN"  out_port="OUT"/>
   </pb_type>
-  <!--
+  -->
   <pb_type name="inpad" blif_model=".input" num_pb="1">
     <output name="inpad" num_pins="1"/>
     <metadata>
@@ -40,17 +43,16 @@
       <meta name="subtype">output</meta>
     </metadata>
   </pb_type>
-  -->
   <interconnect>
-    <!--
     <direct name="I" input="inpad.inpad" output="IOB33M.I"/>
     <direct name="O" input="IOB33M.O" output="outpad.outpad"/>
-      <direct name="I" input="INBUF.OUT" output="IOB33M.I"/>
-      <direct name="T" input="IOB33M.T" output="OUTBUF.TRI"/>
-      <direct name="O" input="IOB33M.O" output="OUTBUF.IN"/>
-      <direct name="to_outpad" input="OUTBUT.OUT" output="outpad.outpad"/>
-      <direct name="to_inpad" input="inpad.inpad" output="INBUF.PAD"/>
-    -->
+<!--
+    <direct name="I" input="INBUF_VPR.OUT" output="IOB33M.I"/>
+    <direct name="T" input="IOB33M.T" output="OUTBUF_VPR.TRI"/>
+    <direct name="O" input="IOB33M.O" output="OUTBUF_VPR.IN"/>
+    <direct name="to_outpad" input="OUTBUF_VPR.OUT" output="outpad.outpad"/>
+    <direct name="to_inpad" input="inpad.inpad" output="INBUF_VPR.PAD"/>
+-->
   </interconnect>
   <!-- TODO -->
 </pb_type>
diff --git a/xc7/primitives/ologice3/ologice3.pb_type.xml b/xc7/primitives/ologice3/ologice3.pb_type.xml
@@ -32,15 +32,8 @@
   <output name="TQ" num_pins="1"/>
   <input name="SHIFTIN1" num_pins="1"/>
   <input name="SHIFTIN2" num_pins="1"/>
-  <pb_type name="outpad" blif_model=".output" num_pb="1">
-    <input name="outpad" num_pins="1"/>
-    <metadata>
-      <meta name="type">bel</meta>
-      <meta name="subtype">output</meta>
-    </metadata>
-  </pb_type>
   <interconnect>
-    <direct name="D1_OQ" input="OLOGICE3.D1" output="outpad.outpad"/>
+    <direct name="D1_OQ" input="OLOGICE3.D1" output="OLOGICE3.OQ"/>
   </interconnect>
   <!-- TODO -->
 </pb_type>
diff --git a/xc7/techmap/cells_map.v b/xc7/techmap/cells_map.v
@@ -1841,3 +1841,33 @@ module SRL16E (
 
 endmodule
 
+// ============================================================================
+// IO
+
+module IBUF (
+  input I,
+  output O
+);
+
+   INBUF_VPR _TECHMAP_REPLACE_ (
+     .PAD(I),
+     .INTERMDISABLE(1),
+     .IBUFDISABLE(1),
+     .DIFFI_IN(1),
+     .OUT(O)
+   );
+
+endmodule
+
+module OBUF (
+  input I,
+  output O
+);
+
+   OUTBUF_VPR _TECHMAP_REPLACE_ (
+     .TRI(1),
+     .IN(I),
+     .OUT(O)
+   );
+
+endmodule
diff --git a/xc7/techmap/cells_sim.v b/xc7/techmap/cells_sim.v
@@ -625,3 +625,19 @@ module SRLC16E (
   endgenerate
 endmodule
 
+// ============================================================================
+// IO
+
+module INBUF_VPR (
+	input PAD,
+	output OUT
+);
+	assign OUT = PAD;
+endmodule
+
+module OUTBUF_VPR (
+	input IN,
+	output OUT
+);
+	assign OUT = IN;
+endmodule
diff --git a/xc7/tests/buttons/buttons_basys3.v b/xc7/tests/buttons/buttons_basys3.v
@@ -2,5 +2,13 @@ module top(
 	input in,
 	output out
 );
-  assign out = in;
+
+   assign out = in;
+   /*
+   wire        in_buf;
+   wire        out_buf;
+   IBUF inbuf(.I(in), .O(in_buf));
+   OBUF outbuf(.I(out_buf), .O(out));
+   assign out_buf = in_buf;
+   */
 endmodule