Add stubs for RAMs.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
f4pga · Nov 19, 2018 · e5a282f · e5a282f
1 parent daf7a22
commit e5a282f
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Showing 7 changed files with 108 additions and 8 deletions.
diff --git a/artix7/primitives/slicem/CMakeLists.txt b/artix7/primitives/slicem/CMakeLists.txt
@@ -1,4 +1,16 @@
 add_subdirectory(Ndram)
 
+add_file_target(FILE dram_2_output_stub.sim.v SCANNER_TYPE verilog)
+add_file_target(FILE dram_4_output_stub.sim.v SCANNER_TYPE verilog)
+
+v2x(
+    NAME dram_2_output_stub
+    SRCS dram_2_output_stub.sim.v
+    )
+v2x(
+    NAME dram_4_output_stub
+    SRCS dram_4_output_stub.sim.v
+    )
+
 add_file_target(FILE slicem.model.xml SCANNER_TYPE xml)
 add_file_target(FILE slicem.pb_type.xml SCANNER_TYPE xml)
diff --git a/artix7/primitives/slicem/Ndram/d_dram.pb_type.xml b/artix7/primitives/slicem/Ndram/d_dram.pb_type.xml
@@ -8,6 +8,7 @@
   <input  name="WE"  num_pins="1" />
 
   <output name="SO6"  num_pins="1" />
+  <output name="SO6_32"  num_pins="1" />
   <output name="O6"  num_pins="1" />
   <output name="O5"  num_pins="1" />
 
@@ -37,6 +38,7 @@
 
      <direct name="O6" input="BLK_MM-SPRAM32.O6" output="BLK_IG-D_DRAM.O6" />
      <direct name="O5" input="BLK_MM-SPRAM32.O5" output="BLK_IG-D_DRAM.O5" />
+     <direct name="SO6_32" input="BLK_MM-SPRAM32.O6" output="BLK_IG-D_DRAM.SO6_32" />
    </interconnect>
  </mode>
 

diff --git a/artix7/primitives/slicem/Ndram/ntemplate.N_dram.pb_type.xml b/artix7/primitives/slicem/Ndram/ntemplate.N_dram.pb_type.xml
@@ -10,6 +10,9 @@
   <input  name="WE"  num_pins="1" />
 
   <output name="DO6"  num_pins="1" />
+  <output name="DO6_32"  num_pins="1" />
+  <output name="SO6"  num_pins="1" />
+  <output name="SO6_32"  num_pins="1" />
   <output name="O6"  num_pins="1" />
   <output name="O5"  num_pins="1" />
 
@@ -78,6 +81,7 @@
       <direct name="WE" input="BLK_IG-{N}_DRAM.WE" output="BLK_MM-SPRAM64.WE" />
 
       <direct name="O6" input="BLK_MM-SPRAM64.O6" output="BLK_IG-{N}_DRAM.O6" />
+      <direct name="SO6" input="BLK_MM-SPRAM64.O6" output="BLK_IG-{N}_DRAM.SO6" />
     </interconnect>
   </mode>
   <mode name="64_DUAL_PORT">
@@ -106,6 +110,7 @@
       <direct name="WE" input="BLK_IG-{N}_DRAM.WE" output="BLK_MM-DPRAM32.WE" />
 
       <direct name="O6" input="BLK_MM-DPRAM32.O6" output="BLK_IG-{N}_DRAM.O6" />
+      <direct name="DO6" input="BLK_MM-DPRAM32.O6" output="BLK_IG-{N}_DRAM.DO6_32" />
       <direct name="O5" input="BLK_MM-DPRAM32.O5" output="BLK_IG-{N}_DRAM.O5" />
     </interconnect>
   </mode>
@@ -124,6 +129,7 @@
       <direct name="WE" input="BLK_IG-{N}_DRAM.WE" output="BLK_MM-SPRAM32.WE" />
 
       <direct name="O6" input="BLK_MM-SPRAM32.O6" output="BLK_IG-{N}_DRAM.O6" />
+      <direct name="SO6" input="BLK_MM-SPRAM32.O6" output="BLK_IG-{N}_DRAM.SO6_32" />
       <direct name="O5" input="BLK_MM-SPRAM32.O5" output="BLK_IG-{N}_DRAM.O5" />
     </interconnect>
   </mode>

diff --git a/artix7/primitives/slicem/slicem.model.xml b/artix7/primitives/slicem/slicem.model.xml
@@ -8,4 +8,6 @@
  <xi:include href="Ndram/b_dram.model.xml"                 xpointer="xpointer(models/child::node())" />
  <xi:include href="Ndram/c_dram.model.xml"                 xpointer="xpointer(models/child::node())" />
  <xi:include href="Ndram/d_dram.model.xml"                 xpointer="xpointer(models/child::node())" />
+ <xi:include href="dram_2_output_stub.model.xml"           xpointer="xpointer(models/child::node())" />
+ <xi:include href="dram_4_output_stub.model.xml"           xpointer="xpointer(models/child::node())" />
 </models>
diff --git a/artix7/primitives/slicem/slicem.pb_type.xml b/artix7/primitives/slicem/slicem.pb_type.xml
@@ -191,6 +191,14 @@
       <xi:include href="../common_slice/muxes/f7amux/f7amux.pb_type.xml"/>
       <xi:include href="../common_slice/muxes/f7bmux/f7bmux.pb_type.xml"/>
       <xi:include href="../common_slice/muxes/f8mux/f8mux.pb_type.xml"/>
+      <pb_type name="BEL_BB-DRAM_4_OUTPUT_STUB" blif_model=".subckt DRAM_4_OUTPUT_STUB" num_pb="2">
+        <xi:include href="dram_4_output_stub.pb_type.xml"
+                    xpointer="xpointer(pb_type/child::node())" />
+      </pb_type>
+      <pb_type name="BEL_BB-DRAM_2_OUTPUT_STUB" blif_model=".subckt DRAM_2_OUTPUT_STUB" num_pb="4">
+        <xi:include href="dram_2_output_stub.pb_type.xml"
+                    xpointer="xpointer(pb_type/child::node())" />
+      </pb_type>
 
       <pb_type name="BLK_MM-WE_MUX" num_pb="1">
         <input name="CE" num_pins="1"/>
@@ -325,16 +333,73 @@
         <direct name="WE4" input="BLK_MM-WE_MUX.WE_OUT"  output="BLK_IG-D_DRAM.WE"/>
 
         <!-- Outputs -->
-        <direct name="DO6" input="BLK_IG-D_DRAM.O6"   output="BLK_IG-SLICEM_MODES.DO6" />
+
+        <direct name="SPO_0" input="BLK_IG-D_DRAM.SO6_32" output="BEL_BB-DRAM_2_OUTPUT_STUB[0].SPO">
+          <pack_pattern in_port="BLK_IG-D_DRAM.SO6_32" name="DRAM_DP_32" out_port="BEL_BB-DRAM_2_OUTPUT_STUB[0].SPO" />
+        </direct>
+        <direct name="DPO_0" input="BLK_IG-C_DRAM.DO6_32" output="BEL_BB-DRAM_2_OUTPUT_STUB[0].DPO">
+          <pack_pattern in_port="BLK_IG-C_DRAM.DO6_32" name="DRAM_DP_32" out_port="BEL_BB-DRAM_2_OUTPUT_STUB[0].DPO" />
+        </direct>
+        <direct name="SPO_1" input="BLK_IG-B_DRAM.SO6_32" output="BEL_BB-DRAM_2_OUTPUT_STUB[1].SPO">
+          <pack_pattern in_port="BLK_IG-B_DRAM.SO6_32" name="DRAM_DP_32" out_port="BEL_BB-DRAM_2_OUTPUT_STUB[1].SPO" />
+        </direct>
+        <direct name="DPO_1" input="BLK_IG-A_DRAM.DO6_32" output="BEL_BB-DRAM_2_OUTPUT_STUB[1].DPO">
+          <pack_pattern in_port="BLK_IG-A_DRAM.DO6_32" name="DRAM_DP_32" out_port="BEL_BB-DRAM_2_OUTPUT_STUB[1].DPO" />
+        </direct>
+
+        <direct name="SPO_2" input="BLK_IG-D_DRAM.SO6" output="BEL_BB-DRAM_2_OUTPUT_STUB[2].SPO">
+          <pack_pattern in_port="BLK_IG-D_DRAM.SO6" name="DRAM_DP" out_port="BEL_BB-DRAM_2_OUTPUT_STUB[2].SPO" />
+        </direct>
+        <direct name="DPO_2" input="BLK_IG-C_DRAM.DO6" output="BEL_BB-DRAM_2_OUTPUT_STUB[2].DPO">
+          <pack_pattern in_port="BLK_IG-C_DRAM.DO6" name="DRAM_DP" out_port="BEL_BB-DRAM_2_OUTPUT_STUB[2].DPO" />
+        </direct>
+        <direct name="SPO_3" input="BLK_IG-B_DRAM.SO6" output="BEL_BB-DRAM_2_OUTPUT_STUB[3].SPO">
+          <pack_pattern in_port="BLK_IG-B_DRAM.SO6" name="DRAM_DP" out_port="BEL_BB-DRAM_2_OUTPUT_STUB[3].SPO" />
+        </direct>
+        <direct name="DPO_3" input="BLK_IG-A_DRAM.DO6" output="BEL_BB-DRAM_2_OUTPUT_STUB[3].DPO">
+          <pack_pattern in_port="BLK_IG-A_DRAM.DO6" name="DRAM_DP" out_port="BEL_BB-DRAM_2_OUTPUT_STUB[3].DPO" />
+        </direct>
+
+        <direct name="DOD32" input="BLK_IG-D_DRAM.SO6_32" output="BEL_BB-DRAM_4_OUTPUT_STUB[0].DOD">
+          <pack_pattern  in_port="BLK_IG-D_DRAM.SO6_32" name="DRAM_QP_32" out_port="BEL_BB-DRAM_4_OUTPUT_STUB[0].DOD" />
+        </direct>
+        <direct name="DOC32" input="BLK_IG-C_DRAM.DO6_32" output="BEL_BB-DRAM_4_OUTPUT_STUB[0].DOC">
+          <pack_pattern  in_port="BLK_IG-C_DRAM.DO6_32" name="DRAM_QP_32" out_port="BEL_BB-DRAM_4_OUTPUT_STUB[0].DOC" />
+        </direct>
+        <direct name="DOB32" input="BLK_IG-B_DRAM.DO6_32" output="BEL_BB-DRAM_4_OUTPUT_STUB[0].DOB">
+          <pack_pattern  in_port="BLK_IG-B_DRAM.DO6_32" name="DRAM_QP_32" out_port="BEL_BB-DRAM_4_OUTPUT_STUB[0].DOB" />
+        </direct>
+        <direct name="DOA32" input="BLK_IG-A_DRAM.DO6_32" output="BEL_BB-DRAM_4_OUTPUT_STUB[0].DOA">
+          <pack_pattern  in_port="BLK_IG-A_DRAM.DO6_32" name="DRAM_QP_32" out_port="BEL_BB-DRAM_4_OUTPUT_STUB[0].DOA" />
+        </direct>
+
+        <direct name="DOD" input="BLK_IG-D_DRAM.SO6" output="BEL_BB-DRAM_4_OUTPUT_STUB[1].DOD">
+          <pack_pattern  in_port="BLK_IG-D_DRAM.SO6" name="DRAM_QP" out_port="BEL_BB-DRAM_4_OUTPUT_STUB[1].DOD" />
+        </direct>
+        <direct name="DOC" input="BLK_IG-C_DRAM.DO6" output="BEL_BB-DRAM_4_OUTPUT_STUB[1].DOC">
+          <pack_pattern  in_port="BLK_IG-C_DRAM.DO6" name="DRAM_QP" out_port="BEL_BB-DRAM_4_OUTPUT_STUB[1].DOC" />
+        </direct>
+        <direct name="DOB" input="BLK_IG-B_DRAM.DO6" output="BEL_BB-DRAM_4_OUTPUT_STUB[1].DOB">
+          <pack_pattern  in_port="BLK_IG-B_DRAM.DO6" name="DRAM_QP" out_port="BEL_BB-DRAM_4_OUTPUT_STUB[1].DOB" />
+        </direct>
+        <direct name="DOA" input="BLK_IG-A_DRAM.DO6" output="BEL_BB-DRAM_4_OUTPUT_STUB[1].DOA">
+          <pack_pattern  in_port="BLK_IG-A_DRAM.DO6" name="DRAM_QP" out_port="BEL_BB-DRAM_4_OUTPUT_STUB[1].DOA" />
+        </direct>
+
+        <mux    name="DO6" input="BLK_IG-D_DRAM.O6 BEL_BB-DRAM_2_OUTPUT_STUB[0].SPO_OUT BEL_BB-DRAM_2_OUTPUT_STUB[2].SPO_OUT BEL_BB-DRAM_4_OUTPUT_STUB[0].DOD_OUT BEL_BB-DRAM_4_OUTPUT_STUB[1].DOD_OUT"
+                output="BLK_IG-SLICEM_MODES.DO6" />
         <direct name="DO5" input="BLK_IG-D_DRAM.O5"   output="BLK_IG-SLICEM_MODES.DO5" />
 
-        <direct name="CO6" input="BLK_IG-C_DRAM.O6"   output="BLK_IG-SLICEM_MODES.CO6" />
+        <mux    name="CO6" input="BLK_IG-C_DRAM.O6 BEL_BB-DRAM_2_OUTPUT_STUB[0].DPO_OUT BEL_BB-DRAM_2_OUTPUT_STUB[2].DPO_OUT BEL_BB-DRAM_4_OUTPUT_STUB[0].DOC_OUT BEL_BB-DRAM_4_OUTPUT_STUB[1].DOC_OUT"
+                output="BLK_IG-SLICEM_MODES.CO6" />
         <direct name="CO5" input="BLK_IG-C_DRAM.O5"   output="BLK_IG-SLICEM_MODES.CO5" />
 
-        <direct name="BO6" input="BLK_IG-B_DRAM.O6"   output="BLK_IG-SLICEM_MODES.BO6" />
+        <mux    name="BO6" input="BLK_IG-B_DRAM.O6 BEL_BB-DRAM_2_OUTPUT_STUB[1].SPO_OUT BEL_BB-DRAM_2_OUTPUT_STUB[3].SPO_OUT BEL_BB-DRAM_4_OUTPUT_STUB[0].DOB_OUT BEL_BB-DRAM_4_OUTPUT_STUB[1].DOB_OUT"
+                output="BLK_IG-SLICEM_MODES.BO6" />
         <direct name="BO5" input="BLK_IG-B_DRAM.O5"   output="BLK_IG-SLICEM_MODES.BO5" />
 
-        <direct name="AO6" input="BLK_IG-A_DRAM.O6"   output="BLK_IG-SLICEM_MODES.AO6" />
+        <mux    name="AO6" input="BLK_IG-A_DRAM.O6 BEL_BB-DRAM_2_OUTPUT_STUB[1].DPO_OUT BEL_BB-DRAM_2_OUTPUT_STUB[3].DPO_OUT BEL_BB-DRAM_4_OUTPUT_STUB[0].DOA_OUT BEL_BB-DRAM_4_OUTPUT_STUB[1].DOA_OUT"
+                output="BLK_IG-SLICEM_MODES.AO6" />
         <direct name="AO5" input="BLK_IG-A_DRAM.O5"   output="BLK_IG-SLICEM_MODES.AO5" />
 
         <!-- F7AMUX inputs -->
@@ -381,6 +446,7 @@
       <xi:include href="Ndram/d_dram128.pb_type.xml"/>
       <xi:include href="../common_slice/muxes/f7amux/f7amux.pb_type.xml"/>
       <xi:include href="../common_slice/muxes/f7bmux/f7bmux.pb_type.xml"/>
+      <xi:include href="dram_2_output_stub.pb_type.xml"/>
 
       <pb_type name="BLK_MM-WE_MUX" num_pb="1">
         <input name="CE" num_pins="1"/>
@@ -506,8 +572,15 @@
         </direct>
         <direct name="F7BMUX_S"  input="BLK_IG-SLICEM_MODES.CX" output="BEL_MX-F7BMUX.S" />
 
-        <direct name="F7AMUX_O"   input="BEL_MX-F7AMUX.O" output="BLK_IG-SLICEM_MODES.F7AMUX_O" />
-        <direct name="F7BMUX_O"   input="BEL_MX-F7BMUX.O" output="BLK_IG-SLICEM_MODES.F7BMUX_O" />
+        <direct name="DPO" input="BEL_MX-F7AMUX.O" output="BEL_BB-DRAM_2_OUTPUT_STUB.DPO">
+          <pack_pattern in_port="BEL_MX-F7AMUX.O" name="DRAM128_DP" out_port="BEL_BB-DRAM_2_OUTPUT_STUB.DPO" />
+        </direct>
+        <direct name="SPO" input="BEL_MX-F7BMUX.O" output="BEL_BB-DRAM_2_OUTPUT_STUB.SPO">
+          <pack_pattern in_port="BEL_MX-F7BMUX.O" name="DRAM128_DP" out_port="BEL_BB-DRAM_2_OUTPUT_STUB.SPO" />
+        </direct>
+
+        <mux name="F7AMUX_O"   input="BEL_MX-F7AMUX.O BEL_BB-DRAM_2_OUTPUT_STUB.DPO_OUT" output="BLK_IG-SLICEM_MODES.F7AMUX_O" />
+        <mux name="F7BMUX_O"   input="BEL_MX-F7BMUX.O BEL_BB-DRAM_2_OUTPUT_STUB.SPO_OUT" output="BLK_IG-SLICEM_MODES.F7BMUX_O" />
       </interconnect>
       <!-- The DLUT must be in RAM-mode for an of the RAM's to work. -->
       <metadata>

diff --git a/artix7/tests/CMakeLists.txt b/artix7/tests/CMakeLists.txt
@@ -1,5 +1,6 @@
 add_subdirectory(buttons)
 add_subdirectory(counter)
+add_subdirectory(uart_tx)
 add_subdirectory(carry)
 add_subdirectory(simple_ff)
 add_subdirectory(dram)

diff --git a/make/devices.cmake b/make/devices.cmake
@@ -808,6 +808,7 @@ function(ADD_FPGA_TARGET)
   # Generate BLIF as start of vpr input.
   #
   set(OUT_EBLIF ${OUT_LOCAL}/${TOP}.eblif)
+  set(OUT_SYNTH_V ${OUT_LOCAL}/${TOP}_synth.v)
 
   set(SOURCE_FILES_DEPS "")
   set(SOURCE_FILES "")
@@ -819,11 +820,11 @@ function(ADD_FPGA_TARGET)
   if(NOT ${ADD_FPGA_TARGET_NO_SYNTHESIS})
     set(
       COMPLETE_YOSYS_SCRIPT
-      "${YOSYS_SCRIPT} $<SEMICOLON> write_blif -attr -cname -param ${OUT_EBLIF}"
+      "${YOSYS_SCRIPT} $<SEMICOLON> write_blif -attr -cname -param ${OUT_EBLIF} $<SEMICOLON> write_verilog ${OUT_SYNTH_V}"
     )
 
     add_custom_command(
-      OUTPUT ${OUT_EBLIF}
+      OUTPUT ${OUT_EBLIF} ${OUT_SYNTH_V}
       DEPENDS ${SOURCE_FILES} ${SOURCE_FILES_DEPS}
               ${YOSYS} ${YOSYS_TARGET} ${QUIET_CMD} ${QUIET_CMD_TARGET}
       COMMAND
@@ -833,6 +834,9 @@ function(ADD_FPGA_TARGET)
       WORKING_DIRECTORY ${CMAKE_CURRENT_BINARY_DIR}
       VERBATIM
     )
+    add_file_target(FILE ${OUT_SYNTH_V} GENERATED)
+    add_output_to_fpga_target(${NAME} SYNTH_V
+        ${OUT_LOCAL_REL}/${TOP}_synth.v)
   else()
     add_custom_command(
       OUTPUT ${OUT_EBLIF}