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Refactor CMake system to enable ROI-less xc7 graphs that share arches. #1143
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Previously some xc7 properties were attached to devices, but belonged to the board. This is now fixed. Moving the PINMAP to the board is less obvious, but I think late binding the PINMAP allows for less confusion, and more flexiblity. This does result in some data duplication, but not a lot. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
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Looks like going from A* factor of 1 to 1.2 doesn't consistently work with the ROI-less picosoc. I'll try returning the A* factor to 1.0, and will investigate this week how/why the lookahead is mispredicting. |
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
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Just one comment.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
It looks only a handful of connections are causing a ton of problems, example breakdown:
I'm going to pick one sink rr (1971067) and try to figure out what is going wrong. |
This path should only be used with explicitly BUFH buffers or during clock routing from a BUFG. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
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LGTM, xc7 build is not yet finished though. I guess still for the routing issues of picosoc
Yep, I'm still working on how to get picosoc to route better. |
I have noticed that some clock signals are being routed (IMO) incorrectly when I have run the OSERDES test with the full 50T. In fact, it happens that, instead of following the dedicated clock route, some of the clocks are being routed through logic, traversing several INT tiles before getting to the destination. Another reason to avoid this behavior is that, if we allow clock nets to be routed between INT tiles, it may happen that some clock signals cross two different clock regions without going through any clock buffer. |
This is not the issue
I've fixed this behavior via 82ea6c1 . This prevents the graph from having a path from the general interconnect to the BUFH. This prevents general interconnect signals from using the clock network. |
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
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I had already locally applied 82ea6c1, but the problem is that clock signals coming from BUFHCEs can still be routed through GFANs in the interconnects. Example of route that was produced by VPR:
From GFAN0 then it was spread among several more INT tiles before arriving at destination. |
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
Previously some xc7 properties were attached to devices, but belonged to
the board. This is now fixed.
Moving the PINMAP to the board is less obvious, but I think late binding
the PINMAP allows for less confusion, and more flexiblity. This does
result in some data duplication, but not a lot.