f4pga · tcal-x · Jun 19, 2020 · May 22, 2020 · Jun 9, 2020 · Jun 9, 2020
diff --git a/CMakeLists.txt b/CMakeLists.txt
@@ -290,6 +290,7 @@ add_dependencies(all_xc7_demos
     all_arty-swbut_bin
     all_arty-uart_bin
     all_arty-full_bin
+    all_arty100t-full_bin
     all_basys3_bin
     all_basys3-full_bin
     #all_basys3-bottom_bin
@@ -303,6 +304,7 @@ add_custom_target(all_xc7_diff_fasm)
 if (NOT DEFINED ENV{CI} OR NOT $ENV{CI})
 add_dependencies(all_xc7_diff_fasm
     all_artix7_diff_fasm
+    all_artix7_100t_diff_fasm
     all_zynq7_diff_fasm
     )
 endif()

diff --git a/xc/xc7/archs/CMakeLists.txt b/xc/xc7/archs/CMakeLists.txt
@@ -1,3 +1,4 @@
 add_subdirectory(artix7)
+add_subdirectory(artix7_100t)
 add_subdirectory(artix7_200t)
 add_subdirectory(zynq7)
diff --git a/xc/xc7/archs/artix7_100t/CMakeLists.txt b/xc/xc7/archs/artix7_100t/CMakeLists.txt
@@ -0,0 +1,22 @@
+project_ray_prepare_database(
+  PRJRAY_ARCH artix7
+  PRJRAY_DIR ${PRJXRAY_DIR}
+  PRJRAY_DB_DIR ${PRJXRAY_DB_DIR}
+  PROTOTYPE_PART xc7a100tfgg676-1
+  PARTS xc7a100tfgg676-1 xc7a100tcsg324-1
+)
+
+add_xc_arch_define(
+  ARCH artix7_100t
+  FAMILY xc7
+  PRJRAY_DIR ${PRJXRAY_DIR}
+  PRJRAY_DB_DIR ${PRJXRAY_DB_DIR}
+  PRJRAY_NAME prjxray
+  PRJRAY_ARCH artix7
+  PROTOTYPE_PART xc7a100tfgg676-1
+  YOSYS_SYNTH_SCRIPT ${symbiflow-arch-defs_SOURCE_DIR}/xc/xc7/yosys/synth.tcl
+  YOSYS_CONV_SCRIPT ${symbiflow-arch-defs_SOURCE_DIR}/xc/xc7/yosys/conv.tcl
+)
+
+add_subdirectory(tiles)
+add_subdirectory(devices)
diff --git a/xc/xc7/archs/artix7_100t/devices/CMakeLists.txt b/xc/xc7/archs/artix7_100t/devices/CMakeLists.txt
@@ -0,0 +1,5 @@
+add_xc_device_define(
+  ARCH artix7_100t
+  PART xc7a100tfgg676-1
+  DEVICES xc7a100t
+)
diff --git a/xc/xc7/archs/artix7_100t/devices/xc7a100t-virt/CMakeLists.txt b/xc/xc7/archs/artix7_100t/devices/xc7a100t-virt/CMakeLists.txt
@@ -0,0 +1,31 @@
+add_xc_device_define_type(
+  ARCH artix7_100t
+  DEVICE xc7a100t
+  TILE_TYPES
+    CLBLL_L
+    CLBLL_R
+    CLBLM_L
+    CLBLM_R
+    BRAM_L
+    LIOPAD_M
+    LIOPAD_S
+    LIOPAD_SING
+    RIOPAD_M
+    RIOPAD_S
+    RIOPAD_SING
+    CLK_BUFG_BOT_R
+    CLK_BUFG_TOP_R
+    CMT_TOP_L_UPPER_T
+    CMT_TOP_R_UPPER_T
+    HCLK_IOI3
+  PB_TYPES
+    SLICEL
+    SLICEM
+    BRAM_L
+    IOPAD
+    IOPAD_M
+    IOPAD_S
+    BUFGCTRL
+    PLLE2_ADV
+    HCLK_IOI3
+)
diff --git a/xc/xc7/archs/artix7_100t/tiles/CMakeLists.txt b/xc/xc7/archs/artix7_100t/tiles/CMakeLists.txt
@@ -0,0 +1,33 @@
+add_subdirectory(bram_l)
+add_subdirectory(bram_r)
+add_subdirectory(clbll_l)
+add_subdirectory(clbll_r)
+add_subdirectory(clblm_l)
+add_subdirectory(clblm_r)
+add_subdirectory(slicel)
+add_subdirectory(slicem)
+add_subdirectory(clk_bufg_top_r)
+add_subdirectory(clk_bufg_bot_r)
+add_subdirectory(bufgctrl)
+add_subdirectory(hclk_ioi3)
+
+set(IOPAD_SITES IOB33 IDELAYE2 ILOGICE3 OLOGICE3)
+set(IOPAD_S_SITES IOB33S IDELAYE2 ILOGICE3 OLOGICE3)
+set(IOPAD_M_SITES IOB33M IDELAYE2 ILOGICE3 OLOGICE3)
+
+project_ray_equiv_tile(
+  ARCH artix7_100t
+  TILES RIOPAD_M RIOPAD_S RIOPAD_SING LIOPAD_M LIOPAD_S LIOPAD_SING
+  PB_TYPES IOPAD IOPAD_S IOPAD_M
+  PB_TYPE_SITES IOPAD_SITES IOPAD_S_SITES IOPAD_M_SITES
+  SITE_EQUIV IOB33M=IOB33 IOB33S=IOB33
+  )
+
+set(PLLE2_ADV_SITES PLLE2_ADV)
+
+project_ray_equiv_tile(
+  ARCH artix7_100t
+  TILES CMT_TOP_L_UPPER_T CMT_TOP_R_UPPER_T
+  PB_TYPES PLLE2_ADV
+  PB_TYPE_SITES PLLE2_ADV_SITES
+  )
diff --git a/xc/xc7/archs/artix7_100t/tiles/bram_l/CMakeLists.txt b/xc/xc7/archs/artix7_100t/tiles/bram_l/CMakeLists.txt
@@ -0,0 +1,7 @@
+project_ray_tile(
+  ARCH artix7_100t
+  TILE BRAM_L
+  SITE_TYPES BRAM_L/BRAM_L
+  FUSED_SITES
+  EQUIVALENT_SITES BRAM_L
+  )
diff --git a/xc/xc7/archs/artix7_100t/tiles/bram_r/CMakeLists.txt b/xc/xc7/archs/artix7_100t/tiles/bram_r/CMakeLists.txt
@@ -0,0 +1,7 @@
+project_ray_tile(
+  ARCH artix7_100t
+  TILE BRAM_R
+  SITE_TYPES BRAM_R/BRAM_R
+  FUSED_SITES
+  EQUIVALENT_SITES BRAM_R
+  )
diff --git a/xc/xc7/archs/artix7_100t/tiles/bufgctrl/CMakeLists.txt b/xc/xc7/archs/artix7_100t/tiles/bufgctrl/CMakeLists.txt
@@ -0,0 +1,21 @@
+set(DEPS "")
+append_file_dependency(DEPS ${symbiflow-arch-defs_SOURCE_DIR}/xc/common/primitives/bufgctrl/bufgctrl.pb_type.xml)
+get_file_location(BUFGCTRL_PB_TYPE ${symbiflow-arch-defs_SOURCE_DIR}/xc/common/primitives/bufgctrl/bufgctrl.pb_type.xml)
+
+add_custom_command(
+  OUTPUT bufgctrl.pb_type.xml
+  COMMAND ${CMAKE_COMMAND} -E copy ${BUFGCTRL_PB_TYPE} ${CMAKE_CURRENT_BINARY_DIR}
+  DEPENDS ${DEPS}
+  )
+add_file_target(FILE bufgctrl.pb_type.xml GENERATED)
+
+set(DEPS "")
+append_file_dependency(DEPS ${symbiflow-arch-defs_SOURCE_DIR}/xc/common/primitives/bufgctrl/bufgctrl.model.xml)
+get_file_location(BUFGCTRL_MODEL ${symbiflow-arch-defs_SOURCE_DIR}/xc/common/primitives/bufgctrl/bufgctrl.model.xml)
+
+add_custom_command(
+  OUTPUT bufgctrl.model.xml
+  COMMAND ${CMAKE_COMMAND} -E copy ${BUFGCTRL_MODEL} ${CMAKE_CURRENT_BINARY_DIR}
+  DEPENDS ${DEPS}
+  )
+add_file_target(FILE bufgctrl.model.xml GENERATED)
diff --git a/xc/xc7/archs/artix7_100t/tiles/clbll_l/CMakeLists.txt b/xc/xc7/archs/artix7_100t/tiles/clbll_l/CMakeLists.txt
@@ -0,0 +1,5 @@
+project_ray_tile_capacity(
+  ARCH artix7_100t
+  TILE CLBLL_L
+  SITE_TYPES SLICEL
+  )
diff --git a/xc/xc7/archs/artix7_100t/tiles/clbll_r/CMakeLists.txt b/xc/xc7/archs/artix7_100t/tiles/clbll_r/CMakeLists.txt
@@ -0,0 +1,6 @@
+project_ray_tile_capacity(
+  ARCH artix7_100t
+  TILE CLBLL_R
+  SITE_TYPES SLICEL
+  )
+
diff --git a/xc/xc7/archs/artix7_100t/tiles/clblm_l/CMakeLists.txt b/xc/xc7/archs/artix7_100t/tiles/clblm_l/CMakeLists.txt
@@ -0,0 +1,5 @@
+project_ray_tile_capacity(
+  ARCH artix7_100t
+  TILE CLBLM_L
+  SITE_TYPES SLICEM/SLICEL SLICEL
+  )
diff --git a/xc/xc7/archs/artix7_100t/tiles/clblm_r/CMakeLists.txt b/xc/xc7/archs/artix7_100t/tiles/clblm_r/CMakeLists.txt
@@ -0,0 +1,5 @@
+project_ray_tile_capacity(
+  ARCH artix7_100t
+  TILE CLBLM_R
+  SITE_TYPES SLICEM/SLICEL SLICEL
+  )
diff --git a/xc/xc7/archs/artix7_100t/tiles/clk_bufg_bot_r/CMakeLists.txt b/xc/xc7/archs/artix7_100t/tiles/clk_bufg_bot_r/CMakeLists.txt
@@ -0,0 +1,5 @@
+project_ray_tile_capacity(
+    ARCH artix7_100t
+    TILE CLK_BUFG_BOT_R
+    SITE_TYPES BUFGCTRL
+    )
diff --git a/xc/xc7/archs/artix7_100t/tiles/clk_bufg_top_r/CMakeLists.txt b/xc/xc7/archs/artix7_100t/tiles/clk_bufg_top_r/CMakeLists.txt
@@ -0,0 +1,5 @@
+project_ray_tile_capacity(
+    ARCH artix7_100t
+    TILE CLK_BUFG_TOP_R
+    SITE_TYPES BUFGCTRL
+    )
diff --git a/xc/xc7/archs/artix7_100t/tiles/cmt_top_l_upper_t/CMakeLists.txt b/xc/xc7/archs/artix7_100t/tiles/cmt_top_l_upper_t/CMakeLists.txt
@@ -0,0 +1,7 @@
+project_ray_tile(
+  ARCH artix7_100t
+  TILE CMT_TOP_L_UPPER_T
+  SITE_TYPES PLLE2_ADV/PLLE2_ADV
+  EQUIVALENT_SITES CMT_TOP_L_UPPER_T
+  NO_FASM_PREFIX
+  )
diff --git a/xc/xc7/archs/artix7_100t/tiles/cmt_top_r_upper_t/CMakeLists.txt b/xc/xc7/archs/artix7_100t/tiles/cmt_top_r_upper_t/CMakeLists.txt
@@ -0,0 +1,7 @@
+project_ray_tile(
+  ARCH artix7_100t
+  TILE CMT_TOP_R_UPPER_T
+  SITE_TYPES PLLE2_ADV/PLLE2_ADV
+  EQUIVALENT_SITES CMT_TOP_R_UPPER_T
+  NO_FASM_PREFIX
+  )
diff --git a/xc/xc7/archs/artix7_100t/tiles/hclk_ioi3/CMakeLists.txt b/xc/xc7/archs/artix7_100t/tiles/hclk_ioi3/CMakeLists.txt
@@ -0,0 +1,7 @@
+project_ray_tile(
+  ARCH artix7_100t
+  TILE HCLK_IOI3
+  SITE_TYPES IDELAYCTRL/IDELAYCTRL
+  EQUIVALENT_SITES HCLK_IOI3
+  SITE_COORDS Y
+  )
diff --git a/xc/xc7/archs/artix7_100t/tiles/liob33_sing/CMakeLists.txt b/xc/xc7/archs/artix7_100t/tiles/liob33_sing/CMakeLists.txt
@@ -0,0 +1,5 @@
+project_ray_tile(
+  ARCH artix7_100t
+  TILE LIOB33_SING
+  SITE_TYPES IOB33
+  )
diff --git a/xc/xc7/archs/artix7_100t/tiles/riopad_m/CMakeLists.txt b/xc/xc7/archs/artix7_100t/tiles/riopad_m/CMakeLists.txt
@@ -0,0 +1,7 @@
+project_ray_tile(
+    ARCH artix7_100t
+    TILE RIOPAD_M
+    SITE_TYPES IOB33M/IOB33M ILOGICE3/ILOGICE3 OLOGICE3/OLOGICE3 IDELAYE2/IDELAYE2
+    USE_DATABASE
+    EQUIVALENT_SITES RIOPAD_M
+    )
diff --git a/xc/xc7/archs/artix7_100t/tiles/slicel/CMakeLists.txt b/xc/xc7/archs/artix7_100t/tiles/slicel/CMakeLists.txt
@@ -0,0 +1,7 @@
+project_ray_tile(
+  ARCH artix7_100t
+  TILE SLICEL
+  SITE_AS_TILE
+  SITE_TYPES SLICEL/SLICEL0
+  EQUIVALENT_SITES SLICEL
+  )
diff --git a/xc/xc7/archs/artix7_100t/tiles/slicem/CMakeLists.txt b/xc/xc7/archs/artix7_100t/tiles/slicem/CMakeLists.txt
@@ -0,0 +1,7 @@
+project_ray_tile(
+  ARCH artix7_100t
+  TILE SLICEM
+  SITE_AS_TILE
+  SITE_TYPES SLICEM/SLICEM
+  EQUIVALENT_SITES SLICEM SLICEL
+  )
diff --git a/xc/xc7/boards.cmake b/xc/xc7/boards.cmake
@@ -55,6 +55,15 @@ add_xc_board(
   PART xc7a35tcsg324-1
 )
 
+add_xc_board(
+  BOARD arty100t-full
+  DEVICE xc7a100t
+  PACKAGE test
+  PROG_TOOL ${OPENOCD_TARGET}
+  PROG_CMD "${OPENOCD} -f ${PRJXRAY_DIR}/utils/openocd/board-digilent-basys3.cfg -c \\\"init $<SEMICOLON> pld load 0 \${OUT_BIN} $<SEMICOLON> exit\\\""
+  PART xc7a100tcsg324-1
+)
+
 # TODO: https://github.com/SymbiFlow/symbiflow-arch-defs/issues/344
 add_xc_board(
   BOARD zybo

diff --git a/xc/xc7/tests/buttons/CMakeLists.txt b/xc/xc7/tests/buttons/CMakeLists.txt
@@ -7,6 +7,19 @@ add_fpga_target(
   EXPLICIT_ADD_FILE_TARGET
   )
 
+add_fpga_target(
+  NAME buttons_arty100t
+  BOARD arty100t-full
+  SOURCES buttons_arty.v
+  INPUT_IO_FILE ${COMMON}/arty_swbut.pcf
+  EXPLICIT_ADD_FILE_TARGET
+  )
+
+add_vivado_target(
+  NAME buttons_arty100t_vivado
+  PARENT_NAME buttons_arty100t
+  )
+
 add_file_target(FILE buttons_basys3.v SCANNER_TYPE verilog)
  add_fpga_target(
   NAME buttons_basys3

diff --git a/xc/xc7/tests/counter/CMakeLists.txt b/xc/xc7/tests/counter/CMakeLists.txt
@@ -43,6 +43,21 @@ add_fpga_target(
   EXPLICIT_ADD_FILE_TARGET
 )
 
+add_file_target(FILE counter_arty_bufg.v SCANNER_TYPE verilog)
+add_fpga_target(
+  NAME counter_arty100t
+  BOARD arty100t-full
+  SOURCES counter_arty_bufg.v
+  INPUT_IO_FILE ${COMMON}/arty_swbut.pcf
+  EXPLICIT_ADD_FILE_TARGET
+)
+
+add_vivado_target(
+  NAME counter_arty100t_vivado
+  PARENT_NAME counter_arty100t
+)
+
+
 add_file_target(FILE counter_nexys_video.v SCANNER_TYPE verilog)
 add_fpga_target(
   NAME counter_nexys_video

diff --git a/xc/xc7/tests/counter/counter_arty_bufg.v b/xc/xc7/tests/counter/counter_arty_bufg.v
@@ -0,0 +1,21 @@
+module top (
+    input  wire clk,
+
+    input  wire [7:0] sw,
+    output wire [7:0] led
+);
+
+    localparam BITS = 8;
+    localparam LOG2DELAY = 28;
+
+    reg [BITS+LOG2DELAY-1:0] counter = 0;
+
+    IBUF clk_ibuf(.I(clk),      .O(clk_ibuf));
+    BUFG clk_bufg(.I(clk_ibuf), .O(clk_b));
+
+    always @(posedge clk_b) begin
+        counter <= counter + 1;
+    end
+
+    assign led = counter >> LOG2DELAY;
+endmodule
diff --git a/xc/xc7/tests/ddr/CMakeLists.txt b/xc/xc7/tests/ddr/CMakeLists.txt
@@ -26,3 +26,20 @@ add_vivado_target(
     PARENT_NAME ddr_uart_arty
     XDC arty_clocks.xdc
 )
+
+add_file_target(FILE ddr_uart_100t.v SCANNER_TYPE verilog)
+add_fpga_target(
+  NAME ddr_uart_arty100t
+  BOARD arty100t-full
+  SOURCES
+    ddr_uart_100t.v
+  INPUT_IO_FILE arty.pcf
+  INPUT_XDC_FILE arty.xdc
+  SDC_FILE arty.sdc
+  EXPLICIT_ADD_FILE_TARGET
+)
+
+add_vivado_target(
+  NAME ddr_uart_arty100t_vivado
+  PARENT_NAME ddr_uart_arty100t
+)