Enhance docs with details on new tiles/primitives addition #1950
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umarcor
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Feb 4, 2022
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| The following notes describe in more details the approach required to add new architectures, or enhance an already existing architecture with additional tiles and primitives. | ||
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| Adding a new tiles and primitives |
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I'd suggest "Adding a new tiles and primitives".
umarcor
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Feb 4, 2022
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| This is a VTR-related file which includes a detailed description of the internal logic of the block, as well as its I/O interface. | ||
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| More details can be gathered in the [official VTR documentation](https://docs.verilogtorouting.org/en/latest/arch/reference/). |
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Since this is RST, the syntax for external links is the following:
`official VTR documentation <https://docs.verilogtorouting.org/en/latest/arch/reference/>`__.
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Replaced with an interpshinx ref in a897178.
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
Signed-off-by: Unai Martinez-Corral <umartinezcorral@antmicro.com>
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Signed-off-by: Unai Martinez-Corral <umartinezcorral@antmicro.com>
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Signed-off-by: Alessandro Comodi acomodi@antmicro.com