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Fixed support for PLLE2_BASE #2007
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Vendor tool tests (Vivado) fails on the PLL test with:
This is due to missing correct I'll try to limit the number of output clocks from the PLL in the test design. This should mitigate the problem. |
The |
:/ Looks like there are some conflicting bits in the
|
@mkurc-ant This should have been fixed with f4pga/prjxray#1692, I guess that the prjxray-db conda package needs a bump. |
@acomodi Thanks, I've just done that. I was under impression that we used the most recent one on master. |
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
Hmm, after rebasing which removed the fixed version of prjxray-db package the bit conflict came back again. |
Right, the fact is that now, |
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
For some reason Vivado fails the
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Hey @mkurc-ant, any update on this PR? Do you need help? |
Attempt to solve #1991. Expecting CI to fail for now due toBUFHCE
handling in fasm2bels.This PR fixes the incorrect
PLLE2_BASE
techmap (#1991) plus updates theprjxray-db
so that the most recent version is used.