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Add explicit CEUSEDMUX and SRUSEDMUX support. #576

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merged 2 commits into from Apr 16, 2019

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This has been tested with #575

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
@probot-autolabeler probot-autolabeler bot added lang-verilog Issue uses (or requires) Verilog language. lang-xml Issues uses (or requires) XML language. type-vpr labels Apr 11, 2019
@litghost litghost requested review from mkurc-ant, mithro, elms and kgugala and removed request for mkurc-ant April 11, 2019 16:56
@litghost litghost changed the title Add explicit CEUSEDMUX and SRUSEDMUX support. WIP: Add explicit CEUSEDMUX and SRUSEDMUX support. Apr 11, 2019
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This breaks on non-trival examples, investigating.

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This breaks on non-trival examples, investigating.

Looks like pack patterns were required, but they are nasty. I'll commit the "working" version, and begin thinking about how to make the pack pattern generation suck less.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
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litghost commented Apr 11, 2019

This breaks on non-trival examples, investigating.

Looks like pack patterns were required, but they are nasty. I'll commit the "working" version, and begin thinking about how to make the pack pattern generation suck less.

Using pack patterns solves the packing issue at the cost of the typical VPR packing problem, which is that it no longer packs consumes all the FF's in the slice. Investigating ...

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mithro commented Apr 11, 2019

The pack pattern is a be horrific but otherwise looks okay I think?

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The pack pattern is a be horrific but otherwise looks okay I think?

Amazingly the CI shows green, so that means murax pack/placed/routed! I want to make those pack patterns generated (rather than hand written), and I also need to verify resource usage. It's unclear if VPR can pack all 8 FF's into a SLICE any more with this PR.

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@litghost So with this PR the VPR will be able to use VCC and GND local to CEUSEDMUX and SEUSEDMUX ?

BTW I like the comment "... to make the pack pattern generation suck less" ;)

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@litghost So with this PR the VPR will be able to use VCC and GND local to CEUSEDMUX and SEUSEDMUX ?

Exactly!

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litghost commented Apr 15, 2019

Using #591 I've determined that this PR does not increase sum CLB usage for any of the basys3 test bitstreams. Given that, I'll focus on making the pack pattern output be less terrible. This is probably a good time to migrate to v2x, and hopefully I can compactly express the required pack pattern there without too much trouble using generate statements.

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litghost commented Apr 15, 2019

Using #591 I've determined that this PR does need increase sum CLB usage for any of the basys3 test bitstreams. Given that, I'll focus on making the pack pattern output be less terrible. This is probably a good time to migrate to v2x, and hopefully I can compactly express the required pack pattern there without too much trouble using generate statements.

https://gist.github.com/litghost/5208eb5304e441cd281ec08aa4a0c975 has the data in CSV format. Data points:

  • ff_pack: Results from this PR
  • no_ff_pack: Results from master
  • round_robin_ff_pack: Results from this PR with round robin turned on
Gist
Comparision of master and CE/SR usage PR. GitHub Gist: instantly share code, notes, and snippets.

@litghost litghost changed the title WIP: Add explicit CEUSEDMUX and SRUSEDMUX support. Add explicit CEUSEDMUX and SRUSEDMUX support. Apr 15, 2019
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LGTM.

@litghost litghost merged commit 45be450 into f4pga:master Apr 16, 2019
@litghost litghost deleted the new_sr_ce_on_master branch April 16, 2019 17:12
mkurc-ant referenced this pull request in antmicro/f4pga-arch-defs Oct 6, 2021
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