WIP - utils/vlog: More tests from timing tutorial.

CMakeLists.txt

@@ -110,8 +110,9 @@ add_custom_target(all_xml_lint)
 add_custom_target(all_vpr_test_pbtype)
 
 add_subdirectory(common)
-add_subdirectory(utils)
 add_subdirectory(vpr)
+# FIXME: utils tests depend on targets from vpr
+add_subdirectory(utils)
 add_subdirectory(library)
 # Disable 7-series support in CI because it consumes too much memory.
 if (NOT DEFINED ENV{CI} OR NOT $ENV{CI})

utils/vlog/tests/CMakeLists.txt

@@ -1,21 +1,37 @@
 include(v2x_tests.cmake)
 
+# Functional testing
+add_subdirectory(clocks)
+
+# Simple design tests
+add_subdirectory(simple_pll)
+
+# Tests from the VtR timing tutorial
 add_subdirectory(fig41-full-adder)
 add_subdirectory(fig42-dff)
-add_subdirectory(clocks)
+add_subdirectory(fig43-single_port_ram_mixed)
+#add_subdirectory(fig44-single_port_ram_seq)
+#add_subdirectory(fig45-single_port_ram_seq_comb)
+#add_subdirectory(fig46-multiclock_dual_port_ram)
+
+# FIXME: Should be in the functional testing section but depends on tests from
+# the VtR timing tutorial.
+add_subdirectory(multiple_instance)
+# FIXME: Where should this be?
+add_subdirectory(single_port_rom_mixed)
+
+# Tests which demonstrate DSP style systems
 add_subdirectory(dsp_combinational)
 # FIXME: Output is incorrectly marked as being clocked.
-#add_subdirectory(dsp_in_registered)
+add_subdirectory(dsp_in_registered)
 # FIXME: utils/vlog/tests/dsp_inout_registered/dsp_inout_registered.arch.merged.xml:-1
 # <pb_type> 'dff' timing-annotation/<model> mismatch on port 'd' of model
 # 'dff', port is a sequential input but has neither T_setup nor T_hold
 # specified
-#add_subdirectory(dsp_inout_registered)
-#add_subdirectory(dsp_inout_registered_dualclk)
+add_subdirectory(dsp_inout_registered)
+add_subdirectory(dsp_inout_registered_dualclk)
 # FIXME: Input is incorrectly marked as being clocked.
-#add_subdirectory(dsp_out_registered)
+add_subdirectory(dsp_out_registered)
 # FIXME: Input `m` and output is incorrectly marked as being clocked.
-#add_subdirectory(dsp_partial_registered)
-#add_subdirectory(dsp_modes)
-add_subdirectory(simple_pll)
-add_subdirectory(multiple_instance)
+add_subdirectory(dsp_partial_registered)
+add_subdirectory(dsp_modes)

utils/vlog/tests/dsp_in_registered/golden.model.xml

@@ -1,15 +1,4 @@
 <models xmlns:xi="http://www.w3.org/2001/XInclude">
   <xi:include href="../dsp_combinational/dsp_combinational.model.xml" xpointer="xpointer(models/child::node())"/>
   <xi:include href="../fig42-dff/dff.model.xml" xpointer="xpointer(models/child::node())"/>
-  <model name="dsp_in_registered">
-    <input_ports>
-      <port clock="clk" combinational_sink_ports="out" name="a"/>
-      <port clock="clk" combinational_sink_ports="out" name="b"/>
-      <port is_clock="1" name="clk"/>
-      <port clock="clk" combinational_sink_ports="out" name="m"/>
-    </input_ports>
-    <output_ports>
-      <port name="out"/>
-    </output_ports>
-  </model>
 </models>

utils/vlog/tests/dsp_modes/golden.model.xml

@@ -1,15 +1,4 @@
 <models xmlns:xi="http://www.w3.org/2001/XInclude">
   <xi:include href="../dsp_combinational/dsp_combinational.model.xml" xpointer="xpointer(models/child::node())"/>
   <xi:include href="../dsp_inout_registered/dsp_inout_registered.model.xml" xpointer="xpointer(models/child::node())"/>
-  <model name="dsp_modes">
-    <input_ports>
-      <port clock="clk" combinational_sink_ports="out" name="a"/>
-      <port clock="clk" combinational_sink_ports="out" name="b"/>
-      <port is_clock="1" name="clk"/>
-      <port clock="clk" combinational_sink_ports="out" name="m"/>
-    </input_ports>
-    <output_ports>
-      <port clock="clk" name="out"/>
-    </output_ports>
-  </model>
 </models>

utils/vlog/tests/fig42-dff/dff.sim.v

@@ -1,7 +1,10 @@
 (* blackbox *)
 module dff (d, clk, q);
+	(* SETUP="clk 10e-12" *)
+	(* HOLD="clk 10e-12" *)
 	input wire d;
 	input wire clk;
+	(* CLK_TO_Q="clk 10e-12" *)
 	output reg q;
 
 	always @ ( posedge clk ) begin

utils/vlog/tests/fig43-single_port_ram_mixed/CMakeLists.txt

@@ -0,0 +1,2 @@
+add_file_target(FILE single_port_ram_mixed.sim.v SCANNER_TYPE verilog)
+v2x_test_model(NAME single_port_ram_mixed TOP_MODULE single_port_ram_mixed)

utils/vlog/tests/fig43-single_port_ram_mixed/README.md

@@ -0,0 +1,15 @@
+
+# Figure 43 - Signal Port RAM Mixed
+
+ * [Example shown in 'Figure 43' of the Verilog to Routing Timing Tutorial](). Also shown below;
+
+
+![]()
+
+
+## Features
+
+ - Single address port, captured on clock
+ - Write data port, captured on clock
+ - Read data port, updated after combinational delay (but address is only updated on clock).
+

utils/vlog/tests/fig43-single_port_ram_mixed/golden.model.xml

@@ -0,0 +1,13 @@
+<models xmlns:xi="http://www.w3.org/2001/XInclude">
+  <model name="single_port_ram_mixed">
+    <input_ports>
+      <port clock="clk" combinational_sink_ports="out" name="addr"/>
+      <port is_clock="1" name="clk"/>
+      <port name="data"/>
+      <port name="we"/>
+    </input_ports>
+    <output_ports>
+      <port clock="clk" name="out"/>
+    </output_ports>
+  </model>
+</models>

utils/vlog/tests/fig43-single_port_ram_mixed/golden.pb_type.xml

@@ -0,0 +1,22 @@
+<pb_type name="mem_sp" blif_model=".subckt single_port_ram_mixed" num_pb="1">
+  <input name="addr" num_pins="9"/>
+  <input name="data" num_pins="64"/>
+  <input name="we" num_pins="1"/>
+  <output name="out" num_pins="64"/>
+  <clock name="clk" num_pins="1"/>
+
+  <!-- External input register timing -->
+  <T_setup value="50e-12" port="mem_sp.addr" clock="clk"/>
+  <T_setup value="50e-12" port="mem_sp.data" clock="clk"/>
+  <T_setup value="50e-12" port="mem_sp.we" clock="clk"/>
+
+  <!-- Internal input register timing -->
+  <T_clock_to_Q max="200e-12" port="mem_sp.addr" clock="clk"/>
+  <T_clock_to_Q max="200e-12" port="mem_sp.data" clock="clk"/>
+  <T_clock_to_Q max="200e-12" port="mem_sp.we" clock="clk"/>
+
+  <!-- Internal combinational delay -->
+  <delay_constant max="800e-12" in_port="mem_sp.addr" out_port="mem_sp.out"/>
+  <delay_constant max="800e-12" in_port="mem_sp.data" out_port="mem_sp.out"/>
+  <delay_constant max="800e-12" in_port="mem_sp.we" out_port="mem_sp.out"/>
+</pb_type>

utils/vlog/tests/fig43-single_port_ram_mixed/single_port_ram_mixed.sim.v

@@ -0,0 +1,28 @@
+module single_port_ram_mixed (we, addr, data, clk, out);
+	localparam ADDR_WIDTH = 9;
+	localparam DATA_WIDTH = 64;
+
+	input wire we;
+	input wire [ADDR_WIDTH-1:0] addr;
+	input wire [DATA_WIDTH-1:0] data;
+	input wire clk;
+	output wire [DATA_WIDTH-1:0] out;
+
+	localparam MEM_SIZE = 2 ** ADDR_WIDTH;
+	reg [DATA_WIDTH-1:0] storage[MEM_SIZE-1:0];
+
+	reg q_we;
+	reg q_addr;
+	reg q_data;
+	always @(posedge clk) begin
+		q_we = we;
+		q_addr = addr;
+		q_data = data;
+		if (q_we) begin
+			storage[q_addr] <= q_data;
+		end
+	end
+
+	assign out = storage[q_addr];
+
+endmodule

utils/vlog/tests/fig44-single_port_ram_seq/CMakeLists.txt

@@ -0,0 +1 @@
+v2x_test_model(NAME single_port_ram_seq TOP_MODULE single_port_ram_seq)

utils/vlog/tests/fig44-single_port_ram_seq/README.md

@@ -0,0 +1,15 @@
+# Figure 44 - Sequential Single Port RAM
+
+ * [Example shown in 'Figure 44' of the Verilog to Routing Timing Tutorial](). Also shown below;
+
+
+![]()
+
+
+## Features
+
+ - Single address port, captured on clock
+ - Write data port, captured on clock
+ - Read data port, registered output on clock. (IE Read data available the cycle after address updates (?)).
+    * FIXME: Check this is accurate.
+

utils/vlog/tests/fig44-single_port_ram_seq/golden.model.xml

@@ -0,0 +1,13 @@
+<models xmlns:xi="http://www.w3.org/2001/XInclude">
+  <model name="single_port_ram_seq">
+    <input_ports>
+      <port name="we" clock="clk" combinational_sink_ports="out"/>
+      <port name="addr" clock="clk" combinational_sink_ports="out"/>
+      <port name="data" clock="clk" combinational_sink_ports="out"/>
+      <port name="clk" is_clock="1"/>
+    </input_ports>
+    <output_ports>
+      <port name="out" clock="clk"/>
+    </output_ports>
+  </model>
+</models>

utils/vlog/tests/fig44-single_port_ram_seq/golden.pb_type.xml

@@ -0,0 +1,28 @@
+<pb_type name="mem_sp" blif_model=".subckt single_port_ram_seq" num_pb="1">
+  <input name="addr" num_pins="9"/>
+  <input name="data" num_pins="64"/>
+  <input name="we" num_pins="1"/>
+  <output name="out" num_pins="64"/>
+  <clock name="clk" num_pins="1"/>
+
+  <!-- External input register timing -->
+  <T_setup value="50e-12" port="mem_sp.addr" clock="clk"/>
+  <T_setup value="50e-12" port="mem_sp.data" clock="clk"/>
+  <T_setup value="50e-12" port="mem_sp.we" clock="clk"/>
+
+  <!-- Internal input register timing -->
+  <T_clock_to_Q max="200e-12" port="mem_sp.addr" clock="clk"/>
+  <T_clock_to_Q max="200e-12" port="mem_sp.data" clock="clk"/>
+  <T_clock_to_Q max="200e-12" port="mem_sp.we" clock="clk"/>
+
+  <!-- Internal combinational delay -->
+  <delay_constant max="740e-12" in_port="mem_sp.addr" out_port="mem_sp.out"/>
+  <delay_constant max="740e-12" in_port="mem_sp.data" out_port="mem_sp.out"/>
+  <delay_constant max="740e-12" in_port="mem_sp.we" out_port="mem_sp.out"/>
+
+  <!-- Internal output register timing -->
+  <T_setup value="60e-12" port="mem_sp.out" clock="clk"/>
+
+  <!-- External output register timing -->
+  <T_clock_to_Q max="300e-12" port="mem_sp.out" clock="clk"/>
+</pb_type>

utils/vlog/tests/fig44-single_port_ram_seq/single_port_ram_seq.sim.v

@@ -0,0 +1,67 @@
+`include "../../../../vpr/ff/vpr_ff.sim.v"
+`include "../../../../vpr/mem/vpr_sp_ram.sim.v"
+
+module single_port_ram_seq (we, addr, data, clk, out);
+	localparam ADDR_WIDTH = 9;
+	localparam DATA_WIDTH = 64;
+
+	input wire we;
+	input wire [ADDR_WIDTH-1:0] addr;
+	input wire [DATA_WIDTH-1:0] data;
+	input wire clk;
+	output wire [DATA_WIDTH-1:0] out;
+
+	wire q_we;
+        VPR_FF ff(
+                .D(we),
+                .clk(clk),
+                .Q(q_we),
+        );
+
+	wire [ADDR_WIDTH-1:0] q_addr;
+	generate
+		genvar i;
+		for (i=0; i < ADDR_WIDTH; i=i+1) begin
+			VPR_FF ff(
+				.D(addr[i]),
+				.clk(clk),
+				.Q(q_addr[i]),
+			);
+		end
+	endgenerate
+
+	wire [DATA_WIDTH-1:0] q_data;
+	generate
+		genvar i;
+		for (i=0; i < DATA_WIDTH; i=i+1) begin
+			VPR_FF ff(
+				.D(data[i]),
+				.clk(clk),
+				.Q(q_data[i]),
+			);
+		end
+	endgenerate
+
+	VPR_SP_RAM #(
+		.ADDR_WIDTH(ADDR_WIDTH),
+		.DATA_WIDTH(DATA_WIDTH)
+	) storage (
+		.we(q_we),
+		.addr(q_addr),
+		.data(q_data),
+		.out(out)
+	);
+
+	wire [DATA_WIDTH-1:0] o_out;
+	generate
+		genvar i;
+		for (i=0; i < DATA_WIDTH; i=i+1) begin
+			VPR_FF ff(
+				.D(o_out[i]),
+				.clk(clk),
+				.Q(out[i]),
+			);
+		end
+	endgenerate
+
+endmodule

utils/vlog/tests/fig45-single_port_ram_seq_comb/CMakeLists.txt

@@ -0,0 +1 @@
+v2x_test_model(NAME single_port_ram_seq_comb TOP_MODULE single_port_ram_seq_comb)

utils/vlog/tests/fig45-single_port_ram_seq_comb/README.md

@@ -0,0 +1,14 @@
+# Figure 45 - Combinational Signal Port RAM
+
+ * [Example shown in 'Figure 45' of the Verilog to Routing Timing Tutorial](). Also shown below;
+
+
+![]()
+
+
+## Features
+
+ - Single address port, captured on clock
+ - Write data port, captured on clock
+ - Read data port, registered output on clock. (IE Read data available the cycle after address updates (?)).
+  * FIXME: Check this is true.

utils/vlog/tests/fig45-single_port_ram_seq_comb/golden.model.xml

@@ -0,0 +1,14 @@
+<models xmlns:xi="http://www.w3.org/2001/XInclude">
+  <!-- https://docs.verilogtorouting.org/en/latest/tutorials/arch/timing_modeling/#sequential-block-with-internal-paths-and-combinational-input -->
+  <model name="single_port_ram_seq_comb">
+    <input_ports>
+      <port name="we" combinational_sink_ports="out"/>
+      <port name="addr" clock="clk" combinational_sink_ports="out"/>
+      <port name="data" clock="clk" combinational_sink_ports="out"/>
+      <port name="clk" is_clock="1"/>
+    </input_ports>
+    <output_ports>
+      <port name="out" clock="clk"/>
+    </output_ports>
+  </model>
+</models>

utils/vlog/tests/fig45-single_port_ram_seq_comb/golden.pb_type.xml

@@ -0,0 +1,28 @@
+<pb_type name="mem_sp" blif_model=".subckt single_port_ram_seq_comb" num_pb="1">
+  <input name="addr" num_pins="9"/>
+  <input name="data" num_pins="64"/>
+  <input name="we" num_pins="1"/>
+  <output name="out" num_pins="64"/>
+  <clock name="clk" num_pins="1"/>
+
+  <!-- External input register timing -->
+  <T_setup value="50e-12" port="mem_sp.addr" clock="clk"/>
+  <T_setup value="50e-12" port="mem_sp.data" clock="clk"/>
+
+  <!-- Internal input register timing -->
+  <T_clock_to_Q max="200e-12" port="mem_sp.addr" clock="clk"/>
+  <T_clock_to_Q max="200e-12" port="mem_sp.data" clock="clk"/>
+
+  <!-- External combinational delay -->
+  <delay_constant max="800e-12" in_port="mem_sp.we" out_port="mem_sp.out"/>
+
+  <!-- Internal combinational delay -->
+  <delay_constant max="740e-12" in_port="mem_sp.addr" out_port="mem_sp.out"/>
+  <delay_constant max="740e-12" in_port="mem_sp.data" out_port="mem_sp.out"/>
+
+  <!-- Internal output register timing -->
+  <T_setup value="60e-12" port="mem_sp.out" clock="clk"/>
+
+  <!-- External output register timing -->
+  <T_clock_to_Q max="300e-12" port="mem_sp.out" clock="clk"/>
+</pb_type>