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checks.cfg
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checks.cfg
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# NERV -- Naive Educational RISC-V Processor
#
# Copyright (C) 2020 Claire Xenia Wolf <claire@symbioticeda.com>
#
# Permission to use, copy, modify, and/or distribute this software for any
# purpose with or without fee is hereby granted, provided that the above
# copyright notice and this permission notice appear in all copies.
#
# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
[options]
isa rv32i
[depth]
insn 10
reg 5 10
pc_fwd 5 10
pc_bwd 5 10
unique 1 5 10
causal 5 10
cover 1 10
[sort]
reg_ch0
[defines]
`define NERV_RVFI
`define RISCV_FORMAL_ALIGNED_MEM
[defines liveness]
`define NERV_FAIRNESS
[script-sources]
read_verilog -sv @basedir@/cores/@core@/wrapper.sv
read_verilog @basedir@/cores/@core@/@core@.sv
[cover]
always @* if (!reset) cover (channel[0].cnt_insns == 2);