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AMBA AXI4-Lite

Implements the register block using an AMBA AXI4-Lite CPU interface.

The AXI4-Lite CPU interface comes in two i/o port flavors:

SystemVerilog Interface
  • Command line: --cpuif axi4-lite
  • Interface Definition: axi4lite_intf.sv <../../hdl-src/axi4lite_intf.sv>
  • Class: peakrdl_regblock.cpuif.axi4lite.AXI4Lite_Cpuif
Flattened inputs/outputs

Flattens the interface into discrete input and output ports.

  • Command line: --cpuif axi4-lite-flat
  • Class: peakrdl_regblock.cpuif.axi4lite.AXI4Lite_Cpuif_flattened

Pipelined Performance

This implementation of the AXI4-Lite interface supports transaction pipelining which can significantly improve performance of back-to-back transfers.

In order to support transaction pipelining, the CPU interface will accept multiple concurrent transactions. The number of outstanding transactions allowed is automatically determined based on the register file pipeline depth (affected by retiming options), and influences the depth of the internal transaction response skid buffer.