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Merge changes from topic "rmm_sme" into integration
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* changes:
  feat(runtime): handle SME exceptions from realms
  feat(runtime): emulate SME specific feature ID register for realms
  feat(lib/arch): add support for NS SME context
  fix(lib/arch): add function to clear SVE P and FFR registers
  feat(runtime): handle SVE hint bit passed in RMI SMCs
  feat(lib/arch): add SVE hint bit support
  feat(lib/arch): add support for simd context
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@soby-mathew
soby-mathew authored and TrustedFirmware Code Review committed Sep 29, 2023
2 parents 30452e9 + 0ff7c87 commit 0ccd7ae
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Showing 20 changed files with 981 additions and 594 deletions.
44 changes: 43 additions & 1 deletion lib/arch/include/arch.h
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Original file line number Diff line number Diff line change
Expand Up @@ -278,6 +278,7 @@
#define ESR_EL2_EC_SMC INPLACE(ESR_EL2_EC, UL(23))
#define ESR_EL2_EC_SYSREG INPLACE(ESR_EL2_EC, UL(24))
#define ESR_EL2_EC_SVE INPLACE(ESR_EL2_EC, UL(25))
#define ESR_EL2_EC_SME INPLACE(ESR_EL2_EC, UL(29))
#define ESR_EL2_EC_INST_ABORT INPLACE(ESR_EL2_EC, UL(32))
#define ESR_EL2_EC_INST_ABORT_SEL INPLACE(ESR_EL2_EC, UL(33))
#define ESR_EL2_EC_DATA_ABORT INPLACE(ESR_EL2_EC, UL(36))
Expand Down Expand Up @@ -468,6 +469,12 @@
#define ID_AA64PFR1_EL1_MTE_SHIFT UL(8)
#define ID_AA64PFR1_EL1_MTE_WIDTH UL(4)

#define ID_AA64PFR1_EL1_SME_SHIFT UL(24)
#define ID_AA64PFR1_EL1_SME_WIDTH UL(4)
#define ID_AA64PFR1_EL1_SME_NOT_IMPLEMENTED UL(0)
#define ID_AA64PFR1_EL1_SME_IMPLEMENTED UL(1)
#define ID_AA64PFR1_EL1_SME2_IMPLEMENTED UL(2)

/* ID_AA64MMFR0_EL1 definitions */
#define ID_AA64MMFR0_EL1_PARANGE_SHIFT U(0)
#define ID_AA64MMFR0_EL1_PARANGE_WIDTH UL(4)
Expand Down Expand Up @@ -536,6 +543,9 @@
/* SVE Feature ID register 0 */
#define ID_AA64ZFR0_EL1 S3_0_C0_C4_4

/* SME Feature ID register 0 */
#define ID_AA64SMFR0_EL1 S3_0_C0_C4_5

/* HPFAR_EL2 definitions */
#define HPFAR_EL2_FIPA_SHIFT 4
#define HPFAR_EL2_FIPA_WIDTH U(40)
Expand Down Expand Up @@ -584,11 +594,35 @@
#define SPSR_EL2_PM_BIT (UL(1) << 32)
#define SPSR_EL2_PPEND_BIT (UL(1) << 33)

/* Floating point control and status register */
#define FPCR S3_3_C4_C4_0
#define FPSR S3_3_C4_C4_1

/* SVE Control Register */
#define ZCR_EL2 S3_4_C1_C2_0
#define ZCR_EL2_LEN_SHIFT UL(0)
#define ZCR_EL2_LEN_WIDTH UL(4)

#define ZCR_EL12 S3_5_C1_C2_0

/* SME Control Register */
#define SMCR_EL2 S3_4_C1_C2_6
#define SMCR_EL2_LEN_SHIFT UL(0)
#define SMCR_EL2_LEN_WIDTH UL(4)
/*
* SMCR_EL2_RAZ_LEN is defined to find the architecturally permitted SVL. This
* is a combination of RAZ and LEN bit fields.
*/
#define SMCR_EL2_RAZ_LEN_SHIFT UL(0)
#define SMCR_EL2_RAZ_LEN_WIDTH UL(9)
#define SMCR_EL2_EZT0_BIT (UL(1) << 30)
#define SMCR_EL2_FA64_BIT (UL(1) << 31)

/* Streaming Vector Control register */
#define SVCR S3_3_C4_C2_2
#define SVCR_SM_BIT (UL(1) << 0)
#define SVCR_ZA_BIT (UL(1) << 1)

/* VTCR definitions */
#define VTCR_T0SZ_SHIFT 0
#define VTCR_T0SZ_WIDTH U(6)
Expand Down Expand Up @@ -741,9 +775,16 @@
#define CPTR_EL2_VHE_ZEN_TRAP_ALL_00 UL(0x0)
#define CPTR_EL2_VHE_ZEN_NO_TRAP_11 UL(0x3)

/* Trap all AMU, trace, FPU, SVE accesses */
#define CPTR_EL2_VHE_SMEN_SHIFT UL(24)
#define CPTR_EL2_VHE_SMEN_WIDTH UL(2)
#define CPTR_EL2_VHE_SMEN_TRAP_ALL_00 UL(0x0)
#define CPTR_EL2_VHE_SMEN_NO_TRAP_11 UL(0x3)

/* Trap all AMU, trace, FPU, SVE, SME accesses */
#define CPTR_EL2_VHE_INIT ((CPTR_EL2_VHE_ZEN_TRAP_ALL_00 << \
CPTR_EL2_VHE_ZEN_SHIFT) | \
(CPTR_EL2_VHE_SMEN_TRAP_ALL_00 << \
CPTR_EL2_VHE_SMEN_SHIFT) | \
(CPTR_EL2_VHE_FPEN_TRAP_ALL_00 << \
CPTR_EL2_VHE_FPEN_SHIFT) | \
CPTR_EL2_VHE_TTA | \
Expand Down Expand Up @@ -874,6 +915,7 @@
#define ESR_EL2_SYSREG_ID_AA64PFR0_EL1 SYSREG_ESR(3, 0, 0, 4, 0)
#define ESR_EL2_SYSREG_ID_AA64PFR1_EL1 SYSREG_ESR(3, 0, 0, 4, 1)
#define ESR_EL2_SYSREG_ID_AA64ZFR0_EL1 SYSREG_ESR(3, 0, 0, 4, 4)
#define ESR_EL2_SYSREG_ID_AA64SMFR0_EL1 SYSREG_ESR(3, 0, 0, 4, 5)

#define ESR_EL2_SYSREG_ID_AA64DFR0_EL1 SYSREG_ESR(3, 0, 0, 5, 0)
#define ESR_EL2_SYSREG_ID_AA64DFR1_EL1 SYSREG_ESR(3, 0, 0, 5, 1)
Expand Down
12 changes: 12 additions & 0 deletions lib/arch/include/arch_features.h
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Original file line number Diff line number Diff line change
Expand Up @@ -27,6 +27,18 @@ static inline bool is_feat_sve_present(void)
read_id_aa64pfr0_el1()) != 0UL);
}

/*
* Check if SME is enabled
* ID_AA64PFR1_EL1.SME, bits [27:24]:
* 0b0000 SME architectural state and programmers' model are not implemented.
* 0b0001 SME architectural state and programmers' model are implemented.
* 0b0010 SME2 implemented. As 0b0001, plus the SME2 ZT0 register.
*/
static inline bool is_feat_sme_present(void)
{
return (EXTRACT(ID_AA64PFR1_EL1_SME, read_id_aa64pfr1_el1()) != 0UL);
}

/*
* Check if RNDR is available
*/
Expand Down
13 changes: 13 additions & 0 deletions lib/arch/include/arch_helpers.h
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Original file line number Diff line number Diff line change
Expand Up @@ -105,6 +105,12 @@ void inv_dcache_range(uintptr_t addr, size_t size);
#define is_zen_enabled() (EXTRACT(CPTR_EL2_VHE_ZEN, read_cptr_el2()) == \
CPTR_EL2_VHE_ZEN_NO_TRAP_11)

/*******************************************************************************
* SME management
******************************************************************************/
#define is_smen_enabled() (EXTRACT(CPTR_EL2_SMEN, read_cptr_el2()) == \
CPTR_EL2_SMEN_NO_TRAP_11)

/*******************************************************************************
* Misc. accessor prototypes
******************************************************************************/
Expand Down Expand Up @@ -278,6 +284,9 @@ DEFINE_SYSREG_RW_FUNCS(csselr_el1)
DEFINE_SYSREG_RW_FUNCS(sctlr_el12)
DEFINE_SYSREG_RW_FUNCS(cpacr_el12)
DEFINE_RENAME_SYSREG_RW_FUNCS(zcr_el2, ZCR_EL2)
DEFINE_RENAME_SYSREG_RW_FUNCS(zcr_el12, ZCR_EL12)
DEFINE_RENAME_SYSREG_RW_FUNCS(smcr_el2, SMCR_EL2)
DEFINE_RENAME_SYSREG_RW_FUNCS(svcr, SVCR)
DEFINE_SYSREG_RW_FUNCS(ttbr0_el12)
DEFINE_SYSREG_RW_FUNCS(ttbr1_el12)
DEFINE_SYSREG_RW_FUNCS(tcr_el12)
Expand Down Expand Up @@ -315,6 +324,7 @@ DEFINE_SYSREG_READ_FUNC(id_aa64afr1_el1)
DEFINE_SYSREG_READ_FUNC(id_aa64dfr0_el1)
DEFINE_SYSREG_READ_FUNC(id_aa64dfr1_el1)
DEFINE_RENAME_SYSREG_READ_FUNC(id_aa64zfr0_el1, ID_AA64ZFR0_EL1)
DEFINE_RENAME_SYSREG_READ_FUNC(id_aa64smfr0_el1, ID_AA64SMFR0_EL1)
DEFINE_SYSREG_READ_FUNC(id_aa64isar0_el1)
DEFINE_SYSREG_READ_FUNC(id_aa64isar1_el1)
DEFINE_SYSREG_READ_FUNC(id_aa64mmfr0_el1)
Expand Down Expand Up @@ -397,6 +407,9 @@ DEFINE_SYSREG_RW_FUNCS(mpam2_el2)
DEFINE_SYSREG_RW_FUNCS(mpamhcr_el2)
DEFINE_SYSREG_RW_FUNCS(pmscr_el2)

DEFINE_RENAME_SYSREG_RW_FUNCS(fpcr, FPCR)
DEFINE_RENAME_SYSREG_RW_FUNCS(fpsr, FPSR)

/*******************************************************************************
* Timer register accessor prototypes
******************************************************************************/
Expand Down
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