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clk-sun20iw1p1.h
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clk-sun20iw1p1.h
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// SPDX-License-Identifier: BSD-2-Clause
/*
* standby/clk-sun8iw19p1.h
*
* Copyright (c) 2018 Allwinner.
* 2019-05-05 Written by frank (frank@allwinnertech.com).
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#ifndef __CLK_SUN8IW20P1_H__
#define __CLK_SUN8IW20P1_H__
#define CCMU_BASE 0x02001000
#define CPUS_CFG_BASE 0x07000400
#define R_PRCM_BASE (0x07010000)
#define RTC_GENERAL(n) (RTC_BASE + 0x100 + ((n)*4))
#define STANDBY_STATUS_REG RTC_GENERAL(3)
#define STANDBY_START (0x00)
#define SUPER_STANDBY_FLAG (0x10000)
//#define DRAM_CRC_MAGIC (0x76543210)
#define TIMESTAMP_STA_BASE 0x08110000
#define CNT_LOW_REG (TIMESTAMP_STA_BASE + 0x0)
#define CNT_HIGH_REG (TIMESTAMP_STA_BASE + 0x4)
#define SUPER_STANDBY_FLAG_REG (CPUS_CFG_BASE + 0x1d4)
#define SUPER_STANDBY_ENTRY_REG (CPUS_CFG_BASE + 0x1d8)
#define CPUS_CLK_CFG_REG (R_PRCM_BASE + 0x000)
#define APBS1_CFG_REG (R_PRCM_BASE + 0x00c)
#define RISCV_CLK_CFG_REG (CCMU_BASE + 0xD00)
#define PLL_CTRL_REG0 (R_PRCM_BASE + 0x240)
#define PLL_CTRL_REG1 (R_PRCM_BASE + 0x244)
/*RTC REG LIST*/
#define RTC_LOSC_CTRL (RTC_BASE + 0x000)
#define RTC_LOSC_AUTO_SWT (RTC_BASE + 0x004)
#define RTC_INOSC_CLK_PRE (RTC_BASE + 0x008)
//#define RTC_INTOSC_CLK_AUTO_CALI_REG (RTC_BASE + 0x00C)
//#define RTC_YMD (RTC_BASE + 0x010)
#define RTC_DAY (RTC_BASE + 0x010)
#define RTC_HMS (RTC_BASE + 0x014)
//#define RTC_ALM0_COUNTER (RTC_BASE + 0x020)
#define RTC_ALM0_DAY_SET_REG (RTC_BASE + 0x020)
//#define RTC_ALM0_CV (RTC_BASE + 0x024)
#define RTC_ALM0_HMS_SET_REG (RTC_BASE + 0x024)
#define RTC_ALM0_EN (RTC_BASE + 0x028)
#define RTC_ALM0_IRQ_EN (RTC_BASE + 0x02C)
#define RTC_ALM0_IRQ_STA (RTC_BASE + 0x030)
//#define RTC_ALM1_WK_HMS (RTC_BASE + 0x040)
//#define RTC_ALM1_EN (RTC_BASE + 0x044)
//#define RTC_ALM1_IRQ_EN (RTC_BASE + 0x048)
//#define RTC_ALM1_IRQ_STA (RTC_BASE + 0x04C)
#define RTC_ALM_CONFIG (RTC_BASE + 0x050)
#define RTC_LOSC_OUT_GATING (RTC_BASE + 0x060)
//#define RTC_VER_REG (RTC_BASE + 0x070)
#define RTC_GP(n) (RTC_BASE + 0x100 + n*0x4)
#define RTC_GP0 (RTC_BASE + 0x100)
#define RTC_GP1 (RTC_BASE + 0x104)
#define RTC_GP2 (RTC_BASE + 0x108)
#define RTC_GP3 (RTC_BASE + 0x10C)
#define RTC_GP4 (RTC_BASE + 0x110)
#define RTC_GP5 (RTC_BASE + 0x114)
#define RTC_GP6 (RTC_BASE + 0x118)
#define RTC_GP7 (RTC_BASE + 0x11C)
#define RTC_FAST_BOOT_INFO0 (RTC_BASE + 0x120)
#define RTC_FAST_BOOT_INFO1 (RTC_BASE + 0x124)
#define RTC_XO_CTRL (RTC_BASE + 0x160)
#define RTC_CALI_CTRL (RTC_BASE + 0x164)
#define RTC_DEBUG (RTC_BASE + 0x170)
#define RTC_GPL_HOLD_OUT (RTC_BASE + 0x180)
//#define RTC_GPM_HOLD_OUT (RTC_BASE + 0x184)
#define RTC_POW_MOD_SEL (RTC_BASE + 0x188)
#define RTC_VDD_RTC (RTC_BASE + 0x190)
#define RTC_IC_CHARA (RTC_BASE + 0x1F0)
#define RTC_VDD_OFF_GATING (RTC_BASE + 0x1F4)
#define RTC_EFUSE_PWRSWT_REG (RTC_BASE + 0x204)
#define RTC_VER_REG (RTC_BASE + 0x300)
#define RTC_BROM_DEB_REG0 (RTC_BASE + 0x304)
#define RTC_BROM_DEB_REG1 (RTC_BASE + 0x308)
#define RTC_BROM_SPI_CLK_CTRL_REG (RTC_BASE + 0x310)
#define RTC_BROM_SD2_DEB_REG (RTC_BASE + 0x314)
#define RTC_BROM_EMMC_DEB_REG (RTC_BASE + 0x318)
//#define RTC_BROM_NAND_DEB_REG (RTC_BASE + 0x1AC)
#define RTC_BROM_SPI_NOR_DEB_REG (RTC_BASE + 0x31C)
#define RTC_BROM_SPI_NAND_DEB_REG (RTC_BASE + 0x320)
#define RTC_SPI_CLK_GATING_REG (RTC_BASE + 0x310)
/*CCMU REG LIST*/
#define CCMU_PLL_CPUX_C0_CTRL_REG (CCMU_BASE + 0x0000)
#define CCMU_PLL_CPUX_CTRL_REG CCMU_PLL_CPUX_C0_CTRL_REG
#define CCMU_PLL_CPUX_C1_CTRL_REG (CCMU_BASE + 0x0008)
#define CCMU_PLL_DDR0_CTRL_REG (CCMU_BASE + 0x0010)
#define CCMU_PLL_DDR1_CTRL_REG (CCMU_BASE + 0x0018)
#define CCMU_PLL_PERI0_CTRL_REG (CCMU_BASE + 0x0020)
#define CCMU_PLL_PERI1_CTRL_REG (CCMU_BASE + 0x0028)
#define CCMU_PLL_UNI_CTRL_REG (CCMU_BASE + 0x0028) //AW1823 new add
#define CCMU_PLL_GPU0_CTRL_REG (CCMU_BASE + 0x0030)
#define CCMU_PLL_GPU1_CTRL_REG (CCMU_BASE + 0x0038)
#define CCMU_PLL_VIDEO0_CTRL_REG (CCMU_BASE + 0x0040)
#define CCMU_PLL_VIDEO1_CTRL_REG (CCMU_BASE + 0x0048)
#define CCMU_PLL_VIDEO2_CTRL_REG (CCMU_BASE + 0x0050)
#define CCMU_PLL_VE_CTRL_REG (CCMU_BASE + 0x0058)
#define CCMU_PLL_DE_CTRL_REG (CCMU_BASE + 0x0060)
#define CCMU_PLL_ISP_CTRL_REG (CCMU_BASE + 0x0068)
#define CCMU_PLL_HSIC_CTRL_REG (CCMU_BASE + 0x0070)
#define CCMU_PLL_AUDIO_CTRL_REG (CCMU_BASE + 0x0078)
#define CCMU_PLL_AUDIO1_CTRL_REG (CCMU_BASE + 0x0080)
#define CCMU_PLL_NOC_CTRL_REG (CCMU_BASE + 0x0080)
#define CCMU_PLL_BSV_CTRL_REG (CCMU_BASE + 0x0088)
#define CCMU_PLL_USB_CTRL_REG (CCMU_BASE + 0x0090)
#define CCMU_PLL_EDP_CTRL_REG (CCMU_BASE + 0x0098)
#define CCMU_PLL_SATA_CTRL_REG (CCMU_BASE + 0x00A0)
#define CCMU_PLL_ADC_CTRL_REG (CCMU_BASE + 0x00A8)
#define CCMU_PLL_DTMB_CTRL_REG (CCMU_BASE + 0x00B0)
#define CCMU_PLL_24M_CTRL_REG (CCMU_BASE + 0x00B8)
#define CCMU_PLL_EVE_CTRL_REG (CCMU_BASE + 0x00C0)
#define CCMU_PLL_CVE_CTRL_REG (CCMU_BASE + 0x00C8)
#define CCMU_PLL_ISE_CTRL_REG (CCMU_BASE + 0x00D0)
#define CCMU_PLL_CSI_CTRL_REG (CCMU_BASE + 0x00E0)
#define CCMU_PLL_CPUX_C0_PATTERN_REG (CCMU_BASE + 0x0100)
#define CCMU_PLL_CPUX_C1_PATTERN_REG (CCMU_BASE + 0x0108)
#define CCMU_PLL_DDR_PATTERN_CTRL_REG (CCMU_BASE + 0x0110)
#define CCMU_PLL_DDR0_PATTERN0_REG (CCMU_BASE + 0x0110)
#define CCMU_PLL_DDR0_PATTERN1_REG (CCMU_BASE + 0x0114)
#define CCMU_PLL_DDR1_PATTERN0_REG (CCMU_BASE + 0x0118)
#define CCMU_PLL_DDR1_PATTERN1_REG (CCMU_BASE + 0x011C)
#define CCMU_PLL_PERI0_PATTERN_REG (CCMU_BASE + 0x0120)
#define CCMU_PLL_PERI0_PATTERN0_REG (CCMU_BASE + 0x0120)
#define CCMU_PLL_PERI0_PATTERN1_REG (CCMU_BASE + 0x0124)
#define CCMU_PLL_PERI1_PATTERN0_REG (CCMU_BASE + 0x0128)
#define CCMU_PLL_PERI1_PATTERN1_REG (CCMU_BASE + 0x012C)
#define CCMU_PLL_GPU0_PATTERN_REG (CCMU_BASE + 0x0130)
#define CCMU_PLL_GPU0_PATTERN0_REG (CCMU_BASE + 0x0130)
#define CCMU_PLL_GPU0_PATTERN1_REG (CCMU_BASE + 0x0134)
#define CCMU_PLL_GPU1_PATTERN_REG (CCMU_BASE + 0x0138)
#define CCMU_PLL_GPU1_PATTERN0_REG (CCMU_BASE + 0x0138)
#define CCMU_PLL_GPU1_PATTERN1_REG (CCMU_BASE + 0x013C)
#define CCMU_PLL_VIDEO0_PATTERN_REG (CCMU_BASE + 0x0140)
#define CCMU_PLL_VIDEO0_PATTERN0_REG (CCMU_BASE + 0x0140)
#define CCMU_PLL_VIDEO0_PATTERN1_REG (CCMU_BASE + 0x0144)
#define CCMU_PLL_VIDEO1_PATTERN_REG (CCMU_BASE + 0x0148)
#define CCMU_PLL_VIDEO1_PATTERN0_REG (CCMU_BASE + 0x0148)
#define CCMU_PLL_VIDEO1_PATTERN1_REG (CCMU_BASE + 0x014C)
#define CCMU_PLL_VIDEO2_PATTERN_REG (CCMU_BASE + 0x0150)
#define CCMU_PLL_VIDEO2_PATTERN0_REG (CCMU_BASE + 0x0150)
#define CCMU_PLL_VIDEO2_PATTERN1_REG (CCMU_BASE + 0x0154)
#define CCMU_PLL_VE_PATTERN_REG (CCMU_BASE + 0x0158)
#define CCMU_PLL_VE_PATTERN0_REG (CCMU_BASE + 0x0158)
#define CCMU_PLL_VE_PATTERN1_REG (CCMU_BASE + 0x015C)
#define CCMU_PLL_DE_PATTERN_REG (CCMU_BASE + 0x0160)
#define CCMU_PLL_DE_PATTERN0_REG (CCMU_BASE + 0x0160)
#define CCMU_PLL_DE_PATTERN1_REG (CCMU_BASE + 0x0164)
#define CCMU_PLL_ISP_PATTERN_REG (CCMU_BASE + 0x0168)
#define CCMU_PLL_ISP_PATTERN0_REG (CCMU_BASE + 0x0168)
#define CCMU_PLL_ISP_PATTERN1_REG (CCMU_BASE + 0x016C)
#define CCMU_PLL_HSIC_PATTERN_REG (CCMU_BASE + 0x0170)
#define CCMU_PLL_HSIC_PATTERN0_REG (CCMU_BASE + 0x0170)
#define CCMU_PLL_HSIC_PATTERN1_REG (CCMU_BASE + 0x0174)
#define CCMU_PLL_AUDIO_PATTERN_REG (CCMU_BASE + 0x0178)
#define CCMU_PLL_AUDIO_PATTERN0_REG (CCMU_BASE + 0x0178)
#define CCMU_PLL_AUDIO_PATTERN1_REG (CCMU_BASE + 0x017C)
#define CCMU_PLL_AUDIO1_PATTERN_REG (CCMU_BASE + 0x0180)
#define CCMU_PLL_AUDIO1_PATTERN0_REG (CCMU_BASE + 0x0180)
#define CCMU_PLL_AUDIO1_PATTERN1_REG (CCMU_BASE + 0x0184)
//#define CCMU_PLL_MIPI_PATTERN_REG (CCMU_BASE + 0x0180)
//#define CCMU_PLL_MIPI_PATTERN0_REG (CCMU_BASE + 0x0180)
//#define CCMU_PLL_MIPI_PATTERN1_REG (CCMU_BASE + 0x0184)
#define CCMU_PLL_HDMI_PATTERN_REG (CCMU_BASE + 0x0188)
#define CCMU_PLL_HDMI_PATTERN0_REG (CCMU_BASE + 0x0188)
#define CCMU_PLL_HDMI_PATTERN1_REG (CCMU_BASE + 0x018C)
#define CCMU_PLL_USB_PATTERN_REG (CCMU_BASE + 0x0190)
#define CCMU_PLL_USB_PATTERN0_REG (CCMU_BASE + 0x0190)
#define CCMU_PLL_USB_PATTERN1_REG (CCMU_BASE + 0x0194)
#define CCMU_PLL_EDP_PATTERN_REG (CCMU_BASE + 0x0198)
#define CCMU_PLL_EDP_PATTERN0_REG (CCMU_BASE + 0x0198)
#define CCMU_PLL_EDP_PATTERN1_REG (CCMU_BASE + 0x019C)
#define CCMU_PLL_SATA_PATTERN_REG (CCMU_BASE + 0x01A0)
#define CCMU_PLL_SATA_PATTERN0_REG (CCMU_BASE + 0x01A0)
#define CCMU_PLL_SATA_PATTERN1_REG (CCMU_BASE + 0x01A4)
#define CCMU_PLL_ADC_PATTERN_REG (CCMU_BASE + 0x01A8)
#define CCMU_PLL_ADC_PATTERN0_REG (CCMU_BASE + 0x01A8)
#define CCMU_PLL_ADC_PATTERN1_REG (CCMU_BASE + 0x01AC)
#define CCMU_PLL_DTMB_PATTERN_REG (CCMU_BASE + 0x01B0)
#define CCMU_PLL_DTMB_PATTERN0_REG (CCMU_BASE + 0x01B0)
#define CCMU_PLL_DTMB_PATTERN1_REG (CCMU_BASE + 0x01B4)
#define CCMU_PLL_24M_PATTERN_REG (CCMU_BASE + 0x01B8)
#define CCMU_PLL_24M_PATTERN0_REG (CCMU_BASE + 0x01B8)
#define CCMU_PLL_24M_PATTERN1_REG (CCMU_BASE + 0x01BC)
#define CCMU_PLL_EVE_PATTERN_REG (CCMU_BASE + 0x01C0)
#define CCMU_PLL_EVE_PATTERN0_REG (CCMU_BASE + 0x01C0)
#define CCMU_PLL_EVE_PATTERN1_REG (CCMU_BASE + 0x01C4)
#define CCMU_PLL_CVE_PATTERN_REG (CCMU_BASE + 0x01C8)
#define CCMU_PLL_CVE_PATTERN0_REG (CCMU_BASE + 0x01C8)
#define CCMU_PLL_CVE_PATTERN1_REG (CCMU_BASE + 0x01CC)
#define CCMU_PLL_ISE_PATTERN_REG (CCMU_BASE + 0x01D0)
#define CCMU_PLL_ISE_PATTERN0_REG (CCMU_BASE + 0x01D0)
#define CCMU_PLL_ISE_PATTERN1_REG (CCMU_BASE + 0x01D4)
#define CCMU_PLL_CPUX_C0_SSC_LIN_REG (CCMU_BASE + 0x0200)
#define CCMU_PLL_CPUX_C1_SSC_LIN_REG (CCMU_BASE + 0x0208)
#define CCMU_PLL_DDR0_SSC_LIN_REG (CCMU_BASE + 0x0210)
#define CCMU_PLL_DDR1_SSC_LIN_REG (CCMU_BASE + 0x0218)
#define CCMU_PLL_GPU0_SSC_LIN_REG (CCMU_BASE + 0x0230)
#define CCMU_PLL_GPU1_SSC_LIN_REG (CCMU_BASE + 0x0238)
#define CCMU_PLL_CPUX_C0_BIAS_REG (CCMU_BASE + 0x0300)
#define CCMU_PLL_CPUX_BIAS_REG (CCMU_BASE + 0x0300)
#define CCMU_PLL_CPUX_C1_BIAS_REG (CCMU_BASE + 0x0308)
#define CCMU_PLL_DDR0_BIAS_REG (CCMU_BASE + 0x0310)
#define CCMU_PLL_DDR_BIAS_REG (CCMU_BASE + 0x0310)
#define CCMU_PLL_DDR1_BIAS_REG (CCMU_BASE + 0x0318)
#define CCMU_PLL_PERI0_BIAS_REG (CCMU_BASE + 0x0320)
#define CCMU_PLL_PERI1_BIAS_REG (CCMU_BASE + 0x0328)
#define CCMU_PLL_GPU0_BIAS_REG (CCMU_BASE + 0x0330)
#define CCMU_PLL_GPU1_BIAS_REG (CCMU_BASE + 0x0338)
#define CCMU_PLL_VIDEO0_BIAS_REG (CCMU_BASE + 0x0340)
#define CCMU_PLL_VIDEO1_BIAS_REG (CCMU_BASE + 0x0348)
#define CCMU_PLL_VIDEO2_BIAS_REG (CCMU_BASE + 0x0350)
#define CCMU_PLL_VE_BIAS_REG (CCMU_BASE + 0x0358)
#define CCMU_PLL_DE_BIAS_REG (CCMU_BASE + 0x0360)
#define CCMU_PLL_ISP_BIAS_REG (CCMU_BASE + 0x0368)
#define CCMU_PLL_HSIC_BIAS_REG (CCMU_BASE + 0x0370)
#define CCMU_PLL_AUDIO_BIAS_REG (CCMU_BASE + 0x0378)
#define CCMU_PLL_AUDIO1_BIAS_REG (CCMU_BASE + 0x0380)
#define CCMU_PLL_MIPI_BIAS_REG (CCMU_BASE + 0x0380)
#define CCMU_PLL_HDMI_BIAS_REG (CCMU_BASE + 0x0388)
#define CCMU_PLL_PLL_USB_BIAS_REG (CCMU_BASE + 0x0390)
#define CCMU_PLL_EDP_BIAS_REG (CCMU_BASE + 0x0398)
#define CCMU_PLL_SATA_BIAS_REG (CCMU_BASE + 0x03A0)
#define CCMU_PLL_ADC_BIAS_REG (CCMU_BASE + 0x03A8)
#define CCMU_PLL_DTMB_BIAS_REG (CCMU_BASE + 0x03B0)
#define CCMU_PLL_24M_BIAS_REG (CCMU_BASE + 0x03B8)
#define CCMU_PLL_EVE_BIAS_REG (CCMU_BASE + 0x03C0)
#define CCMU_PLL_CVE_BIAS_REG (CCMU_BASE + 0x03C8)
#define CCMU_PLL_ISE_BIAS_REG (CCMU_BASE + 0x03D0)
#define CCMU_PLL_CPUX_C0_TUN_REG (CCMU_BASE + 0x0400)
#define CCMU_PLL_CPUX_TUN_REG CCMU_PLL_CPUX_C0_TUN_REG
#define CCMU_PLL_CPUX_C1_TUN_REG (CCMU_BASE + 0x0408)
#define CCMU_PLL_MIPI_TUN_REG (CCMU_BASE + 0x0480)
#define CCMU_CPUX_C0_AXI_CFG_REG (CCMU_BASE + 0x0500)
#define CCMU_CPUX_AXI_CFG_REG (CCMU_BASE + 0x0500)
#define CCMU_CPUX_GATING_REG (CCMU_BASE + 0x0504)
#define CCMU_CPUX_C1_AXI_CFG_REG (CCMU_BASE + 0x0504)
#define CCMU_PSI_CFG_REG (CCMU_BASE + 0x0510)
//#define CCMU_AHB1_CFG_REG (CCMU_BASE + 0x0514)
//#define CCMU_AHB2_CFG_REG (CCMU_BASE + 0x0518)
#define CCMU_AHB3_CFG_REG (CCMU_BASE + 0x051C)
#define CCMU_APB1_CFG_REG (CCMU_BASE + 0x0520)
#define CCMU_APB2_CFG_REG (CCMU_BASE + 0x0524)
#define CCMU_CCI400_CFG_REG (CCMU_BASE + 0x0530)
#define CCMU_MBUS_CFG_REG (CCMU_BASE + 0x0540)
#define CCMU_NOCBUS_CFG_REG (CCMU_BASE + 0x0550)
#define CCMU_MSILITE_CFG_REG (CCMU_BASE + 0x0554)
#define CCMU_DE_CLK_REG (CCMU_BASE + 0x0600)
#define CCMU_DE_BGR_REG (CCMU_BASE + 0x060C)
#define CCMU_EE_CLK_REG (CCMU_BASE + 0x0610)
#define CCMU_EE_BGR_REG (CCMU_BASE + 0x061C)
#define CCMU_EDMA_CLK_REG (CCMU_BASE + 0x0640)
#define CCMU_DI0_CLK_REG (CCMU_BASE + 0x0620)
#define CCMU_DI_CLK_REG CCMU_DI0_CLK_REG
#define CCMU_DI1_CLK_REG (CCMU_BASE + 0x0624)
#define CCMU_DI_BGR_REG (CCMU_BASE + 0x062C)
#define CCMU_G2D_CLK_REG (CCMU_BASE + 0x0630)
#define CCMU_G2D_BGR_REG (CCMU_BASE + 0x063C)
#define CCMU_EDMA_CLK_REG (CCMU_BASE + 0x0640)
#define CCMU_EDMA_BGR_REG (CCMU_BASE + 0x064C)
#define CCMU_EVE_CLK_REG (CCMU_BASE + 0x0650)
#define CCMU_EVE_BGR_REG (CCMU_BASE + 0x065C)
#define CCMU_CVE_CLK_REG (CCMU_BASE + 0x0660)
#define CCMU_CVE_BGR_REG (CCMU_BASE + 0x066C)
#define CCMU_GPU_CORE_CLK_REG (CCMU_BASE + 0x0670)
#define CCMU_GPU_MEM_CLK_REG (CCMU_BASE + 0x0674)
#define CCMU_GPU_HYD_CLK_REG (CCMU_BASE + 0x0678)
#define CCMU_GPU_CLK_REG CCMU_GPU_CORE_CLK_REG
#define CCMU_GPU_BGR_REG (CCMU_BASE + 0x067C)
#define CCMU_CE_CLK_REG (CCMU_BASE + 0x0680)
#define CCMU_CE_BGR_REG (CCMU_BASE + 0x068C)
#define CCMU_VE_CLK_REG (CCMU_BASE + 0x0690)
#define CCMU_VE_BGR_REG (CCMU_BASE + 0x069C)
#define CCMU_ISE_CLK_REG (CCMU_BASE + 0x06A0)
#define CCMU_ISE_BGR_REG (CCMU_BASE + 0x06AC)
#define CCMU_EMCE_CLK_REG (CCMU_BASE + 0x06B0)
#define CCMU_EMCE_BGR_REG (CCMU_BASE + 0x06BC)
#define CCMU_VP9_CLK_REG (CCMU_BASE + 0x06C0)
#define CCMU_VP9_BGR_REG (CCMU_BASE + 0x06CC)
#define CCMU_EISE_CLK_REG (CCMU_BASE + 0x06D0)
#define CCMU_EISE_BGR_REG (CCMU_BASE + 0x06DC)
#define CCMU_NNA_CLK_REG (CCMU_BASE + 0x06E0) //AI 修改为 NNA
#define CCMU_NNA_BGR_REG (CCMU_BASE + 0x06EC) //AI 修改为 NNA
#define CCMU_DMA_BGR_REG (CCMU_BASE + 0x070C)
#define CCMU_MSGBOX_BGR_REG (CCMU_BASE + 0x071C)
#define CCMU_SPINLOCK_BGR_REG (CCMU_BASE + 0x072C)
#define CCMU_HSTIMER_BGR_REG (CCMU_BASE + 0x073C)
#define CCMU_AVS_CLK_REG (CCMU_BASE + 0x0740)
#define CCMU_AVS_BGR_REG (CCMU_BASE + 0x074C)
#define CCMU_GPIO_BGR_REG (CCMU_BASE + 0x075C)
#define CCMU_ATS_CLK_REG (CCMU_BASE + 0x0760)
#define CCMU_TRACE_CLK_REG (CCMU_BASE + 0x0770)
#define CCMU_DBGSYS_BGR_REG (CCMU_BASE + 0x078C)
#define CCMU_PSI_BGR_REG (CCMU_BASE + 0x079C)
#define CCMU_PWM_BGR_REG (CCMU_BASE + 0x07AC)
#define CCMU_IOMMU_BGR_REG (CCMU_BASE + 0x07BC)
#define CCMU_IDC_BGR_REG (CCMU_BASE + 0x07CC)
#define CCMU_DRAM_CLK_REG (CCMU_BASE + 0x0800)
#define CCMU_MBUS_CLK_GATING_REG (CCMU_BASE + 0x0804)
#define PLL_DDR_AUX_REG (CCMU_BASE + 0x0808)
#define CCMU_DRAM_BGR_REG (CCMU_BASE + 0x080C)
#define CCMU_NAND0_CLK0_REG (CCMU_BASE + 0x0810)
#define CCMU_NAND0_CLK1_REG (CCMU_BASE + 0x0814)
#define CCMU_NAND1_CLK0_REG (CCMU_BASE + 0x0818)
#define CCMU_NAND1_CLK1_REG (CCMU_BASE + 0x081C)
#define CCMU_NAND_BGR_REG (CCMU_BASE + 0x082C)
#define CCMU_SMHC0_CLK_REG (CCMU_BASE + 0x0830)
#define CCMU_SMHC1_CLK_REG (CCMU_BASE + 0x0834)
#define CCMU_SMHC2_CLK_REG (CCMU_BASE + 0x0838)
#define CCMU_SMHC_BGR_REG (CCMU_BASE + 0x084C)
#define CCMU_UART_BGR_REG (CCMU_BASE + 0x090C)
#define CCMU_TWI_BGR_REG (CCMU_BASE + 0x091C)
#define CCMU_CAN_BGR_REG (CCMU_BASE + 0x092C)
#define CCMU_SPI0_CLK_REG (CCMU_BASE + 0x0940)
#define CCMU_SPI1_CLK_REG (CCMU_BASE + 0x0944)
#define CCMU_SPI_BGR_REG (CCMU_BASE + 0x096C)
#define CCMU_GMAC25M_CLK_REG (CCMU_BASE + 0x0970)
#define CCMU_GMAC_BGR_REG (CCMU_BASE + 0x097C)
//#define CCMU_EPHY_CLK_REG (CCMU_BASE + 0x0980)
//#define CCMU_EPHY0_CLK_REG (CCMU_BASE + 0x0980)
//#define CCMU_EPHY1_CLK_REG (CCMU_BASE + 0x0984)
//#define CCMU_EPHY_BGR_REG (CCMU_BASE + 0x098C)
//
//#define CCMU_EMAC_BGR_REG (CCMU_BASE + 0x099C)
//
//#define CCMU_SATA_CLK_REG (CCMU_BASE + 0x09A0)
//#define CCMU_SATA_24M_CLK_REG (CCMU_BASE + 0x09A4)
//#define CCMU_SATA_BGR_REG (CCMU_BASE + 0x09AC)
//
//#define CCMU_TS0_CLK_REG (CCMU_BASE + 0x09B0)
//#define CCMU_TS1_CLK_REG (CCMU_BASE + 0x09B4)
//#define CCMU_TS_BGR_REG (CCMU_BASE + 0x09BC)
#define CCMU_IRTX_CLK_REG (CCMU_BASE + 0x09C0)
#define CCMU_IRTX_BGR_REG (CCMU_BASE + 0x09CC)
//#define CCMU_KEYPAD_CLK_REG (CCMU_BASE + 0x09D0)
//#define CCMU_KEYPAD_BGR_REG (CCMU_BASE + 0x09DC)
#define CCMU_GPADC_BGR_REG (CCMU_BASE + 0x09EC)
#define CCMU_THS_BGR_REG (CCMU_BASE + 0x09FC)
//#define CCMU_DTMB_AXI_CLK_REG (CCMU_BASE + 0x0A00)
//#define CCMU_DTMB_CLK_REG (CCMU_BASE + 0x0A04)
//#define CCMU_DTMB_BGR_REG (CCMU_BASE + 0x0A0C)
#define CCMU_I2S0_CLK_REG (CCMU_BASE+0x0A10)
#define CCMU_I2S1_CLK_REG (CCMU_BASE+0x0A14)
#define CCMU_I2S2_CLK_REG (CCMU_BASE+0x0A18)
#define CCMU_I2S2_ASRC_CLK_REG (CCMU_BASE+0x0A1C)
#define CCMU_I2S_BGR_REG (CCMU_BASE+0x0A20)
#define CCMU_SPDIF_TX_CLK_REG (CCMU_BASE + 0x0A24)
#define CCMU_SPDIF_RX_CLK_REG (CCMU_BASE + 0x0A28)
#define CCMU_SPDIF_BGR_REG (CCMU_BASE + 0x0A2C)
//#define CCMU_DSD_CLK_REG (CCMU_BASE + 0x0A30)
//#define CCMU_DSD_BGR_REG (CCMU_BASE + 0x0A3C)
#define CCMU_DMIC_CLK_REG (CCMU_BASE + 0x0A40)
#define CCMU_DMIC_BGR_REG (CCMU_BASE + 0x0A4C)
#define CCMU_ACodec_DAC_CLK_REG (CCMU_BASE + 0x0A50)
#define CCMU_ACodec_ADC_CLK_REG (CCMU_BASE + 0x0A54)
#define CCMU_ACodec_BGR_REG (CCMU_BASE + 0x0A5C)
//#define CCMU_WLAN_CGR_REG (CCMU_BASE + 0x0A60)
//#define CCMU_AUDIO_HUB_CLK_REG (CCMU_BASE + 0xA60)
//#define CCMU_AUDIO_HUB_BGR_REG (CCMU_BASE + 0xA6C)
#define CCMU_USB0_CLK_REG (CCMU_BASE+0x0A70)
#define CCMU_USB1_CLK_REG (CCMU_BASE+0x0A74)
#define CCMU_USB_BGR_REG (CCMU_BASE+0x0A8C)
#define CCMU_LRADC_BGR_REG (CCMU_BASE + 0x0A9C)
//#define CCMU_MAD_CLK_REG (CCMU_BASE + 0x0AC0)
#define CCMU_MAD_BGR_REG (CCMU_BASE + 0x0ACC)
#define CCMU_LPSD_CLK_REG (CCMU_BASE + 0x0AD0)
#define CCMU_LPSD_BGR_REG (CCMU_BASE + 0x0ADC)
//#define CCMU_PCIE_REF_CLK_REG (CCMU_BASE + 0x0AB0)
//#define CCMU_PCIE_AXI_CLK_REG (CCMU_BASE + 0x0AB4)
//#define CCMU_PCIE_AUX_CLK_REG (CCMU_BASE + 0x0AB8)
//#define CCMU_PCIE_CGR_REG (CCMU_BASE + 0x0ABC)
#define CCMU_DPSS_TOP_BGR_REG (CCMU_BASE + 0x0ABC)
#define CCMU_HDMI0_CLK_REG (CCMU_BASE + 0x0B00)
#define CCMU_HDMI0_SCLK_REG (CCMU_BASE + 0x0B04)
#define CCMU_HDMI1_CLK_REG (CCMU_BASE + 0x0B08)
#define CCMU_HDMI1_SCLK_REG1 (CCMU_BASE + 0x0B0C)
#define CCMU_HDMI_CEC_CLK_REG (CCMU_BASE + 0x0B10)
#define CCMU_HDMI0_CEC_REG (CCMU_BASE + 0x0B10)
#define CCMU_HDMI_BGR_REG (CCMU_BASE + 0x0B1C)
#define CCMU_MIPI_DSI_DPYHY0_HS_CLK_REG (CCMU_BASE + 0x0B20)
#define CCMU_MIPI_DSI_DPHY0_HS_CLK_REG (CCMU_BASE + 0x0B20)
#define CCMU_MIPI_DSI_HOST0_CLK_REG (CCMU_BASE + 0x0B24)
#define CCMU_MIPI_DSI_DPHY1_HS_CLK_REG (CCMU_BASE + 0x0B28)
#define CCMU_MIPI_DSI_HOST1_CLK_REG (CCMU_BASE + 0x0B2C)
#define CCMU_MIPI_DSI_DPHY2_HS_CLK_REG (CCMU_BASE + 0x0B30)
#define CCMU_MIPI_DSI_HOST2_CLK_REG (CCMU_BASE + 0x0B34)
#define CCMU_MIPI_DSI_DPHY3_HS_CLK_REG (CCMU_BASE + 0x0B38)
#define CCMU_MIPI_DSI_HOST3_CLK_REG (CCMU_BASE + 0x0B3C)
#define CCMU_MIPI_DSC_CLK_REG (CCMU_BASE + 0x0B40)
#define CCMU_MIPI_BGR_REG (CCMU_BASE + 0x0B4C)
#define CCMU_DSI_BGR_REG (CCMU_BASE + 0x0B4C)
#define CCMU_MIPI_DSI_BGR_REG (CCMU_BASE + 0x0B4C)
#define CCMU_DISPLAY_IF_TOP_BGR_REG (CCMU_BASE + 0x0B5C)
#define CCMU_TCON_LCD0_CLK_REG (CCMU_BASE + 0x0B60)
#define CCMU_TCON_LCD_BGR_REG (CCMU_BASE + 0x0B7C)
#define CCMU_TCON_TV0_CLK_REG (CCMU_BASE + 0x0B80)
#define CCMU_TCON_TV_BGR_REG (CCMU_BASE + 0x0B9C)
//
//#define CCMU_TVE0_CLK_REG (CCMU_BASE + 0x0BA0)
//#define CCMU_TVE1_CLK_REG (CCMU_BASE + 0x0BA4)
//#define CCMU_TVE_BGR_REG (CCMU_BASE + 0x0BAC)
//#define CCMU_LVDS_BGR_REG (CCMU_BASE + 0x0BB0)
#define CCMU_LVDS_BGR_REG (CCMU_BASE + 0x0BAC)
#define CCMU_TVE0_CLK_REG (CCMU_BASE + 0x0BB0)
#define CCMU_TVE1_CLK_REG (CCMU_BASE + 0x0BB4)
#define CCMU_TVE_BGR_REG (CCMU_BASE + 0x0BBC)
#define CCMU_TVD0_CLK_REG (CCMU_BASE + 0x0BC0)
#define CCMU_TVD1_CLK_REG (CCMU_BASE + 0x0BC4)
#define CCMU_TVD2_CLK_REG (CCMU_BASE + 0x0BC8)
#define CCMU_TVD3_CLK_REG (CCMU_BASE + 0x0BCC)
#define CCMU_TVD4_CLK_REG (CCMU_BASE + 0x0BD0)
#define CCMU_TVD5_CLK_REG (CCMU_BASE + 0x0BD4)
#define CCMU_TVD_BGR_REG (CCMU_BASE + 0x0BDC)
#define CCMU_EDP0_CLK_REG (CCMU_BASE + 0x0BE0)
#define CCMU_EDP1_CLK_REG (CCMU_BASE + 0x0BE4)
#define CCMU_EDP_BGR_REG (CCMU_BASE + 0x0BEC)
#define CCMU_LEDC_CLK_REG (CCMU_BASE + 0x0BF0)
#define CCMU_LEDC_BGR_REG (CCMU_BASE + 0x0BFC)
#define CCMU_CSI0_MISC_CLK_REG (CCMU_BASE + 0x0C00)
#define CCMU_CSI0_TOP_CLK_REG (CCMU_BASE + 0x0C04)
#define CCMU_CSI0_MCLK0_REG (CCMU_BASE + 0x0C08)
#define CCMU_CSI_MISC_CLK_REG (CCMU_BASE + 0x0C00)
#define CCMU_CSI_TOP_CLK_REG (CCMU_BASE + 0x0C04)
#define CCMU_CSI0_MCLK0_REG (CCMU_BASE + 0x0C08)
#define CCMU_CSI0_MCLK1_REG (CCMU_BASE + 0x0C0C)
#define CCMU_CSI0_MCLK2_REG (CCMU_BASE + 0x0C10)
#define CCMU_CSI_BGR_REG (CCMU_BASE + 0x0C1C)
#define CCMU_CSI_ISP_CLK_REG (CCMU_BASE + 0x0C30)
#define CCMU_MIPI_RX_CLK_REG (CCMU_BASE + 0x0C30)
#define CCMU_TPADC_CLK_REG (CCMU_BASE + 0x0C50)
#define CCMU_TPADC_BGR_REG (CCMU_BASE + 0x0C5C)
#define CCMU_TZMA_BGR_REG (CCMU_BASE + 0x0C6C)
#define CCMU_DSP_CLK_REG (CCMU_BASE + 0x0C70)
#define CCMU_DSP_BGR_REG (CCMU_BASE + 0x0C7C)
//#define CCMU_DSP_CFG_BGR_REG (CCMU_BASE + 0x0C8C)
//#define CCMU_DSP_DBG_BGR_REG (CCMU_BASE + 0x0C9C)
#define CCMU_RISCV_CLK_REG (CCMU_BASE + 0x0D00)
#define CCMU_RISCV_GATING_REG (CCMU_BASE + 0x0D04)
#define CCMU_RISCV_CFG_BGR_REG (CCMU_BASE + 0x0D0C)
#define CCMU_RISCV_RST_REG (CCMU_BASE + 0x0F20)
#define CCMU_HDCP_CLK_REG (CCMU_BASE + 0x0C40)
#define CCMU_HDCP_BGR_REG (CCMU_BASE + 0x0C4C)
#define CCMU_SEC_SWITCH_REG (CCMU_BASE + 0x0F00)
#define CCMU_PLL_LOCK_CTRL_REG (CCMU_BASE + 0x0F04)
#define CCMU_FRE_DET_CTRL_REG (CCMU_BASE + 0x0F08)
#define CCMU_FRE_UP_LIM_REG (CCMU_BASE + 0x0F0C)
#define CCMU_FRE_DOWN_LIM_REG (CCMU_BASE + 0x0F10)
//#define PLL_CPUX_HW_FM_REG (CCMU_BASE + 0x0F20)
#define CCMU_FAN_GATE_REG (CCMU_BASE + 0x0F30)
#define CCMU_CLK27M_FAN_REG (CCMU_BASE + 0x0F34)
#define CCMU_PCLK_FAN_REG (CCMU_BASE + 0x0F38)
#define CCMU_FAN_REG (CCMU_BASE + 0x0F3C)
//#define CCMU_MOD_SPE_CLK_REG (CCMU_BASE + 0x0F30)
//#define CCMU_HOSC_CTRL_CLK_REG (CCMU_BASE + 0x0f40)
#define CCMU_VERSION_REG (CCMU_BASE + 0x0FF0)
#define CCMU_VER_REG (CCMU_BASE + 0x0FF0)
/* select cpu/cpus/abps1 clock source to hosc */
static inline void cpu2hosc(void)
{
}
static inline void cpu2pll(void)
{
}
static inline void set_standby_flag(u32 __attribute__((unused)) flag)
{
writel(flag, (void *)SUPER_STANDBY_FLAG_REG);
}
static inline void set_standby_entry(u32 __attribute__((unused)) entry)
{
writel(entry, (void *)SUPER_STANDBY_ENTRY_REG);
}
#endif /* __CLK_SUN8IW20P1_H__ */