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mp_startup.c
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mp_startup.c
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/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* or http://www.opensolaris.org/os/licensing.
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright (c) 1992, 2010, Oracle and/or its affiliates. All rights reserved.
*/
/*
* Copyright (c) 2010, Intel Corporation.
* All rights reserved.
*/
/*
* Copyright 2018 Joyent, Inc.
* Copyright 2013 Nexenta Systems, Inc. All rights reserved.
*/
#include <sys/types.h>
#include <sys/thread.h>
#include <sys/cpuvar.h>
#include <sys/cpu.h>
#include <sys/t_lock.h>
#include <sys/param.h>
#include <sys/proc.h>
#include <sys/disp.h>
#include <sys/class.h>
#include <sys/cmn_err.h>
#include <sys/debug.h>
#include <sys/note.h>
#include <sys/asm_linkage.h>
#include <sys/x_call.h>
#include <sys/systm.h>
#include <sys/var.h>
#include <sys/vtrace.h>
#include <vm/hat.h>
#include <vm/as.h>
#include <vm/seg_kmem.h>
#include <vm/seg_kp.h>
#include <sys/segments.h>
#include <sys/kmem.h>
#include <sys/stack.h>
#include <sys/smp_impldefs.h>
#include <sys/x86_archext.h>
#include <sys/machsystm.h>
#include <sys/traptrace.h>
#include <sys/clock.h>
#include <sys/cpc_impl.h>
#include <sys/pg.h>
#include <sys/cmt.h>
#include <sys/dtrace.h>
#include <sys/archsystm.h>
#include <sys/fp.h>
#include <sys/reboot.h>
#include <sys/kdi_machimpl.h>
#include <vm/hat_i86.h>
#include <vm/vm_dep.h>
#include <sys/memnode.h>
#include <sys/pci_cfgspace.h>
#include <sys/mach_mmu.h>
#include <sys/sysmacros.h>
#if defined(__xpv)
#include <sys/hypervisor.h>
#endif
#include <sys/cpu_module.h>
#include <sys/ontrap.h>
struct cpu cpus[1] __aligned(MMU_PAGESIZE);
struct cpu *cpu[NCPU] = {&cpus[0]};
struct cpu *cpu_free_list;
cpu_core_t cpu_core[NCPU];
#define cpu_next_free cpu_prev
/*
* Useful for disabling MP bring-up on a MP capable system.
*/
int use_mp = 1;
/*
* to be set by a PSM to indicate what cpus
* are sitting around on the system.
*/
cpuset_t mp_cpus;
/*
* This variable is used by the hat layer to decide whether or not
* critical sections are needed to prevent race conditions. For sun4m,
* this variable is set once enough MP initialization has been done in
* order to allow cross calls.
*/
int flushes_require_xcalls;
cpuset_t cpu_ready_set; /* initialized in startup() */
static void mp_startup_boot(void);
static void mp_startup_hotplug(void);
static void cpu_sep_enable(void);
static void cpu_sep_disable(void);
static void cpu_asysc_enable(void);
static void cpu_asysc_disable(void);
/*
* Init CPU info - get CPU type info for processor_info system call.
*/
void
init_cpu_info(struct cpu *cp)
{
processor_info_t *pi = &cp->cpu_type_info;
/*
* Get clock-frequency property for the CPU.
*/
pi->pi_clock = cpu_freq;
/*
* Current frequency in Hz.
*/
cp->cpu_curr_clock = cpu_freq_hz;
/*
* Supported frequencies.
*/
if (cp->cpu_supp_freqs == NULL) {
cpu_set_supp_freqs(cp, NULL);
}
(void) strcpy(pi->pi_processor_type, "i386");
if (fpu_exists)
(void) strcpy(pi->pi_fputypes, "i387 compatible");
cp->cpu_idstr = kmem_zalloc(CPU_IDSTRLEN, KM_SLEEP);
cp->cpu_brandstr = kmem_zalloc(CPU_IDSTRLEN, KM_SLEEP);
/*
* If called for the BSP, cp is equal to current CPU.
* For non-BSPs, cpuid info of cp is not ready yet, so use cpuid info
* of current CPU as default values for cpu_idstr and cpu_brandstr.
* They will be corrected in mp_startup_common() after cpuid_pass1()
* has been invoked on target CPU.
*/
(void) cpuid_getidstr(CPU, cp->cpu_idstr, CPU_IDSTRLEN);
(void) cpuid_getbrandstr(CPU, cp->cpu_brandstr, CPU_IDSTRLEN);
}
/*
* Configure syscall support on this CPU.
*/
/*ARGSUSED*/
void
init_cpu_syscall(struct cpu *cp)
{
kpreempt_disable();
if (is_x86_feature(x86_featureset, X86FSET_MSR) &&
is_x86_feature(x86_featureset, X86FSET_ASYSC)) {
uint64_t flags;
#if !defined(__xpv)
/*
* The syscall instruction imposes a certain ordering on
* segment selectors, so we double-check that ordering
* here.
*/
CTASSERT(KDS_SEL == KCS_SEL + 8);
CTASSERT(UDS_SEL == U32CS_SEL + 8);
CTASSERT(UCS_SEL == U32CS_SEL + 16);
#endif
/*
* Turn syscall/sysret extensions on.
*/
cpu_asysc_enable();
/*
* Program the magic registers ..
*/
wrmsr(MSR_AMD_STAR,
((uint64_t)(U32CS_SEL << 16 | KCS_SEL)) << 32);
if (kpti_enable == 1) {
wrmsr(MSR_AMD_LSTAR,
(uint64_t)(uintptr_t)tr_sys_syscall);
wrmsr(MSR_AMD_CSTAR,
(uint64_t)(uintptr_t)tr_sys_syscall32);
} else {
wrmsr(MSR_AMD_LSTAR,
(uint64_t)(uintptr_t)sys_syscall);
wrmsr(MSR_AMD_CSTAR,
(uint64_t)(uintptr_t)sys_syscall32);
}
/*
* This list of flags is masked off the incoming
* %rfl when we enter the kernel.
*/
flags = PS_IE | PS_T;
if (is_x86_feature(x86_featureset, X86FSET_SMAP) == B_TRUE)
flags |= PS_ACHK;
wrmsr(MSR_AMD_SFMASK, flags);
}
/*
* On 64-bit kernels on Nocona machines, the 32-bit syscall
* variant isn't available to 32-bit applications, but sysenter is.
*/
if (is_x86_feature(x86_featureset, X86FSET_MSR) &&
is_x86_feature(x86_featureset, X86FSET_SEP)) {
#if !defined(__xpv)
/*
* The sysenter instruction imposes a certain ordering on
* segment selectors, so we double-check that ordering
* here. See "sysenter" in Intel document 245471-012, "IA-32
* Intel Architecture Software Developer's Manual Volume 2:
* Instruction Set Reference"
*/
CTASSERT(KDS_SEL == KCS_SEL + 8);
CTASSERT(U32CS_SEL == ((KCS_SEL + 16) | 3));
CTASSERT(UDS_SEL == U32CS_SEL + 8);
#endif
cpu_sep_enable();
/*
* resume() sets this value to the base of the threads stack
* via a context handler.
*/
wrmsr(MSR_INTC_SEP_ESP, 0);
if (kpti_enable == 1) {
wrmsr(MSR_INTC_SEP_EIP,
(uint64_t)(uintptr_t)tr_sys_sysenter);
} else {
wrmsr(MSR_INTC_SEP_EIP,
(uint64_t)(uintptr_t)sys_sysenter);
}
}
kpreempt_enable();
}
#if !defined(__xpv)
/*
* Configure per-cpu ID GDT
*/
static void
init_cpu_id_gdt(struct cpu *cp)
{
/* Write cpu_id into limit field of GDT for usermode retrieval */
#if defined(__amd64)
set_usegd(&cp->cpu_gdt[GDT_CPUID], SDP_SHORT, NULL, cp->cpu_id,
SDT_MEMRODA, SEL_UPL, SDP_BYTES, SDP_OP32);
#elif defined(__i386)
set_usegd(&cp->cpu_gdt[GDT_CPUID], NULL, cp->cpu_id, SDT_MEMRODA,
SEL_UPL, SDP_BYTES, SDP_OP32);
#endif
}
#endif /* !defined(__xpv) */
/*
* Multiprocessor initialization.
*
* Allocate and initialize the cpu structure, TRAPTRACE buffer, and the
* startup and idle threads for the specified CPU.
* Parameter boot is true for boot time operations and is false for CPU
* DR operations.
*/
static struct cpu *
mp_cpu_configure_common(int cpun, boolean_t boot)
{
struct cpu *cp;
kthread_id_t tp;
caddr_t sp;
proc_t *procp;
#if !defined(__xpv)
extern int idle_cpu_prefer_mwait;
extern void cpu_idle_mwait();
#endif
extern void idle();
extern void cpu_idle();
#ifdef TRAPTRACE
trap_trace_ctl_t *ttc = &trap_trace_ctl[cpun];
#endif
ASSERT(MUTEX_HELD(&cpu_lock));
ASSERT(cpun < NCPU && cpu[cpun] == NULL);
if (cpu_free_list == NULL) {
cp = kmem_zalloc(sizeof (*cp), KM_SLEEP);
} else {
cp = cpu_free_list;
cpu_free_list = cp->cpu_next_free;
}
cp->cpu_m.mcpu_istamp = cpun << 16;
/* Create per CPU specific threads in the process p0. */
procp = &p0;
/*
* Initialize the dispatcher first.
*/
disp_cpu_init(cp);
cpu_vm_data_init(cp);
/*
* Allocate and initialize the startup thread for this CPU.
* Interrupt and process switch stacks get allocated later
* when the CPU starts running.
*/
tp = thread_create(NULL, 0, NULL, NULL, 0, procp,
TS_STOPPED, maxclsyspri);
/*
* Set state to TS_ONPROC since this thread will start running
* as soon as the CPU comes online.
*
* All the other fields of the thread structure are setup by
* thread_create().
*/
THREAD_ONPROC(tp, cp);
tp->t_preempt = 1;
tp->t_bound_cpu = cp;
tp->t_affinitycnt = 1;
tp->t_cpu = cp;
tp->t_disp_queue = cp->cpu_disp;
/*
* Setup thread to start in mp_startup_common.
*/
sp = tp->t_stk;
tp->t_sp = (uintptr_t)(sp - MINFRAME);
#if defined(__amd64)
tp->t_sp -= STACK_ENTRY_ALIGN; /* fake a call */
#endif
/*
* Setup thread start entry point for boot or hotplug.
*/
if (boot) {
tp->t_pc = (uintptr_t)mp_startup_boot;
} else {
tp->t_pc = (uintptr_t)mp_startup_hotplug;
}
cp->cpu_id = cpun;
cp->cpu_self = cp;
cp->cpu_thread = tp;
cp->cpu_lwp = NULL;
cp->cpu_dispthread = tp;
cp->cpu_dispatch_pri = DISP_PRIO(tp);
/*
* cpu_base_spl must be set explicitly here to prevent any blocking
* operations in mp_startup_common from causing the spl of the cpu
* to drop to 0 (allowing device interrupts before we're ready) in
* resume().
* cpu_base_spl MUST remain at LOCK_LEVEL until the cpu is CPU_READY.
* As an extra bit of security on DEBUG kernels, this is enforced with
* an assertion in mp_startup_common() -- before cpu_base_spl is set
* to its proper value.
*/
cp->cpu_base_spl = ipltospl(LOCK_LEVEL);
/*
* Now, initialize per-CPU idle thread for this CPU.
*/
tp = thread_create(NULL, PAGESIZE, idle, NULL, 0, procp, TS_ONPROC, -1);
cp->cpu_idle_thread = tp;
tp->t_preempt = 1;
tp->t_bound_cpu = cp;
tp->t_affinitycnt = 1;
tp->t_cpu = cp;
tp->t_disp_queue = cp->cpu_disp;
/*
* Bootstrap the CPU's PG data
*/
pg_cpu_bootstrap(cp);
/*
* Perform CPC initialization on the new CPU.
*/
kcpc_hw_init(cp);
/*
* Allocate virtual addresses for cpu_caddr1 and cpu_caddr2
* for each CPU.
*/
setup_vaddr_for_ppcopy(cp);
/*
* Allocate page for new GDT and initialize from current GDT.
*/
#if !defined(__lint)
ASSERT((sizeof (*cp->cpu_gdt) * NGDT) <= PAGESIZE);
#endif
cp->cpu_gdt = kmem_zalloc(PAGESIZE, KM_SLEEP);
bcopy(CPU->cpu_gdt, cp->cpu_gdt, (sizeof (*cp->cpu_gdt) * NGDT));
#if defined(__i386)
/*
* setup kernel %gs.
*/
set_usegd(&cp->cpu_gdt[GDT_GS], cp, sizeof (struct cpu) -1, SDT_MEMRWA,
SEL_KPL, 0, 1);
#endif
/*
* Allocate pages for the CPU LDT.
*/
cp->cpu_m.mcpu_ldt = kmem_zalloc(LDT_CPU_SIZE, KM_SLEEP);
cp->cpu_m.mcpu_ldt_len = 0;
/*
* Allocate a per-CPU IDT and initialize the new IDT to the currently
* runing CPU.
*/
#if !defined(__lint)
ASSERT((sizeof (*CPU->cpu_idt) * NIDT) <= PAGESIZE);
#endif
cp->cpu_idt = kmem_alloc(PAGESIZE, KM_SLEEP);
bcopy(CPU->cpu_idt, cp->cpu_idt, PAGESIZE);
/*
* alloc space for cpuid info
*/
cpuid_alloc_space(cp);
#if !defined(__xpv)
if (is_x86_feature(x86_featureset, X86FSET_MWAIT) &&
idle_cpu_prefer_mwait) {
cp->cpu_m.mcpu_mwait = cpuid_mwait_alloc(cp);
cp->cpu_m.mcpu_idle_cpu = cpu_idle_mwait;
} else
#endif
cp->cpu_m.mcpu_idle_cpu = cpu_idle;
init_cpu_info(cp);
#if !defined(__xpv)
init_cpu_id_gdt(cp);
#endif
/*
* alloc space for ucode_info
*/
ucode_alloc_space(cp);
xc_init_cpu(cp);
hat_cpu_online(cp);
#ifdef TRAPTRACE
/*
* If this is a TRAPTRACE kernel, allocate TRAPTRACE buffers
*/
ttc->ttc_first = (uintptr_t)kmem_zalloc(trap_trace_bufsize, KM_SLEEP);
ttc->ttc_next = ttc->ttc_first;
ttc->ttc_limit = ttc->ttc_first + trap_trace_bufsize;
#endif
/*
* Record that we have another CPU.
*/
/*
* Initialize the interrupt threads for this CPU
*/
cpu_intr_alloc(cp, NINTR_THREADS);
cp->cpu_flags = CPU_OFFLINE | CPU_QUIESCED | CPU_POWEROFF;
cpu_set_state(cp);
/*
* Add CPU to list of available CPUs. It'll be on the active list
* after mp_startup_common().
*/
cpu_add_unit(cp);
return (cp);
}
/*
* Undo what was done in mp_cpu_configure_common
*/
static void
mp_cpu_unconfigure_common(struct cpu *cp, int error)
{
ASSERT(MUTEX_HELD(&cpu_lock));
/*
* Remove the CPU from the list of available CPUs.
*/
cpu_del_unit(cp->cpu_id);
if (error == ETIMEDOUT) {
/*
* The cpu was started, but never *seemed* to run any
* code in the kernel; it's probably off spinning in its
* own private world, though with potential references to
* our kmem-allocated IDTs and GDTs (for example).
*
* Worse still, it may actually wake up some time later,
* so rather than guess what it might or might not do, we
* leave the fundamental data structures intact.
*/
cp->cpu_flags = 0;
return;
}
/*
* At this point, the only threads bound to this CPU should
* special per-cpu threads: it's idle thread, it's pause threads,
* and it's interrupt threads. Clean these up.
*/
cpu_destroy_bound_threads(cp);
cp->cpu_idle_thread = NULL;
/*
* Free the interrupt stack.
*/
segkp_release(segkp,
cp->cpu_intr_stack - (INTR_STACK_SIZE - SA(MINFRAME)));
cp->cpu_intr_stack = NULL;
#ifdef TRAPTRACE
/*
* Discard the trap trace buffer
*/
{
trap_trace_ctl_t *ttc = &trap_trace_ctl[cp->cpu_id];
kmem_free((void *)ttc->ttc_first, trap_trace_bufsize);
ttc->ttc_first = NULL;
}
#endif
hat_cpu_offline(cp);
ucode_free_space(cp);
/* Free CPU ID string and brand string. */
if (cp->cpu_idstr) {
kmem_free(cp->cpu_idstr, CPU_IDSTRLEN);
cp->cpu_idstr = NULL;
}
if (cp->cpu_brandstr) {
kmem_free(cp->cpu_brandstr, CPU_IDSTRLEN);
cp->cpu_brandstr = NULL;
}
#if !defined(__xpv)
if (cp->cpu_m.mcpu_mwait != NULL) {
cpuid_mwait_free(cp);
cp->cpu_m.mcpu_mwait = NULL;
}
#endif
cpuid_free_space(cp);
if (cp->cpu_idt != CPU->cpu_idt)
kmem_free(cp->cpu_idt, PAGESIZE);
cp->cpu_idt = NULL;
kmem_free(cp->cpu_m.mcpu_ldt, LDT_CPU_SIZE);
cp->cpu_m.mcpu_ldt = NULL;
cp->cpu_m.mcpu_ldt_len = 0;
kmem_free(cp->cpu_gdt, PAGESIZE);
cp->cpu_gdt = NULL;
if (cp->cpu_supp_freqs != NULL) {
size_t len = strlen(cp->cpu_supp_freqs) + 1;
kmem_free(cp->cpu_supp_freqs, len);
cp->cpu_supp_freqs = NULL;
}
teardown_vaddr_for_ppcopy(cp);
kcpc_hw_fini(cp);
cp->cpu_dispthread = NULL;
cp->cpu_thread = NULL; /* discarded by cpu_destroy_bound_threads() */
cpu_vm_data_destroy(cp);
xc_fini_cpu(cp);
disp_cpu_fini(cp);
ASSERT(cp != CPU0);
bzero(cp, sizeof (*cp));
cp->cpu_next_free = cpu_free_list;
cpu_free_list = cp;
}
/*
* Apply workarounds for known errata, and warn about those that are absent.
*
* System vendors occasionally create configurations which contain different
* revisions of the CPUs that are almost but not exactly the same. At the
* time of writing, this meant that their clock rates were the same, their
* feature sets were the same, but the required workaround were -not-
* necessarily the same. So, this routine is invoked on -every- CPU soon
* after starting to make sure that the resulting system contains the most
* pessimal set of workarounds needed to cope with *any* of the CPUs in the
* system.
*
* workaround_errata is invoked early in mlsetup() for CPU 0, and in
* mp_startup_common() for all slave CPUs. Slaves process workaround_errata
* prior to acknowledging their readiness to the master, so this routine will
* never be executed by multiple CPUs in parallel, thus making updates to
* global data safe.
*
* These workarounds are based on Rev 3.57 of the Revision Guide for
* AMD Athlon(tm) 64 and AMD Opteron(tm) Processors, August 2005.
*/
#if defined(OPTERON_ERRATUM_88)
int opteron_erratum_88; /* if non-zero -> at least one cpu has it */
#endif
#if defined(OPTERON_ERRATUM_91)
int opteron_erratum_91; /* if non-zero -> at least one cpu has it */
#endif
#if defined(OPTERON_ERRATUM_93)
int opteron_erratum_93; /* if non-zero -> at least one cpu has it */
#endif
#if defined(OPTERON_ERRATUM_95)
int opteron_erratum_95; /* if non-zero -> at least one cpu has it */
#endif
#if defined(OPTERON_ERRATUM_100)
int opteron_erratum_100; /* if non-zero -> at least one cpu has it */
#endif
#if defined(OPTERON_ERRATUM_108)
int opteron_erratum_108; /* if non-zero -> at least one cpu has it */
#endif
#if defined(OPTERON_ERRATUM_109)
int opteron_erratum_109; /* if non-zero -> at least one cpu has it */
#endif
#if defined(OPTERON_ERRATUM_121)
int opteron_erratum_121; /* if non-zero -> at least one cpu has it */
#endif
#if defined(OPTERON_ERRATUM_122)
int opteron_erratum_122; /* if non-zero -> at least one cpu has it */
#endif
#if defined(OPTERON_ERRATUM_123)
int opteron_erratum_123; /* if non-zero -> at least one cpu has it */
#endif
#if defined(OPTERON_ERRATUM_131)
int opteron_erratum_131; /* if non-zero -> at least one cpu has it */
#endif
#if defined(OPTERON_WORKAROUND_6336786)
int opteron_workaround_6336786; /* non-zero -> WA relevant and applied */
int opteron_workaround_6336786_UP = 0; /* Not needed for UP */
#endif
#if defined(OPTERON_WORKAROUND_6323525)
int opteron_workaround_6323525; /* if non-zero -> at least one cpu has it */
#endif
#if defined(OPTERON_ERRATUM_298)
int opteron_erratum_298;
#endif
#if defined(OPTERON_ERRATUM_721)
int opteron_erratum_721;
#endif
static void
workaround_warning(cpu_t *cp, uint_t erratum)
{
cmn_err(CE_WARN, "cpu%d: no workaround for erratum %u",
cp->cpu_id, erratum);
}
static void
workaround_applied(uint_t erratum)
{
if (erratum > 1000000)
cmn_err(CE_CONT, "?workaround applied for cpu issue #%d\n",
erratum);
else
cmn_err(CE_CONT, "?workaround applied for cpu erratum #%d\n",
erratum);
}
static void
msr_warning(cpu_t *cp, const char *rw, uint_t msr, int error)
{
cmn_err(CE_WARN, "cpu%d: couldn't %smsr 0x%x, error %d",
cp->cpu_id, rw, msr, error);
}
/*
* Determine the number of nodes in a Hammer / Greyhound / Griffin family
* system.
*/
static uint_t
opteron_get_nnodes(void)
{
static uint_t nnodes = 0;
if (nnodes == 0) {
#ifdef DEBUG
uint_t family;
/*
* This routine uses a PCI config space based mechanism
* for retrieving the number of nodes in the system.
* Device 24, function 0, offset 0x60 as used here is not
* AMD processor architectural, and may not work on processor
* families other than those listed below.
*
* Callers of this routine must ensure that we're running on
* a processor which supports this mechanism.
* The assertion below is meant to catch calls on unsupported
* processors.
*/
family = cpuid_getfamily(CPU);
ASSERT(family == 0xf || family == 0x10 || family == 0x11);
#endif /* DEBUG */
/*
* Obtain the number of nodes in the system from
* bits [6:4] of the Node ID register on node 0.
*
* The actual node count is NodeID[6:4] + 1
*
* The Node ID register is accessed via function 0,
* offset 0x60. Node 0 is device 24.
*/
nnodes = ((pci_getl_func(0, 24, 0, 0x60) & 0x70) >> 4) + 1;
}
return (nnodes);
}
uint_t
do_erratum_298(struct cpu *cpu)
{
static int osvwrc = -3;
extern int osvw_opteron_erratum(cpu_t *, uint_t);
/*
* L2 Eviction May Occur During Processor Operation To Set
* Accessed or Dirty Bit.
*/
if (osvwrc == -3) {
osvwrc = osvw_opteron_erratum(cpu, 298);
} else {
/* osvw return codes should be consistent for all cpus */
ASSERT(osvwrc == osvw_opteron_erratum(cpu, 298));
}
switch (osvwrc) {
case 0: /* erratum is not present: do nothing */
break;
case 1: /* erratum is present: BIOS workaround applied */
/*
* check if workaround is actually in place and issue warning
* if not.
*/
if (((rdmsr(MSR_AMD_HWCR) & AMD_HWCR_TLBCACHEDIS) == 0) ||
((rdmsr(MSR_AMD_BU_CFG) & AMD_BU_CFG_E298) == 0)) {
#if defined(OPTERON_ERRATUM_298)
opteron_erratum_298++;
#else
workaround_warning(cpu, 298);
return (1);
#endif
}
break;
case -1: /* cannot determine via osvw: check cpuid */
if ((cpuid_opteron_erratum(cpu, 298) > 0) &&
(((rdmsr(MSR_AMD_HWCR) & AMD_HWCR_TLBCACHEDIS) == 0) ||
((rdmsr(MSR_AMD_BU_CFG) & AMD_BU_CFG_E298) == 0))) {
#if defined(OPTERON_ERRATUM_298)
opteron_erratum_298++;
#else
workaround_warning(cpu, 298);
return (1);
#endif
}
break;
}
return (0);
}
uint_t
workaround_errata(struct cpu *cpu)
{
uint_t missing = 0;
ASSERT(cpu == CPU);
/*LINTED*/
if (cpuid_opteron_erratum(cpu, 88) > 0) {
/*
* SWAPGS May Fail To Read Correct GS Base
*/
#if defined(OPTERON_ERRATUM_88)
/*
* The workaround is an mfence in the relevant assembler code
*/
opteron_erratum_88++;
#else
workaround_warning(cpu, 88);
missing++;
#endif
}
if (cpuid_opteron_erratum(cpu, 91) > 0) {
/*
* Software Prefetches May Report A Page Fault
*/
#if defined(OPTERON_ERRATUM_91)
/*
* fix is in trap.c
*/
opteron_erratum_91++;
#else
workaround_warning(cpu, 91);
missing++;
#endif
}
if (cpuid_opteron_erratum(cpu, 93) > 0) {
/*
* RSM Auto-Halt Restart Returns to Incorrect RIP
*/
#if defined(OPTERON_ERRATUM_93)
/*
* fix is in trap.c
*/
opteron_erratum_93++;
#else
workaround_warning(cpu, 93);
missing++;
#endif
}
/*LINTED*/
if (cpuid_opteron_erratum(cpu, 95) > 0) {
/*
* RET Instruction May Return to Incorrect EIP
*/
#if defined(OPTERON_ERRATUM_95)
#if defined(_LP64)
/*
* Workaround this by ensuring that 32-bit user code and
* 64-bit kernel code never occupy the same address
* range mod 4G.
*/
if (_userlimit32 > 0xc0000000ul)
*(uintptr_t *)&_userlimit32 = 0xc0000000ul;
/*LINTED*/
ASSERT((uint32_t)COREHEAP_BASE == 0xc0000000u);
opteron_erratum_95++;
#endif /* _LP64 */
#else
workaround_warning(cpu, 95);
missing++;
#endif
}
if (cpuid_opteron_erratum(cpu, 100) > 0) {
/*
* Compatibility Mode Branches Transfer to Illegal Address
*/
#if defined(OPTERON_ERRATUM_100)
/*
* fix is in trap.c
*/
opteron_erratum_100++;
#else
workaround_warning(cpu, 100);
missing++;
#endif
}
/*LINTED*/
if (cpuid_opteron_erratum(cpu, 108) > 0) {
/*
* CPUID Instruction May Return Incorrect Model Number In
* Some Processors
*/
#if defined(OPTERON_ERRATUM_108)
/*
* (Our cpuid-handling code corrects the model number on
* those processors)
*/
#else
workaround_warning(cpu, 108);
missing++;
#endif
}
/*LINTED*/
if (cpuid_opteron_erratum(cpu, 109) > 0) do {
/*
* Certain Reverse REP MOVS May Produce Unpredictable Behavior
*/
#if defined(OPTERON_ERRATUM_109)
/*
* The "workaround" is to print a warning to upgrade the BIOS
*/
uint64_t value;
const uint_t msr = MSR_AMD_PATCHLEVEL;
int err;
if ((err = checked_rdmsr(msr, &value)) != 0) {
msr_warning(cpu, "rd", msr, err);
workaround_warning(cpu, 109);
missing++;
}
if (value == 0)
opteron_erratum_109++;
#else
workaround_warning(cpu, 109);
missing++;
#endif
/*CONSTANTCONDITION*/
} while (0);
/*LINTED*/
if (cpuid_opteron_erratum(cpu, 121) > 0) {
/*
* Sequential Execution Across Non_Canonical Boundary Caused
* Processor Hang
*/
#if defined(OPTERON_ERRATUM_121)
#if defined(_LP64)
/*
* Erratum 121 is only present in long (64 bit) mode.
* Workaround is to include the page immediately before the
* va hole to eliminate the possibility of system hangs due to
* sequential execution across the va hole boundary.
*/
if (opteron_erratum_121)
opteron_erratum_121++;
else {
if (hole_start) {
hole_start -= PAGESIZE;
} else {
/*
* hole_start not yet initialized by
* mmu_init. Initialize hole_start
* with value to be subtracted.
*/
hole_start = PAGESIZE;
}
opteron_erratum_121++;
}
#endif /* _LP64 */
#else
workaround_warning(cpu, 121);
missing++;
#endif
}
/*LINTED*/
if (cpuid_opteron_erratum(cpu, 122) > 0) do {
/*
* TLB Flush Filter May Cause Coherency Problem in
* Multiprocessor Systems
*/
#if defined(OPTERON_ERRATUM_122)
uint64_t value;
const uint_t msr = MSR_AMD_HWCR;
int error;
/*
* Erratum 122 is only present in MP configurations (multi-core
* or multi-processor).