/
0001-feat-integrate-VPU-which-is-based-on-0.8-release-SPE.patch
1838 lines (1771 loc) · 125 KB
/
0001-feat-integrate-VPU-which-is-based-on-0.8-release-SPE.patch
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From 56a2f047a9ac33350f2726afa0f3b3f40e43616b Mon Sep 17 00:00:00 2001
From: liangzhanhao <549830592@qq.com>
Date: Mon, 14 Sep 2020 19:11:34 +0800
Subject: [PATCH] feat: integrate VPU which is based on 0.8-release SPEC
---
build.sbt | 6 +
src/main/scala/rocket/CSR.scala | 237 ++++++---
src/main/scala/rocket/IDecode.scala | 568 +++++++++++++--------
src/main/scala/rocket/Instructions.scala | 139 +++++
src/main/scala/rocket/RocketCore.scala | 78 ++-
src/main/scala/subsystem/Configs.scala | 63 +++
src/main/scala/system/Configs.scala | 9 +-
src/main/scala/tile/BaseTile.scala | 6 +-
src/main/scala/tile/Core.scala | 8 +
src/main/scala/tile/FPU.scala | 25 +
src/main/scala/tile/RocketTile.scala | 23 +-
src/main/scala/vpuwrapper/VPUWrapper.scala | 53 ++
12 files changed, 920 insertions(+), 295 deletions(-)
create mode 100644 src/main/scala/vpuwrapper/VPUWrapper.scala
diff --git a/build.sbt b/build.sbt
index 3433aeed7..21fc23ded 100644
--- a/build.sbt
+++ b/build.sbt
@@ -83,10 +83,14 @@ lazy val hardfloat = dependOnChisel(project).settings(commonSettings)
.settings(publishArtifact := false)
lazy val `rocket-macros` = (project in file("macros")).settings(commonSettings)
.settings(publishArtifact := false)
+lazy val vpu = dependOnChisel(project).settings(commonSettings) //add for VPU
+ .settings(publishArtifact := false) //add for VPU
+ .dependsOn(hardfloat % "compile-internal;test-internal") //add for VPU
lazy val rocketchip = dependOnChisel(project in file("."))
.settings(commonSettings, chipSettings)
.dependsOn(`api-config-chipsalliance` % "compile-internal;test-internal")
.dependsOn(hardfloat % "compile-internal;test-internal")
+ .dependsOn(vpu % "compile-internal;test-internal") //add for VPU
.dependsOn(`rocket-macros` % "compile-internal;test-internal")
.settings(
aggregate := false,
@@ -95,6 +99,8 @@ lazy val rocketchip = dependOnChisel(project in file("."))
mappings in (Compile, packageSrc) ++= (mappings in (`api-config-chipsalliance`, Compile, packageSrc)).value,
mappings in (Compile, packageBin) ++= (mappings in (hardfloat, Compile, packageBin)).value,
mappings in (Compile, packageSrc) ++= (mappings in (hardfloat, Compile, packageSrc)).value,
+ mappings in (Compile, packageBin) ++= (mappings in (vpu, Compile, packageBin)).value, //add for VPU
+ mappings in (Compile, packageSrc) ++= (mappings in (vpu, Compile, packageSrc)).value, //add for VPU
mappings in (Compile, packageBin) ++= (mappings in (`rocket-macros`, Compile, packageBin)).value,
mappings in (Compile, packageSrc) ++= (mappings in (`rocket-macros`, Compile, packageSrc)).value,
exportJars := true
diff --git a/src/main/scala/rocket/CSR.scala b/src/main/scala/rocket/CSR.scala
index 0cf3d0d2b..fa175e896 100644
--- a/src/main/scala/rocket/CSR.scala
+++ b/src/main/scala/rocket/CSR.scala
@@ -12,6 +12,7 @@ import freechips.rocketchip.util._
import freechips.rocketchip.util.property._
import scala.collection.mutable.LinkedHashMap
import Instructions._
+import vpu._
class MStatus extends Bundle {
// not truly part of mstatus, but convenient
@@ -27,7 +28,10 @@ class MStatus extends Bundle {
val sxl = UInt(width = 2)
val uxl = UInt(width = 2)
val sd_rv32 = Bool()
- val zero1 = UInt(width = 8)
+ // val zero1 = UInt(width = 8)
+ val zero1 = UInt(width = 5) //add for VPU, 0.8-release SPEC
+ val dcache_dis = Bool() //add for VPU, 0.8-release SPEC
+ val vs = UInt(width = 2) //add for VPU, 0.8-release SPEC
val tsr = Bool()
val tw = Bool()
val tvm = Bool()
@@ -37,7 +41,8 @@ class MStatus extends Bundle {
val xs = UInt(width = 2)
val fs = UInt(width = 2)
val mpp = UInt(width = 2)
- val vs = UInt(width = 2)
+// val vs = UInt(width = 2)
+ val hpp = UInt(width = 2) //add for VPU
val spp = UInt(width = 1)
val mpie = Bool()
val hpie = Bool()
@@ -181,6 +186,7 @@ class CSRDecodeIO extends Bundle {
val fp_illegal = Bool(OUTPUT)
val vector_illegal = Bool(OUTPUT)
val fp_csr = Bool(OUTPUT)
+ val vp_csr = Bool(OUTPUT) //add for VPU
val rocc_illegal = Bool(OUTPUT)
val read_illegal = Bool(OUTPUT)
val write_illegal = Bool(OUTPUT)
@@ -218,6 +224,14 @@ class CSRFileIO(implicit p: Parameters) extends CoreBundle
val fcsr_rm = Bits(OUTPUT, FPConstants.RM_SZ)
val fcsr_flags = Valid(Bits(width = FPConstants.FLAGS_SZ)).flip
val set_fs_dirty = coreParams.haveFSDirty.option(Bool(INPUT))
+ //add for VPU
+ val vcsr_vxrm = Bits(OUTPUT, VPUConstants.XRM_SZ)
+ val vcsr_vxsat = Valid(Bits(width = VPUConstants.XSAT_SZ)).flip
+ val vcsr_vstart = Bits(INPUT, log2Ceil(VLEN))
+ val vcsr_vl = Bits(INPUT, xLen)
+ val vcsr_vtype = Bits(INPUT, xLen)
+ val set_vs_dirty = coreParams.haveVSDirty.option(Bool(INPUT))
+ //add for VPU
val rocc_interrupt = Bool(INPUT)
val interrupt = Bool(OUTPUT)
val interrupt_cause = UInt(OUTPUT, xLen)
@@ -394,10 +408,17 @@ class CSRFile(
val reg_fflags = Reg(UInt(width = 5))
val reg_frm = Reg(UInt(width = 3))
- val reg_vconfig = usingVector.option(Reg(new VConfig))
- val reg_vstart = usingVector.option(Reg(UInt(maxVLMax.log2.W)))
- val reg_vxsat = usingVector.option(Reg(Bool()))
- val reg_vxrm = usingVector.option(Reg(UInt(io.vector.get.vxrm.getWidth.W)))
+// val reg_vconfig = usingVector.option(Reg(new VConfig))
+// val reg_vstart = usingVector.option(Reg(UInt(maxVLMax.log2.W)))
+// val reg_vxsat = usingVector.option(Reg(Bool()))
+// val reg_vxrm = usingVector.option(Reg(UInt(io.vector.get.vxrm.getWidth.W)))
+ //add for VPU
+ val reg_vstart = Reg(UInt(width = log2Ceil(VLEN)))
+ val reg_vxsat = Reg(UInt(width = 1))
+ val reg_vxrm = Reg(UInt(width = 2))
+ val reg_vl = Reg(UInt(width = xLen))
+ val reg_vtype = Reg(UInt(width = xLen))
+ //add for VPU
val reg_instret = WideCounter(64, io.retire)
val reg_cycle = if (enableCommitLog) reg_instret else withClock(io.ungated_clock) { WideCounter(64, !io.csr_stall) }
@@ -433,7 +454,8 @@ class CSRFile(
(if (usingAtomics) "A" else "") +
(if (fLen >= 32) "F" else "") +
(if (fLen >= 64) "D" else "") +
- (if (usingVector) "V" else "") +
+// (if (usingVector) "V" else "") +
+ (if (usingVPU) "V" else "") + //add for VPU
(if (usingCompressed) "C" else "")
val isaString = (if (coreParams.useRVE) "E" else "I") +
isaMaskString +
@@ -466,23 +488,45 @@ class CSRFile(
CSRs.dpc -> readEPC(reg_dpc).sextTo(xLen),
CSRs.dscratch -> reg_dscratch.asUInt)
- val read_fcsr = Cat(reg_frm, reg_fflags) | (reg_vxsat.getOrElse(0.U) << 8) | (reg_vxrm.getOrElse(0.U) << 9)
- val fp_csrs = LinkedHashMap[Int,Bits]() ++
- usingFPU.option(CSRs.fflags -> reg_fflags) ++
- usingFPU.option(CSRs.frm -> reg_frm) ++
- (usingFPU || usingVector).option(CSRs.fcsr -> read_fcsr) ++
- reg_vxsat.map(CSRs.vxsat -> _) ++
- reg_vxrm.map(CSRs.vxrm -> _)
-
- val vector_csrs = if (!usingVector) LinkedHashMap() else LinkedHashMap[Int,Bits](
- CSRs.vstart -> reg_vstart.get,
- CSRs.vtype -> reg_vconfig.get.vtype.asUInt,
- CSRs.vl -> reg_vconfig.get.vl,
- CSRs.vlenb -> (vLen / 8).U)
+// val read_fcsr = Cat(reg_frm, reg_fflags) | (reg_vxsat.getOrElse(0.U) << 8) | (reg_vxrm.getOrElse(0.U) << 9)
+// val fp_csrs = LinkedHashMap[Int,Bits]() ++
+// usingFPU.option(CSRs.fflags -> reg_fflags) ++
+// usingFPU.option(CSRs.frm -> reg_frm) ++
+// (usingFPU || usingVector).option(CSRs.fcsr -> read_fcsr) ++
+// reg_vxsat.map(CSRs.vxsat -> _) ++
+// reg_vxrm.map(CSRs.vxrm -> _)
+//
+// val vector_csrs = if (!usingVector) LinkedHashMap() else LinkedHashMap[Int,Bits](
+// CSRs.vstart -> reg_vstart.get,
+// CSRs.vtype -> reg_vconfig.get.vtype.asUInt,
+// CSRs.vl -> reg_vconfig.get.vl,
+// CSRs.vlenb -> (vLen / 8).U)
+
+//add for VPU
+ val fp_csrs = LinkedHashMap[Int,Bits](
+ CSRs.fflags -> reg_fflags,
+ CSRs.frm -> reg_frm,
+ CSRs.fcsr -> Cat(reg_vxrm, reg_vxsat, reg_frm, reg_fflags)) //vxrm, vxsat are mirrored in the upper bits of fcsr
+
+ val vp_csrs = LinkedHashMap[Int,Bits](
+ CSRs.vstart -> reg_vstart,
+ CSRs.vxsat -> reg_vxsat,
+ CSRs.vxrm -> reg_vxrm,
+ CSRs.vl -> reg_vl,
+ CSRs.vtype -> reg_vtype,
+ CSRs.vlenb -> (VLEN/8).U)
+//add for VPU
read_mapping ++= debug_csrs
- read_mapping ++= fp_csrs
- read_mapping ++= vector_csrs
+// read_mapping ++= fp_csrs
+// read_mapping ++= vector_csrs
+//add for VPU
+ if (usingFPU || usingVPU)
+ read_mapping ++= fp_csrs
+
+ if (usingVPU)
+ read_mapping ++= vp_csrs
+//add for VPU
if (coreParams.haveBasicCounters) {
read_mapping += CSRs.mcycle -> reg_cycle
@@ -601,13 +645,16 @@ class CSRFile(
io_dec.fp_illegal := io.status.fs === 0 || !reg_misa('f'-'a')
io_dec.vector_illegal := io.status.vs === 0 || !reg_misa('v'-'a')
io_dec.fp_csr := decodeFast(fp_csrs.keys.toList)
+// io_dec.vp_csr := Bool(usingVPU) && DecodeLogic(io_dec.csr, vp_csrs.keys.toList.map(_.U), (read_mapping -- vp_csrs.keys.toList).keys.toList.map(_.U)) //add for VPU???
+ io_dec.vp_csr := decodeFast(vp_csrs.keys.toList)
io_dec.rocc_illegal := io.status.xs === 0 || !reg_misa('x'-'a')
io_dec.read_illegal := reg_mstatus.prv < io_dec.csr(9,8) ||
!decodeAny(read_mapping) ||
io_dec.csr === CSRs.satp && !allow_sfence_vma ||
(io_dec.csr.inRange(CSR.firstCtr, CSR.firstCtr + CSR.nCtr) || io_dec.csr.inRange(CSR.firstCtrH, CSR.firstCtrH + CSR.nCtr)) && !allow_counter ||
decodeFast(debug_csrs.keys.toList) && !reg_debug ||
- decodeFast(vector_csrs.keys.toList) && io_dec.vector_illegal ||
+// decodeFast(vector_csrs.keys.toList) && io_dec.vector_illegal ||
+ io_dec.vp_csr && io_dec.vector_illegal || //add for VPU
io_dec.fp_csr && io_dec.fp_illegal
io_dec.write_illegal := io_dec.csr(11,10).andR
io_dec.write_flush := !(io_dec.csr >= CSRs.mscratch && io_dec.csr <= CSRs.mtval || io_dec.csr >= CSRs.sscratch && io_dec.csr <= CSRs.stval)
@@ -761,13 +808,13 @@ class CSRFile(
}
}})
- val set_vs_dirty = Wire(init = io.vector.map(_.set_vs_dirty).getOrElse(false.B))
- io.vector.foreach { vio =>
- when (set_vs_dirty) {
- assert(reg_mstatus.vs > 0)
- reg_mstatus.vs := 3
- }
- }
+// val set_vs_dirty = Wire(init = io.vector.map(_.set_vs_dirty).getOrElse(false.B))
+// io.vector.foreach { vio =>
+// when (set_vs_dirty) {
+// assert(reg_mstatus.vs > 0)
+// reg_mstatus.vs := 3
+// }
+// }
val set_fs_dirty = Wire(init = io.set_fs_dirty.getOrElse(false.B))
if (coreParams.haveFSDirty) {
@@ -783,13 +830,34 @@ class CSRFile(
set_fs_dirty := true
}
- io.vector.foreach { vio =>
- when (vio.set_vxsat) {
- reg_vxsat.get := true
- set_fs_dirty := true
+// io.vector.foreach { vio =>
+// when (vio.set_vxsat) {
+// reg_vxsat.get := true
+// set_fs_dirty := true
+// }
+// }
+
+
+ //add for VPU
+ val set_vs_dirty = Wire(init = io.set_vs_dirty.getOrElse(false.B))
+ if (coreParams.haveVSDirty) {
+ when (set_vs_dirty) {
+ assert(reg_mstatus.vs > 0)
+ reg_mstatus.vs := 3
}
}
+ io.vcsr_vxrm := reg_vxrm
+ when (io.vcsr_vxsat.valid) {
+ reg_vxsat := reg_vxsat | io.vcsr_vxsat.bits
+ set_vs_dirty := true
+ set_fs_dirty := true
+ }
+ reg_vstart := io.vcsr_vstart
+ reg_vl := io.vcsr_vl
+ reg_vtype := io.vcsr_vtype
+ //add for VPU
+
val csr_wen = io.rw.cmd.isOneOf(CSR.S, CSR.C, CSR.W)
io.csrw_counter := Mux(coreParams.haveBasicCounters && csr_wen && (io.rw.addr.inRange(CSRs.mcycle, CSRs.mcycle + CSR.nCtr) || io.rw.addr.inRange(CSRs.mcycleh, CSRs.mcycleh + CSR.nCtr)), UIntToOH(io.rw.addr(log2Ceil(CSR.nCtr+nPerfCounters)-1, 0)), 0.U)
when (csr_wen) {
@@ -813,8 +881,10 @@ class CSRFile(
}
}
- if (usingVM || usingFPU || usingVector) reg_mstatus.fs := formFS(new_mstatus.fs)
- reg_mstatus.vs := formVS(new_mstatus.vs)
+// if (usingVM || usingFPU || usingVector) reg_mstatus.fs := formFS(new_mstatus.fs)
+// reg_mstatus.vs := formVS(new_mstatus.vs)
+ if (usingVM || usingFPU || usingVPU) reg_mstatus.fs := formFS(new_mstatus.fs) //add for VPU
+ if (usingVPU) reg_mstatus.vs := formVS(new_mstatus.vs) //add for VPU
if (usingRoCC) reg_mstatus.xs := Fill(2, new_mstatus.xs.orR)
}
when (decoded_addr(CSRs.misa)) {
@@ -855,19 +925,41 @@ class CSRFile(
writeCounter(CSRs.minstret, reg_instret, wdata)
}
- if (usingFPU) {
+// if (usingFPU) {
+// when (decoded_addr(CSRs.fflags)) { set_fs_dirty := true; reg_fflags := wdata }
+// when (decoded_addr(CSRs.frm)) { set_fs_dirty := true; reg_frm := wdata }
+// }
+// if (usingFPU || usingVector) {
+// when (decoded_addr(CSRs.fcsr)) {
+// set_fs_dirty := true
+// reg_fflags := wdata
+// reg_frm := wdata >> reg_fflags.getWidth
+// reg_vxsat.foreach(_ := wdata >> 8)
+// reg_vxrm.foreach(_ := wdata >> 9)
+// }
+// }
+
+//add for VPU
+ if (usingFPU && !usingVPU) {
when (decoded_addr(CSRs.fflags)) { set_fs_dirty := true; reg_fflags := wdata }
when (decoded_addr(CSRs.frm)) { set_fs_dirty := true; reg_frm := wdata }
- }
- if (usingFPU || usingVector) {
- when (decoded_addr(CSRs.fcsr)) {
- set_fs_dirty := true
- reg_fflags := wdata
- reg_frm := wdata >> reg_fflags.getWidth
- reg_vxsat.foreach(_ := wdata >> 8)
- reg_vxrm.foreach(_ := wdata >> 9)
- }
- }
+ when (decoded_addr(CSRs.fcsr)) { set_fs_dirty := true; reg_fflags := wdata; reg_frm := wdata >> reg_fflags.getWidth }
+ }
+
+ if (usingVPU) {
+ when (decoded_addr(CSRs.vxsat)) { set_fs_dirty := true; reg_vxsat := wdata }
+ when (decoded_addr(CSRs.vxrm)) { set_fs_dirty := true; reg_vxrm := wdata }
+ when (decoded_addr(CSRs.fflags)) { set_fs_dirty := true; reg_fflags := wdata }
+ when (decoded_addr(CSRs.frm)) { set_fs_dirty := true; reg_frm := wdata }
+ when (decoded_addr(CSRs.fcsr)) { set_fs_dirty := true;
+ reg_fflags := wdata;
+ reg_frm := wdata >> reg_fflags.getWidth;
+ reg_vxsat := wdata >> (reg_fflags.getWidth + reg_frm.getWidth);
+ reg_vxrm := wdata >> (reg_fflags.getWidth + reg_frm.getWidth + reg_vxsat.getWidth)
+ }
+ }
+//add for VPU
+
if (usingDebug) {
when (decoded_addr(CSRs.dcsr)) {
val new_dcsr = new DCSR().fromBits(wdata)
@@ -962,32 +1054,32 @@ class CSRFile(
io.wen := true
}
}
- if (usingVector) {
- when (decoded_addr(CSRs.vstart)) { set_vs_dirty := true; reg_vstart.get := wdata }
- when (decoded_addr(CSRs.vxrm)) { set_fs_dirty := true; reg_vxrm.get := wdata }
- when (decoded_addr(CSRs.vxsat)) { set_fs_dirty := true; reg_vxsat.get := wdata }
- }
+// if (usingVector) {
+// when (decoded_addr(CSRs.vstart)) { set_vs_dirty := true; reg_vstart.get := wdata }
+// when (decoded_addr(CSRs.vxrm)) { set_fs_dirty := true; reg_vxrm.get := wdata }
+// when (decoded_addr(CSRs.vxsat)) { set_fs_dirty := true; reg_vxsat.get := wdata }
+// }
}
- io.vector.map { vio =>
- when (vio.set_vconfig.valid) {
- // user of CSRFile is responsible for set_vs_dirty in this case
- assert(vio.set_vconfig.bits.vl <= vio.set_vconfig.bits.vtype.vlMax)
- reg_vconfig.get := vio.set_vconfig.bits
- }
- when (vio.set_vstart.valid) {
- set_vs_dirty := true
- reg_vstart.get := vio.set_vstart.bits
- }
- vio.vstart := reg_vstart.get
- vio.vconfig := reg_vconfig.get
- vio.vxrm := reg_vxrm.get
-
- when (reset.toBool) {
- reg_vconfig.get.vtype := 0.U.asTypeOf(new VType)
- reg_vconfig.get.vtype.vill := true
- }
- }
+// io.vector.map { vio =>
+// when (vio.set_vconfig.valid) {
+// // user of CSRFile is responsible for set_vs_dirty in this case
+// assert(vio.set_vconfig.bits.vl <= vio.set_vconfig.bits.vtype.vlMax)
+// reg_vconfig.get := vio.set_vconfig.bits
+// }
+// when (vio.set_vstart.valid) {
+// set_vs_dirty := true
+// reg_vstart.get := vio.set_vstart.bits
+// }
+// vio.vstart := reg_vstart.get
+// vio.vconfig := reg_vconfig.get
+// vio.vxrm := reg_vxrm.get
+//
+// when (reset.toBool) {
+// reg_vconfig.get.vtype := 0.U.asTypeOf(new VType)
+// reg_vconfig.get.vtype.vill := true
+// }
+// }
reg_satp.asid := 0
if (nBreakpoints <= 1) reg_tselect := 0
@@ -1067,5 +1159,6 @@ class CSRFile(
def formTVec(x: UInt) = x andNot Mux(x(0), ((((BigInt(1) << mtvecInterruptAlign) - 1) << mtvecBaseAlign) | 2).U, 2)
def isaStringToMask(s: String) = s.map(x => 1 << (x - 'A')).foldLeft(0)(_|_)
def formFS(fs: UInt) = if (coreParams.haveFSDirty) fs else Fill(2, fs.orR)
- def formVS(vs: UInt) = if (usingVector) vs else 0.U
+// def formVS(vs: UInt) = if (usingVector) vs else 0.U
+ def formVS(vs: UInt) = if (coreParams.haveVSDirty) vs else Fill(2, vs.orR) //add for VPU
}
diff --git a/src/main/scala/rocket/IDecode.scala b/src/main/scala/rocket/IDecode.scala
index 94594aec2..2438ea07d 100644
--- a/src/main/scala/rocket/IDecode.scala
+++ b/src/main/scala/rocket/IDecode.scala
@@ -46,23 +46,29 @@ class IntCtrlSigs extends Bundle {
val fence = Bool()
val amo = Bool()
val dp = Bool()
+ //add for VPU
+ val vp = Bool()
+ val vp_fp = Bool()
+ val vp_mem = Bool()
+ //add for VPU
def default: List[BitPat] =
// jal renf1 fence.i
// val | jalr | renf2 |
// | fp_val| | renx2 | | renf3 |
// | | rocc| | | renx1 s_alu1 mem_val | | | wfd |
- // | | | br| | | | s_alu2 | imm dw alu | mem_cmd | | | | mul |
- // | | | | | | | | | | | | | | | | | | | | div | fence
- // | | | | | | | | | | | | | | | | | | | | | wxd | | amo
- // | | | | | | | | scie | | | | | | | | | | | | | | | | dp
- List(N,X,X,X,X,X,X,X,X,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, X,X,X,X,X,X,X,CSR.X,X,X,X,X)
+ // | | | br| | | | s_alu2 | imm dw alu | mem_cmd | | | | mul | vp
+ // | | | | | | | | | | | | | | | | | | | | div | fence | vp_fp
+ // | | | | | | | | | | | | | | | | | | | | | wxd | | amo | | vp_mem
+ // | | | | | | | | scie | | | | | | | | | | | | | | | | dp| | |
+ List(N,X,X,X,X,X,X,X,X,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, X,X,X,X,X,X,X,CSR.X,X,X,X,X,X,X,X)
def decode(inst: UInt, table: Iterable[(BitPat, List[BitPat])]) = {
val decoder = DecodeLogic(inst, default, table)
val sigs = Seq(legal, fp, rocc, branch, jal, jalr, rxs2, rxs1, scie, sel_alu2,
sel_alu1, sel_imm, alu_dw, alu_fn, mem, mem_cmd,
- rfs1, rfs2, rfs3, wfd, mul, div, wxd, csr, fence_i, fence, amo, dp)
+ rfs1, rfs2, rfs3, wfd, mul, div, wxd, csr, fence_i, fence, amo, dp,
+ vp, vp_fp, vp_mem)
sigs zip decoder map {case(s,d) => s := d}
this
}
@@ -71,57 +77,57 @@ class IntCtrlSigs extends Bundle {
class IDecode(implicit val p: Parameters) extends DecodeConstants
{
val table: Array[(BitPat, List[BitPat])] = Array(
- BNE-> List(Y,N,N,Y,N,N,Y,Y,N,A2_RS2, A1_RS1, IMM_SB,DW_X, FN_SNE, N,M_X, N,N,N,N,N,N,N,CSR.N,N,N,N,N),
- BEQ-> List(Y,N,N,Y,N,N,Y,Y,N,A2_RS2, A1_RS1, IMM_SB,DW_X, FN_SEQ, N,M_X, N,N,N,N,N,N,N,CSR.N,N,N,N,N),
- BLT-> List(Y,N,N,Y,N,N,Y,Y,N,A2_RS2, A1_RS1, IMM_SB,DW_X, FN_SLT, N,M_X, N,N,N,N,N,N,N,CSR.N,N,N,N,N),
- BLTU-> List(Y,N,N,Y,N,N,Y,Y,N,A2_RS2, A1_RS1, IMM_SB,DW_X, FN_SLTU, N,M_X, N,N,N,N,N,N,N,CSR.N,N,N,N,N),
- BGE-> List(Y,N,N,Y,N,N,Y,Y,N,A2_RS2, A1_RS1, IMM_SB,DW_X, FN_SGE, N,M_X, N,N,N,N,N,N,N,CSR.N,N,N,N,N),
- BGEU-> List(Y,N,N,Y,N,N,Y,Y,N,A2_RS2, A1_RS1, IMM_SB,DW_X, FN_SGEU, N,M_X, N,N,N,N,N,N,N,CSR.N,N,N,N,N),
-
- JAL-> List(Y,N,N,N,Y,N,N,N,N,A2_SIZE,A1_PC, IMM_UJ,DW_XPR,FN_ADD, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
- JALR-> List(Y,N,N,N,N,Y,N,Y,N,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_ADD, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
- AUIPC-> List(Y,N,N,N,N,N,N,N,N,A2_IMM, A1_PC, IMM_U, DW_XPR,FN_ADD, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
-
- LB-> List(Y,N,N,N,N,N,N,Y,N,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_ADD, Y,M_XRD, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
- LH-> List(Y,N,N,N,N,N,N,Y,N,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_ADD, Y,M_XRD, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
- LW-> List(Y,N,N,N,N,N,N,Y,N,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_ADD, Y,M_XRD, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
- LBU-> List(Y,N,N,N,N,N,N,Y,N,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_ADD, Y,M_XRD, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
- LHU-> List(Y,N,N,N,N,N,N,Y,N,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_ADD, Y,M_XRD, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
- SB-> List(Y,N,N,N,N,N,Y,Y,N,A2_IMM, A1_RS1, IMM_S, DW_XPR,FN_ADD, Y,M_XWR, N,N,N,N,N,N,N,CSR.N,N,N,N,N),
- SH-> List(Y,N,N,N,N,N,Y,Y,N,A2_IMM, A1_RS1, IMM_S, DW_XPR,FN_ADD, Y,M_XWR, N,N,N,N,N,N,N,CSR.N,N,N,N,N),
- SW-> List(Y,N,N,N,N,N,Y,Y,N,A2_IMM, A1_RS1, IMM_S, DW_XPR,FN_ADD, Y,M_XWR, N,N,N,N,N,N,N,CSR.N,N,N,N,N),
-
- LUI-> List(Y,N,N,N,N,N,N,N,N,A2_IMM, A1_ZERO,IMM_U, DW_XPR,FN_ADD, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
- ADDI-> List(Y,N,N,N,N,N,N,Y,N,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_ADD, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
- SLTI -> List(Y,N,N,N,N,N,N,Y,N,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_SLT, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
- SLTIU-> List(Y,N,N,N,N,N,N,Y,N,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_SLTU, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
- ANDI-> List(Y,N,N,N,N,N,N,Y,N,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_AND, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
- ORI-> List(Y,N,N,N,N,N,N,Y,N,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_OR, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
- XORI-> List(Y,N,N,N,N,N,N,Y,N,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_XOR, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
- ADD-> List(Y,N,N,N,N,N,Y,Y,N,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
- SUB-> List(Y,N,N,N,N,N,Y,Y,N,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_SUB, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
- SLT-> List(Y,N,N,N,N,N,Y,Y,N,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_SLT, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
- SLTU-> List(Y,N,N,N,N,N,Y,Y,N,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_SLTU, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
- AND-> List(Y,N,N,N,N,N,Y,Y,N,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_AND, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
- OR-> List(Y,N,N,N,N,N,Y,Y,N,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_OR, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
- XOR-> List(Y,N,N,N,N,N,Y,Y,N,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_XOR, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
- SLL-> List(Y,N,N,N,N,N,Y,Y,N,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_SL, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
- SRL-> List(Y,N,N,N,N,N,Y,Y,N,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_SR, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
- SRA-> List(Y,N,N,N,N,N,Y,Y,N,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_SRA, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
-
- FENCE-> List(Y,N,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, N,N,N,N,N,N,N,CSR.N,N,Y,N,N),
-
- SCALL-> List(Y,N,N,N,N,N,N,X,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, N,N,N,N,N,N,N,CSR.I,N,N,N,N),
- SBREAK-> List(Y,N,N,N,N,N,N,X,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, N,N,N,N,N,N,N,CSR.I,N,N,N,N),
- MRET-> List(Y,N,N,N,N,N,N,X,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, N,N,N,N,N,N,N,CSR.I,N,N,N,N),
- WFI-> List(Y,N,N,N,N,N,N,X,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, N,N,N,N,N,N,N,CSR.I,N,N,N,N),
- CEASE-> List(Y,N,N,N,N,N,N,X,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, N,N,N,N,N,N,N,CSR.I,N,N,N,N),
- CSRRW-> List(Y,N,N,N,N,N,N,Y,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, N,N,N,N,N,N,Y,CSR.W,N,N,N,N),
- CSRRS-> List(Y,N,N,N,N,N,N,Y,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, N,N,N,N,N,N,Y,CSR.S,N,N,N,N),
- CSRRC-> List(Y,N,N,N,N,N,N,Y,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, N,N,N,N,N,N,Y,CSR.C,N,N,N,N),
- CSRRWI-> List(Y,N,N,N,N,N,N,N,N,A2_IMM, A1_ZERO,IMM_Z, DW_XPR,FN_ADD, N,M_X, N,N,N,N,N,N,Y,CSR.W,N,N,N,N),
- CSRRSI-> List(Y,N,N,N,N,N,N,N,N,A2_IMM, A1_ZERO,IMM_Z, DW_XPR,FN_ADD, N,M_X, N,N,N,N,N,N,Y,CSR.S,N,N,N,N),
- CSRRCI-> List(Y,N,N,N,N,N,N,N,N,A2_IMM, A1_ZERO,IMM_Z, DW_XPR,FN_ADD, N,M_X, N,N,N,N,N,N,Y,CSR.C,N,N,N,N))
+ BNE-> List(Y,N,N,Y,N,N,Y,Y,N,A2_RS2, A1_RS1, IMM_SB,DW_X, FN_SNE, N,M_X, N,N,N,N,N,N,N,CSR.N,N,N,N,N,N,N,N),
+ BEQ-> List(Y,N,N,Y,N,N,Y,Y,N,A2_RS2, A1_RS1, IMM_SB,DW_X, FN_SEQ, N,M_X, N,N,N,N,N,N,N,CSR.N,N,N,N,N,N,N,N),
+ BLT-> List(Y,N,N,Y,N,N,Y,Y,N,A2_RS2, A1_RS1, IMM_SB,DW_X, FN_SLT, N,M_X, N,N,N,N,N,N,N,CSR.N,N,N,N,N,N,N,N),
+ BLTU-> List(Y,N,N,Y,N,N,Y,Y,N,A2_RS2, A1_RS1, IMM_SB,DW_X, FN_SLTU, N,M_X, N,N,N,N,N,N,N,CSR.N,N,N,N,N,N,N,N),
+ BGE-> List(Y,N,N,Y,N,N,Y,Y,N,A2_RS2, A1_RS1, IMM_SB,DW_X, FN_SGE, N,M_X, N,N,N,N,N,N,N,CSR.N,N,N,N,N,N,N,N),
+ BGEU-> List(Y,N,N,Y,N,N,Y,Y,N,A2_RS2, A1_RS1, IMM_SB,DW_X, FN_SGEU, N,M_X, N,N,N,N,N,N,N,CSR.N,N,N,N,N,N,N,N),
+
+ JAL-> List(Y,N,N,N,Y,N,N,N,N,A2_SIZE,A1_PC, IMM_UJ,DW_XPR,FN_ADD, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N,N,N,N),
+ JALR-> List(Y,N,N,N,N,Y,N,Y,N,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_ADD, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N,N,N,N),
+ AUIPC-> List(Y,N,N,N,N,N,N,N,N,A2_IMM, A1_PC, IMM_U, DW_XPR,FN_ADD, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N,N,N,N),
+
+ LB-> List(Y,N,N,N,N,N,N,Y,N,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_ADD, Y,M_XRD, N,N,N,N,N,N,Y,CSR.N,N,N,N,N,N,N,N),
+ LH-> List(Y,N,N,N,N,N,N,Y,N,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_ADD, Y,M_XRD, N,N,N,N,N,N,Y,CSR.N,N,N,N,N,N,N,N),
+ LW-> List(Y,N,N,N,N,N,N,Y,N,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_ADD, Y,M_XRD, N,N,N,N,N,N,Y,CSR.N,N,N,N,N,N,N,N),
+ LBU-> List(Y,N,N,N,N,N,N,Y,N,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_ADD, Y,M_XRD, N,N,N,N,N,N,Y,CSR.N,N,N,N,N,N,N,N),
+ LHU-> List(Y,N,N,N,N,N,N,Y,N,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_ADD, Y,M_XRD, N,N,N,N,N,N,Y,CSR.N,N,N,N,N,N,N,N),
+ SB-> List(Y,N,N,N,N,N,Y,Y,N,A2_IMM, A1_RS1, IMM_S, DW_XPR,FN_ADD, Y,M_XWR, N,N,N,N,N,N,N,CSR.N,N,N,N,N,N,N,N),
+ SH-> List(Y,N,N,N,N,N,Y,Y,N,A2_IMM, A1_RS1, IMM_S, DW_XPR,FN_ADD, Y,M_XWR, N,N,N,N,N,N,N,CSR.N,N,N,N,N,N,N,N),
+ SW-> List(Y,N,N,N,N,N,Y,Y,N,A2_IMM, A1_RS1, IMM_S, DW_XPR,FN_ADD, Y,M_XWR, N,N,N,N,N,N,N,CSR.N,N,N,N,N,N,N,N),
+
+ LUI-> List(Y,N,N,N,N,N,N,N,N,A2_IMM, A1_ZERO,IMM_U, DW_XPR,FN_ADD, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N,N,N,N),
+ ADDI-> List(Y,N,N,N,N,N,N,Y,N,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_ADD, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N,N,N,N),
+ SLTI -> List(Y,N,N,N,N,N,N,Y,N,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_SLT, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N,N,N,N),
+ SLTIU-> List(Y,N,N,N,N,N,N,Y,N,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_SLTU, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N,N,N,N),
+ ANDI-> List(Y,N,N,N,N,N,N,Y,N,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_AND, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N,N,N,N),
+ ORI-> List(Y,N,N,N,N,N,N,Y,N,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_OR, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N,N,N,N),
+ XORI-> List(Y,N,N,N,N,N,N,Y,N,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_XOR, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N,N,N,N),
+ ADD-> List(Y,N,N,N,N,N,Y,Y,N,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N,N,N,N),
+ SUB-> List(Y,N,N,N,N,N,Y,Y,N,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_SUB, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N,N,N,N),
+ SLT-> List(Y,N,N,N,N,N,Y,Y,N,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_SLT, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N,N,N,N),
+ SLTU-> List(Y,N,N,N,N,N,Y,Y,N,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_SLTU, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N,N,N,N),
+ AND-> List(Y,N,N,N,N,N,Y,Y,N,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_AND, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N,N,N,N),
+ OR-> List(Y,N,N,N,N,N,Y,Y,N,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_OR, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N,N,N,N),
+ XOR-> List(Y,N,N,N,N,N,Y,Y,N,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_XOR, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N,N,N,N),
+ SLL-> List(Y,N,N,N,N,N,Y,Y,N,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_SL, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N,N,N,N),
+ SRL-> List(Y,N,N,N,N,N,Y,Y,N,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_SR, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N,N,N,N),
+ SRA-> List(Y,N,N,N,N,N,Y,Y,N,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_SRA, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N,N,N,N),
+
+ FENCE-> List(Y,N,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, N,N,N,N,N,N,N,CSR.N,N,Y,N,N,N,N,N),
+
+ SCALL-> List(Y,N,N,N,N,N,N,X,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, N,N,N,N,N,N,N,CSR.I,N,N,N,N,N,N,N),
+ SBREAK-> List(Y,N,N,N,N,N,N,X,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, N,N,N,N,N,N,N,CSR.I,N,N,N,N,N,N,N),
+ MRET-> List(Y,N,N,N,N,N,N,X,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, N,N,N,N,N,N,N,CSR.I,N,N,N,N,N,N,N),
+ WFI-> List(Y,N,N,N,N,N,N,X,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, N,N,N,N,N,N,N,CSR.I,N,N,N,N,N,N,N),
+ CEASE-> List(Y,N,N,N,N,N,N,X,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, N,N,N,N,N,N,N,CSR.I,N,N,N,N,N,N,N),
+ CSRRW-> List(Y,N,N,N,N,N,N,Y,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, N,N,N,N,N,N,Y,CSR.W,N,N,N,N,N,N,N),
+ CSRRS-> List(Y,N,N,N,N,N,N,Y,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, N,N,N,N,N,N,Y,CSR.S,N,N,N,N,N,N,N),
+ CSRRC-> List(Y,N,N,N,N,N,N,Y,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, N,N,N,N,N,N,Y,CSR.C,N,N,N,N,N,N,N),
+ CSRRWI-> List(Y,N,N,N,N,N,N,N,N,A2_IMM, A1_ZERO,IMM_Z, DW_XPR,FN_ADD, N,M_X, N,N,N,N,N,N,Y,CSR.W,N,N,N,N,N,N,N),
+ CSRRSI-> List(Y,N,N,N,N,N,N,N,N,A2_IMM, A1_ZERO,IMM_Z, DW_XPR,FN_ADD, N,M_X, N,N,N,N,N,N,Y,CSR.S,N,N,N,N,N,N,N),
+ CSRRCI-> List(Y,N,N,N,N,N,N,N,N,A2_IMM, A1_ZERO,IMM_Z, DW_XPR,FN_ADD, N,M_X, N,N,N,N,N,N,Y,CSR.C,N,N,N,N,N,N,N))
}
class FenceIDecode(flushDCache: Boolean)(implicit val p: Parameters) extends DecodeConstants
@@ -129,7 +135,7 @@ class FenceIDecode(flushDCache: Boolean)(implicit val p: Parameters) extends Dec
private val (v, cmd) = if (flushDCache) (Y, BitPat(M_FLUSH_ALL)) else (N, M_X)
val table: Array[(BitPat, List[BitPat])] = Array(
- FENCE_I-> List(Y,N,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, v,cmd, N,N,N,N,N,N,N,CSR.N,Y,Y,N,N))
+ FENCE_I-> List(Y,N,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, v,cmd, N,N,N,N,N,N,N,CSR.N,Y,Y,N,N,N,N,N))
}
class CFlushDecode(supportsFlushLine: Boolean)(implicit val p: Parameters) extends DecodeConstants
@@ -138,52 +144,52 @@ class CFlushDecode(supportsFlushLine: Boolean)(implicit val p: Parameters) exten
val table: Array[(BitPat, List[BitPat])] = Array(
zapRs1(CFLUSH_D_L1)->
- List(Y,N,N,N,N,N,N,Y,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_FLUSH_ALL,N,N,N,N,N,N,N,CSR.I,N,N,N,N),
+ List(Y,N,N,N,N,N,N,Y,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_FLUSH_ALL,N,N,N,N,N,N,N,CSR.I,N,N,N,N,N,N,N),
zapRs1(CDISCARD_D_L1)->
- List(Y,N,N,N,N,N,N,Y,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_FLUSH_ALL,N,N,N,N,N,N,N,CSR.I,N,N,N,N))
+ List(Y,N,N,N,N,N,N,Y,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_FLUSH_ALL,N,N,N,N,N,N,N,CSR.I,N,N,N,N,N,N,N))
}
class SDecode(implicit val p: Parameters) extends DecodeConstants
{
val table: Array[(BitPat, List[BitPat])] = Array(
- SFENCE_VMA->List(Y,N,N,N,N,N,Y,Y,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_SFENCE, N,N,N,N,N,N,N,CSR.N,N,N,N,N),
- SRET-> List(Y,N,N,N,N,N,N,X,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, N,N,N,N,N,N,N,CSR.I,N,N,N,N))
+ SFENCE_VMA->List(Y,N,N,N,N,N,Y,Y,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_SFENCE, N,N,N,N,N,N,N,CSR.N,N,N,N,N,N,N,N),
+ SRET-> List(Y,N,N,N,N,N,N,X,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, N,N,N,N,N,N,N,CSR.I,N,N,N,N,N,N,N))
}
class DebugDecode(implicit val p: Parameters) extends DecodeConstants
{
val table: Array[(BitPat, List[BitPat])] = Array(
- DRET-> List(Y,N,N,N,N,N,N,X,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, N,N,N,N,N,N,N,CSR.I,N,N,N,N))
+ DRET-> List(Y,N,N,N,N,N,N,X,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, N,N,N,N,N,N,N,CSR.I,N,N,N,N,N,N,N))
}
class I32Decode(implicit val p: Parameters) extends DecodeConstants
{
val table: Array[(BitPat, List[BitPat])] = Array(
- SLLI_RV32-> List(Y,N,N,N,N,N,N,Y,N,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_SL, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
- SRLI_RV32-> List(Y,N,N,N,N,N,N,Y,N,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_SR, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
- SRAI_RV32-> List(Y,N,N,N,N,N,N,Y,N,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_SRA, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N))
+ SLLI_RV32-> List(Y,N,N,N,N,N,N,Y,N,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_SL, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N,N,N,N),
+ SRLI_RV32-> List(Y,N,N,N,N,N,N,Y,N,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_SR, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N,N,N,N),
+ SRAI_RV32-> List(Y,N,N,N,N,N,N,Y,N,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_SRA, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N,N,N,N))
}
class I64Decode(implicit val p: Parameters) extends DecodeConstants
{
val table: Array[(BitPat, List[BitPat])] = Array(
- LD-> List(Y,N,N,N,N,N,N,Y,N,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_ADD, Y,M_XRD, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
- LWU-> List(Y,N,N,N,N,N,N,Y,N,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_ADD, Y,M_XRD, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
- SD-> List(Y,N,N,N,N,N,Y,Y,N,A2_IMM, A1_RS1, IMM_S, DW_XPR,FN_ADD, Y,M_XWR, N,N,N,N,N,N,N,CSR.N,N,N,N,N),
-
- SLLI-> List(Y,N,N,N,N,N,N,Y,N,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_SL, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
- SRLI-> List(Y,N,N,N,N,N,N,Y,N,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_SR, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
- SRAI-> List(Y,N,N,N,N,N,N,Y,N,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_SRA, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
-
- ADDIW-> List(Y,N,N,N,N,N,N,Y,N,A2_IMM, A1_RS1, IMM_I, DW_32,FN_ADD, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
- SLLIW-> List(Y,N,N,N,N,N,N,Y,N,A2_IMM, A1_RS1, IMM_I, DW_32,FN_SL, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
- SRLIW-> List(Y,N,N,N,N,N,N,Y,N,A2_IMM, A1_RS1, IMM_I, DW_32,FN_SR, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
- SRAIW-> List(Y,N,N,N,N,N,N,Y,N,A2_IMM, A1_RS1, IMM_I, DW_32,FN_SRA, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
- ADDW-> List(Y,N,N,N,N,N,Y,Y,N,A2_RS2, A1_RS1, IMM_X, DW_32,FN_ADD, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
- SUBW-> List(Y,N,N,N,N,N,Y,Y,N,A2_RS2, A1_RS1, IMM_X, DW_32,FN_SUB, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
- SLLW-> List(Y,N,N,N,N,N,Y,Y,N,A2_RS2, A1_RS1, IMM_X, DW_32,FN_SL, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
- SRLW-> List(Y,N,N,N,N,N,Y,Y,N,A2_RS2, A1_RS1, IMM_X, DW_32,FN_SR, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
- SRAW-> List(Y,N,N,N,N,N,Y,Y,N,A2_RS2, A1_RS1, IMM_X, DW_32,FN_SRA, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N))
+ LD-> List(Y,N,N,N,N,N,N,Y,N,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_ADD, Y,M_XRD, N,N,N,N,N,N,Y,CSR.N,N,N,N,N,N,N,N),
+ LWU-> List(Y,N,N,N,N,N,N,Y,N,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_ADD, Y,M_XRD, N,N,N,N,N,N,Y,CSR.N,N,N,N,N,N,N,N),
+ SD-> List(Y,N,N,N,N,N,Y,Y,N,A2_IMM, A1_RS1, IMM_S, DW_XPR,FN_ADD, Y,M_XWR, N,N,N,N,N,N,N,CSR.N,N,N,N,N,N,N,N),
+
+ SLLI-> List(Y,N,N,N,N,N,N,Y,N,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_SL, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N,N,N,N),
+ SRLI-> List(Y,N,N,N,N,N,N,Y,N,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_SR, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N,N,N,N),
+ SRAI-> List(Y,N,N,N,N,N,N,Y,N,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_SRA, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N,N,N,N),
+
+ ADDIW-> List(Y,N,N,N,N,N,N,Y,N,A2_IMM, A1_RS1, IMM_I, DW_32,FN_ADD, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N,N,N,N),
+ SLLIW-> List(Y,N,N,N,N,N,N,Y,N,A2_IMM, A1_RS1, IMM_I, DW_32,FN_SL, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N,N,N,N),
+ SRLIW-> List(Y,N,N,N,N,N,N,Y,N,A2_IMM, A1_RS1, IMM_I, DW_32,FN_SR, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N,N,N,N),
+ SRAIW-> List(Y,N,N,N,N,N,N,Y,N,A2_IMM, A1_RS1, IMM_I, DW_32,FN_SRA, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N,N,N,N),
+ ADDW-> List(Y,N,N,N,N,N,Y,Y,N,A2_RS2, A1_RS1, IMM_X, DW_32,FN_ADD, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N,N,N,N),
+ SUBW-> List(Y,N,N,N,N,N,Y,Y,N,A2_RS2, A1_RS1, IMM_X, DW_32,FN_SUB, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N,N,N,N),
+ SLLW-> List(Y,N,N,N,N,N,Y,Y,N,A2_RS2, A1_RS1, IMM_X, DW_32,FN_SL, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N,N,N,N),
+ SRLW-> List(Y,N,N,N,N,N,Y,Y,N,A2_RS2, A1_RS1, IMM_X, DW_32,FN_SR, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N,N,N,N),
+ SRAW-> List(Y,N,N,N,N,N,Y,Y,N,A2_RS2, A1_RS1, IMM_X, DW_32,FN_SRA, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N,N,N,N))
}
class MDecode(pipelinedMul: Boolean)(implicit val p: Parameters) extends DecodeConstants
@@ -191,15 +197,15 @@ class MDecode(pipelinedMul: Boolean)(implicit val p: Parameters) extends DecodeC
val M = if (pipelinedMul) Y else N
val D = if (pipelinedMul) N else Y
val table: Array[(BitPat, List[BitPat])] = Array(
- MUL-> List(Y,N,N,N,N,N,Y,Y,N,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_MUL, N,M_X, N,N,N,N,M,D,Y,CSR.N,N,N,N,N),
- MULH-> List(Y,N,N,N,N,N,Y,Y,N,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_MULH, N,M_X, N,N,N,N,M,D,Y,CSR.N,N,N,N,N),
- MULHU-> List(Y,N,N,N,N,N,Y,Y,N,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_MULHU, N,M_X, N,N,N,N,M,D,Y,CSR.N,N,N,N,N),
- MULHSU-> List(Y,N,N,N,N,N,Y,Y,N,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_MULHSU,N,M_X, N,N,N,N,M,D,Y,CSR.N,N,N,N,N),
-
- DIV-> List(Y,N,N,N,N,N,Y,Y,N,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_DIV, N,M_X, N,N,N,N,N,Y,Y,CSR.N,N,N,N,N),
- DIVU-> List(Y,N,N,N,N,N,Y,Y,N,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_DIVU, N,M_X, N,N,N,N,N,Y,Y,CSR.N,N,N,N,N),
- REM-> List(Y,N,N,N,N,N,Y,Y,N,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_REM, N,M_X, N,N,N,N,N,Y,Y,CSR.N,N,N,N,N),
- REMU-> List(Y,N,N,N,N,N,Y,Y,N,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_REMU, N,M_X, N,N,N,N,N,Y,Y,CSR.N,N,N,N,N))
+ MUL-> List(Y,N,N,N,N,N,Y,Y,N,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_MUL, N,M_X, N,N,N,N,M,D,Y,CSR.N,N,N,N,N,N,N,N),
+ MULH-> List(Y,N,N,N,N,N,Y,Y,N,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_MULH, N,M_X, N,N,N,N,M,D,Y,CSR.N,N,N,N,N,N,N,N),
+ MULHU-> List(Y,N,N,N,N,N,Y,Y,N,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_MULHU, N,M_X, N,N,N,N,M,D,Y,CSR.N,N,N,N,N,N,N,N),
+ MULHSU-> List(Y,N,N,N,N,N,Y,Y,N,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_MULHSU,N,M_X, N,N,N,N,M,D,Y,CSR.N,N,N,N,N,N,N,N),
+
+ DIV-> List(Y,N,N,N,N,N,Y,Y,N,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_DIV, N,M_X, N,N,N,N,N,Y,Y,CSR.N,N,N,N,N,N,N,N),
+ DIVU-> List(Y,N,N,N,N,N,Y,Y,N,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_DIVU, N,M_X, N,N,N,N,N,Y,Y,CSR.N,N,N,N,N,N,N,N),
+ REM-> List(Y,N,N,N,N,N,Y,Y,N,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_REM, N,M_X, N,N,N,N,N,Y,Y,CSR.N,N,N,N,N,N,N,N),
+ REMU-> List(Y,N,N,N,N,N,Y,Y,N,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_REMU, N,M_X, N,N,N,N,N,Y,Y,CSR.N,N,N,N,N,N,N,N))
}
class M64Decode(pipelinedMul: Boolean)(implicit val p: Parameters) extends DecodeConstants
@@ -207,161 +213,307 @@ class M64Decode(pipelinedMul: Boolean)(implicit val p: Parameters) extends Decod
val M = if (pipelinedMul) Y else N
val D = if (pipelinedMul) N else Y
val table: Array[(BitPat, List[BitPat])] = Array(
- MULW-> List(Y,N,N,N,N,N,Y,Y,N,A2_RS2, A1_RS1, IMM_X, DW_32, FN_MUL, N,M_X, N,N,N,N,M,D,Y,CSR.N,N,N,N,N),
+ MULW-> List(Y,N,N,N,N,N,Y,Y,N,A2_RS2, A1_RS1, IMM_X, DW_32, FN_MUL, N,M_X, N,N,N,N,M,D,Y,CSR.N,N,N,N,N,N,N,N),
- DIVW-> List(Y,N,N,N,N,N,Y,Y,N,A2_RS2, A1_RS1, IMM_X, DW_32, FN_DIV, N,M_X, N,N,N,N,N,Y,Y,CSR.N,N,N,N,N),
- DIVUW-> List(Y,N,N,N,N,N,Y,Y,N,A2_RS2, A1_RS1, IMM_X, DW_32, FN_DIVU, N,M_X, N,N,N,N,N,Y,Y,CSR.N,N,N,N,N),
- REMW-> List(Y,N,N,N,N,N,Y,Y,N,A2_RS2, A1_RS1, IMM_X, DW_32, FN_REM, N,M_X, N,N,N,N,N,Y,Y,CSR.N,N,N,N,N),
- REMUW-> List(Y,N,N,N,N,N,Y,Y,N,A2_RS2, A1_RS1, IMM_X, DW_32, FN_REMU, N,M_X, N,N,N,N,N,Y,Y,CSR.N,N,N,N,N))
+ DIVW-> List(Y,N,N,N,N,N,Y,Y,N,A2_RS2, A1_RS1, IMM_X, DW_32, FN_DIV, N,M_X, N,N,N,N,N,Y,Y,CSR.N,N,N,N,N,N,N,N),
+ DIVUW-> List(Y,N,N,N,N,N,Y,Y,N,A2_RS2, A1_RS1, IMM_X, DW_32, FN_DIVU, N,M_X, N,N,N,N,N,Y,Y,CSR.N,N,N,N,N,N,N,N),
+ REMW-> List(Y,N,N,N,N,N,Y,Y,N,A2_RS2, A1_RS1, IMM_X, DW_32, FN_REM, N,M_X, N,N,N,N,N,Y,Y,CSR.N,N,N,N,N,N,N,N),
+ REMUW-> List(Y,N,N,N,N,N,Y,Y,N,A2_RS2, A1_RS1, IMM_X, DW_32, FN_REMU, N,M_X, N,N,N,N,N,Y,Y,CSR.N,N,N,N,N,N,N,N))
}
class ADecode(implicit val p: Parameters) extends DecodeConstants
{
val table: Array[(BitPat, List[BitPat])] = Array(
- AMOADD_W-> List(Y,N,N,N,N,N,Y,Y,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_ADD, N,N,N,N,N,N,Y,CSR.N,N,N,Y,N),
- AMOXOR_W-> List(Y,N,N,N,N,N,Y,Y,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_XOR, N,N,N,N,N,N,Y,CSR.N,N,N,Y,N),
- AMOSWAP_W-> List(Y,N,N,N,N,N,Y,Y,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_SWAP, N,N,N,N,N,N,Y,CSR.N,N,N,Y,N),
- AMOAND_W-> List(Y,N,N,N,N,N,Y,Y,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_AND, N,N,N,N,N,N,Y,CSR.N,N,N,Y,N),
- AMOOR_W-> List(Y,N,N,N,N,N,Y,Y,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_OR, N,N,N,N,N,N,Y,CSR.N,N,N,Y,N),
- AMOMIN_W-> List(Y,N,N,N,N,N,Y,Y,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_MIN, N,N,N,N,N,N,Y,CSR.N,N,N,Y,N),
- AMOMINU_W-> List(Y,N,N,N,N,N,Y,Y,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_MINU, N,N,N,N,N,N,Y,CSR.N,N,N,Y,N),
- AMOMAX_W-> List(Y,N,N,N,N,N,Y,Y,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_MAX, N,N,N,N,N,N,Y,CSR.N,N,N,Y,N),
- AMOMAXU_W-> List(Y,N,N,N,N,N,Y,Y,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_MAXU, N,N,N,N,N,N,Y,CSR.N,N,N,Y,N),
-
- LR_W-> List(Y,N,N,N,N,N,Y,Y,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XLR, N,N,N,N,N,N,Y,CSR.N,N,N,Y,N),
- SC_W-> List(Y,N,N,N,N,N,Y,Y,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XSC, N,N,N,N,N,N,Y,CSR.N,N,N,Y,N))
+ AMOADD_W-> List(Y,N,N,N,N,N,Y,Y,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_ADD, N,N,N,N,N,N,Y,CSR.N,N,N,Y,N,N,N,N),
+ AMOXOR_W-> List(Y,N,N,N,N,N,Y,Y,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_XOR, N,N,N,N,N,N,Y,CSR.N,N,N,Y,N,N,N,N),
+ AMOSWAP_W-> List(Y,N,N,N,N,N,Y,Y,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_SWAP, N,N,N,N,N,N,Y,CSR.N,N,N,Y,N,N,N,N),
+ AMOAND_W-> List(Y,N,N,N,N,N,Y,Y,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_AND, N,N,N,N,N,N,Y,CSR.N,N,N,Y,N,N,N,N),
+ AMOOR_W-> List(Y,N,N,N,N,N,Y,Y,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_OR, N,N,N,N,N,N,Y,CSR.N,N,N,Y,N,N,N,N),
+ AMOMIN_W-> List(Y,N,N,N,N,N,Y,Y,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_MIN, N,N,N,N,N,N,Y,CSR.N,N,N,Y,N,N,N,N),
+ AMOMINU_W-> List(Y,N,N,N,N,N,Y,Y,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_MINU, N,N,N,N,N,N,Y,CSR.N,N,N,Y,N,N,N,N),
+ AMOMAX_W-> List(Y,N,N,N,N,N,Y,Y,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_MAX, N,N,N,N,N,N,Y,CSR.N,N,N,Y,N,N,N,N),
+ AMOMAXU_W-> List(Y,N,N,N,N,N,Y,Y,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_MAXU, N,N,N,N,N,N,Y,CSR.N,N,N,Y,N,N,N,N),
+
+ LR_W-> List(Y,N,N,N,N,N,Y,Y,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XLR, N,N,N,N,N,N,Y,CSR.N,N,N,Y,N,N,N,N),
+ SC_W-> List(Y,N,N,N,N,N,Y,Y,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XSC, N,N,N,N,N,N,Y,CSR.N,N,N,Y,N,N,N,N))
}
class A64Decode(implicit val p: Parameters) extends DecodeConstants
{
val table: Array[(BitPat, List[BitPat])] = Array(
- AMOADD_D-> List(Y,N,N,N,N,N,Y,Y,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_ADD, N,N,N,N,N,N,Y,CSR.N,N,N,Y,N),
- AMOSWAP_D-> List(Y,N,N,N,N,N,Y,Y,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_SWAP, N,N,N,N,N,N,Y,CSR.N,N,N,Y,N),
- AMOXOR_D-> List(Y,N,N,N,N,N,Y,Y,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_XOR, N,N,N,N,N,N,Y,CSR.N,N,N,Y,N),
- AMOAND_D-> List(Y,N,N,N,N,N,Y,Y,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_AND, N,N,N,N,N,N,Y,CSR.N,N,N,Y,N),
- AMOOR_D-> List(Y,N,N,N,N,N,Y,Y,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_OR, N,N,N,N,N,N,Y,CSR.N,N,N,Y,N),
- AMOMIN_D-> List(Y,N,N,N,N,N,Y,Y,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_MIN, N,N,N,N,N,N,Y,CSR.N,N,N,Y,N),
- AMOMINU_D-> List(Y,N,N,N,N,N,Y,Y,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_MINU, N,N,N,N,N,N,Y,CSR.N,N,N,Y,N),
- AMOMAX_D-> List(Y,N,N,N,N,N,Y,Y,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_MAX, N,N,N,N,N,N,Y,CSR.N,N,N,Y,N),
- AMOMAXU_D-> List(Y,N,N,N,N,N,Y,Y,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_MAXU, N,N,N,N,N,N,Y,CSR.N,N,N,Y,N),
-
- LR_D-> List(Y,N,N,N,N,N,Y,Y,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XLR, N,N,N,N,N,N,Y,CSR.N,N,N,Y,N),
- SC_D-> List(Y,N,N,N,N,N,Y,Y,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XSC, N,N,N,N,N,N,Y,CSR.N,N,N,Y,N))
+ AMOADD_D-> List(Y,N,N,N,N,N,Y,Y,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_ADD, N,N,N,N,N,N,Y,CSR.N,N,N,Y,N,N,N,N),
+ AMOSWAP_D-> List(Y,N,N,N,N,N,Y,Y,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_SWAP, N,N,N,N,N,N,Y,CSR.N,N,N,Y,N,N,N,N),
+ AMOXOR_D-> List(Y,N,N,N,N,N,Y,Y,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_XOR, N,N,N,N,N,N,Y,CSR.N,N,N,Y,N,N,N,N),
+ AMOAND_D-> List(Y,N,N,N,N,N,Y,Y,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_AND, N,N,N,N,N,N,Y,CSR.N,N,N,Y,N,N,N,N),
+ AMOOR_D-> List(Y,N,N,N,N,N,Y,Y,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_OR, N,N,N,N,N,N,Y,CSR.N,N,N,Y,N,N,N,N),
+ AMOMIN_D-> List(Y,N,N,N,N,N,Y,Y,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_MIN, N,N,N,N,N,N,Y,CSR.N,N,N,Y,N,N,N,N),
+ AMOMINU_D-> List(Y,N,N,N,N,N,Y,Y,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_MINU, N,N,N,N,N,N,Y,CSR.N,N,N,Y,N,N,N,N),
+ AMOMAX_D-> List(Y,N,N,N,N,N,Y,Y,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_MAX, N,N,N,N,N,N,Y,CSR.N,N,N,Y,N,N,N,N),
+ AMOMAXU_D-> List(Y,N,N,N,N,N,Y,Y,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_MAXU, N,N,N,N,N,N,Y,CSR.N,N,N,Y,N,N,N,N),
+
+ LR_D-> List(Y,N,N,N,N,N,Y,Y,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XLR, N,N,N,N,N,N,Y,CSR.N,N,N,Y,N,N,N,N),
+ SC_D-> List(Y,N,N,N,N,N,Y,Y,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XSC, N,N,N,N,N,N,Y,CSR.N,N,N,Y,N,N,N,N))
}
class FDecode(implicit val p: Parameters) extends DecodeConstants
{
val table: Array[(BitPat, List[BitPat])] = Array(
- FSGNJ_S-> List(Y,Y,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, Y,Y,N,Y,N,N,N,CSR.N,N,N,N,N),
- FSGNJX_S-> List(Y,Y,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, Y,Y,N,Y,N,N,N,CSR.N,N,N,N,N),
- FSGNJN_S-> List(Y,Y,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, Y,Y,N,Y,N,N,N,CSR.N,N,N,N,N),
- FMIN_S-> List(Y,Y,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, Y,Y,N,Y,N,N,N,CSR.N,N,N,N,N),
- FMAX_S-> List(Y,Y,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, Y,Y,N,Y,N,N,N,CSR.N,N,N,N,N),
- FADD_S-> List(Y,Y,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, Y,Y,N,Y,N,N,N,CSR.N,N,N,N,N),
- FSUB_S-> List(Y,Y,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, Y,Y,N,Y,N,N,N,CSR.N,N,N,N,N),
- FMUL_S-> List(Y,Y,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, Y,Y,N,Y,N,N,N,CSR.N,N,N,N,N),
- FMADD_S-> List(Y,Y,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, Y,Y,Y,Y,N,N,N,CSR.N,N,N,N,N),
- FMSUB_S-> List(Y,Y,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, Y,Y,Y,Y,N,N,N,CSR.N,N,N,N,N),
- FNMADD_S-> List(Y,Y,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, Y,Y,Y,Y,N,N,N,CSR.N,N,N,N,N),
- FNMSUB_S-> List(Y,Y,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, Y,Y,Y,Y,N,N,N,CSR.N,N,N,N,N),
- FCLASS_S-> List(Y,Y,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, Y,N,N,N,N,N,Y,CSR.N,N,N,N,N),
- FMV_X_S-> List(Y,Y,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, Y,N,N,N,N,N,Y,CSR.N,N,N,N,N),
- FCVT_W_S-> List(Y,Y,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, Y,N,N,N,N,N,Y,CSR.N,N,N,N,N),
- FCVT_WU_S-> List(Y,Y,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, Y,N,N,N,N,N,Y,CSR.N,N,N,N,N),
- FEQ_S-> List(Y,Y,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, Y,Y,N,N,N,N,Y,CSR.N,N,N,N,N),
- FLT_S-> List(Y,Y,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, Y,Y,N,N,N,N,Y,CSR.N,N,N,N,N),
- FLE_S-> List(Y,Y,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, Y,Y,N,N,N,N,Y,CSR.N,N,N,N,N),
- FMV_S_X-> List(Y,Y,N,N,N,N,N,Y,N,A2_X, A1_RS1, IMM_X, DW_X, FN_X, N,M_X, N,N,N,Y,N,N,N,CSR.N,N,N,N,N),
- FCVT_S_W-> List(Y,Y,N,N,N,N,N,Y,N,A2_X, A1_RS1, IMM_X, DW_X, FN_X, N,M_X, N,N,N,Y,N,N,N,CSR.N,N,N,N,N),
- FCVT_S_WU-> List(Y,Y,N,N,N,N,N,Y,N,A2_X, A1_RS1, IMM_X, DW_X, FN_X, N,M_X, N,N,N,Y,N,N,N,CSR.N,N,N,N,N),
- FLW-> List(Y,Y,N,N,N,N,N,Y,N,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_ADD, Y,M_XRD, N,N,N,Y,N,N,N,CSR.N,N,N,N,N),
- FSW-> List(Y,Y,N,N,N,N,N,Y,N,A2_IMM, A1_RS1, IMM_S, DW_XPR,FN_ADD, Y,M_XWR, N,Y,N,N,N,N,N,CSR.N,N,N,N,N),
- FDIV_S-> List(Y,Y,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, Y,Y,N,Y,N,N,N,CSR.N,N,N,N,N),
- FSQRT_S-> List(Y,Y,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, Y,Y,N,Y,N,N,N,CSR.N,N,N,N,N))
+ FSGNJ_S-> List(Y,Y,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, Y,Y,N,Y,N,N,N,CSR.N,N,N,N,N,N,N,N),
+ FSGNJX_S-> List(Y,Y,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, Y,Y,N,Y,N,N,N,CSR.N,N,N,N,N,N,N,N),
+ FSGNJN_S-> List(Y,Y,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, Y,Y,N,Y,N,N,N,CSR.N,N,N,N,N,N,N,N),
+ FMIN_S-> List(Y,Y,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, Y,Y,N,Y,N,N,N,CSR.N,N,N,N,N,N,N,N),
+ FMAX_S-> List(Y,Y,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, Y,Y,N,Y,N,N,N,CSR.N,N,N,N,N,N,N,N),
+ FADD_S-> List(Y,Y,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, Y,Y,N,Y,N,N,N,CSR.N,N,N,N,N,N,N,N),
+ FSUB_S-> List(Y,Y,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, Y,Y,N,Y,N,N,N,CSR.N,N,N,N,N,N,N,N),
+ FMUL_S-> List(Y,Y,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, Y,Y,N,Y,N,N,N,CSR.N,N,N,N,N,N,N,N),
+ FMADD_S-> List(Y,Y,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, Y,Y,Y,Y,N,N,N,CSR.N,N,N,N,N,N,N,N),
+ FMSUB_S-> List(Y,Y,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, Y,Y,Y,Y,N,N,N,CSR.N,N,N,N,N,N,N,N),
+ FNMADD_S-> List(Y,Y,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, Y,Y,Y,Y,N,N,N,CSR.N,N,N,N,N,N,N,N),
+ FNMSUB_S-> List(Y,Y,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, Y,Y,Y,Y,N,N,N,CSR.N,N,N,N,N,N,N,N),
+ FCLASS_S-> List(Y,Y,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, Y,N,N,N,N,N,Y,CSR.N,N,N,N,N,N,N,N),
+ FMV_X_S-> List(Y,Y,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, Y,N,N,N,N,N,Y,CSR.N,N,N,N,N,N,N,N),
+ FCVT_W_S-> List(Y,Y,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, Y,N,N,N,N,N,Y,CSR.N,N,N,N,N,N,N,N),
+ FCVT_WU_S-> List(Y,Y,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, Y,N,N,N,N,N,Y,CSR.N,N,N,N,N,N,N,N),
+ FEQ_S-> List(Y,Y,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, Y,Y,N,N,N,N,Y,CSR.N,N,N,N,N,N,N,N),
+ FLT_S-> List(Y,Y,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, Y,Y,N,N,N,N,Y,CSR.N,N,N,N,N,N,N,N),
+ FLE_S-> List(Y,Y,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, Y,Y,N,N,N,N,Y,CSR.N,N,N,N,N,N,N,N),
+ FMV_S_X-> List(Y,Y,N,N,N,N,N,Y,N,A2_X, A1_RS1, IMM_X, DW_X, FN_X, N,M_X, N,N,N,Y,N,N,N,CSR.N,N,N,N,N,N,N,N),
+ FCVT_S_W-> List(Y,Y,N,N,N,N,N,Y,N,A2_X, A1_RS1, IMM_X, DW_X, FN_X, N,M_X, N,N,N,Y,N,N,N,CSR.N,N,N,N,N,N,N,N),
+ FCVT_S_WU-> List(Y,Y,N,N,N,N,N,Y,N,A2_X, A1_RS1, IMM_X, DW_X, FN_X, N,M_X, N,N,N,Y,N,N,N,CSR.N,N,N,N,N,N,N,N),
+ FLW-> List(Y,Y,N,N,N,N,N,Y,N,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_ADD, Y,M_XRD, N,N,N,Y,N,N,N,CSR.N,N,N,N,N,N,N,N),
+ FSW-> List(Y,Y,N,N,N,N,N,Y,N,A2_IMM, A1_RS1, IMM_S, DW_XPR,FN_ADD, Y,M_XWR, N,Y,N,N,N,N,N,CSR.N,N,N,N,N,N,N,N),
+ FDIV_S-> List(Y,Y,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, Y,Y,N,Y,N,N,N,CSR.N,N,N,N,N,N,N,N),
+ FSQRT_S-> List(Y,Y,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, Y,Y,N,Y,N,N,N,CSR.N,N,N,N,N,N,N,N))
}
class DDecode(implicit val p: Parameters) extends DecodeConstants
{
val table: Array[(BitPat, List[BitPat])] = Array(
- FCVT_S_D-> List(Y,Y,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, Y,N,N,Y,N,N,N,CSR.N,N,N,N,Y),
- FCVT_D_S-> List(Y,Y,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, Y,N,N,Y,N,N,N,CSR.N,N,N,N,Y),
- FSGNJ_D-> List(Y,Y,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, Y,Y,N,Y,N,N,N,CSR.N,N,N,N,Y),
- FSGNJX_D-> List(Y,Y,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, Y,Y,N,Y,N,N,N,CSR.N,N,N,N,Y),
- FSGNJN_D-> List(Y,Y,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, Y,Y,N,Y,N,N,N,CSR.N,N,N,N,Y),
- FMIN_D-> List(Y,Y,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, Y,Y,N,Y,N,N,N,CSR.N,N,N,N,Y),
- FMAX_D-> List(Y,Y,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, Y,Y,N,Y,N,N,N,CSR.N,N,N,N,Y),
- FADD_D-> List(Y,Y,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, Y,Y,N,Y,N,N,N,CSR.N,N,N,N,Y),
- FSUB_D-> List(Y,Y,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, Y,Y,N,Y,N,N,N,CSR.N,N,N,N,Y),
- FMUL_D-> List(Y,Y,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, Y,Y,N,Y,N,N,N,CSR.N,N,N,N,Y),
- FMADD_D-> List(Y,Y,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, Y,Y,Y,Y,N,N,N,CSR.N,N,N,N,Y),
- FMSUB_D-> List(Y,Y,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, Y,Y,Y,Y,N,N,N,CSR.N,N,N,N,Y),
- FNMADD_D-> List(Y,Y,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, Y,Y,Y,Y,N,N,N,CSR.N,N,N,N,Y),
- FNMSUB_D-> List(Y,Y,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, Y,Y,Y,Y,N,N,N,CSR.N,N,N,N,Y),
- FCLASS_D-> List(Y,Y,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, Y,N,N,N,N,N,Y,CSR.N,N,N,N,Y),
- FCVT_W_D-> List(Y,Y,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, Y,N,N,N,N,N,Y,CSR.N,N,N,N,Y),
- FCVT_WU_D-> List(Y,Y,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, Y,N,N,N,N,N,Y,CSR.N,N,N,N,Y),
- FEQ_D-> List(Y,Y,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, Y,Y,N,N,N,N,Y,CSR.N,N,N,N,Y),
- FLT_D-> List(Y,Y,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, Y,Y,N,N,N,N,Y,CSR.N,N,N,N,Y),
- FLE_D-> List(Y,Y,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, Y,Y,N,N,N,N,Y,CSR.N,N,N,N,Y),
- FCVT_D_W-> List(Y,Y,N,N,N,N,N,Y,N,A2_X, A1_RS1, IMM_X, DW_X, FN_X, N,M_X, N,N,N,Y,N,N,N,CSR.N,N,N,N,Y),
- FCVT_D_WU-> List(Y,Y,N,N,N,N,N,Y,N,A2_X, A1_RS1, IMM_X, DW_X, FN_X, N,M_X, N,N,N,Y,N,N,N,CSR.N,N,N,N,Y),
- FLD-> List(Y,Y,N,N,N,N,N,Y,N,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_ADD, Y,M_XRD, N,N,N,Y,N,N,N,CSR.N,N,N,N,Y),
- FSD-> List(Y,Y,N,N,N,N,N,Y,N,A2_IMM, A1_RS1, IMM_S, DW_XPR,FN_ADD, Y,M_XWR, N,Y,N,N,N,N,N,CSR.N,N,N,N,Y),
- FDIV_D-> List(Y,Y,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, Y,Y,N,Y,N,N,N,CSR.N,N,N,N,Y),
- FSQRT_D-> List(Y,Y,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, Y,Y,N,Y,N,N,N,CSR.N,N,N,N,Y))
+ FCVT_S_D-> List(Y,Y,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, Y,N,N,Y,N,N,N,CSR.N,N,N,N,Y,N,N,N),
+ FCVT_D_S-> List(Y,Y,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, Y,N,N,Y,N,N,N,CSR.N,N,N,N,Y,N,N,N),
+ FSGNJ_D-> List(Y,Y,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, Y,Y,N,Y,N,N,N,CSR.N,N,N,N,Y,N,N,N),
+ FSGNJX_D-> List(Y,Y,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, Y,Y,N,Y,N,N,N,CSR.N,N,N,N,Y,N,N,N),
+ FSGNJN_D-> List(Y,Y,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, Y,Y,N,Y,N,N,N,CSR.N,N,N,N,Y,N,N,N),
+ FMIN_D-> List(Y,Y,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, Y,Y,N,Y,N,N,N,CSR.N,N,N,N,Y,N,N,N),
+ FMAX_D-> List(Y,Y,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, Y,Y,N,Y,N,N,N,CSR.N,N,N,N,Y,N,N,N),
+ FADD_D-> List(Y,Y,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, Y,Y,N,Y,N,N,N,CSR.N,N,N,N,Y,N,N,N),
+ FSUB_D-> List(Y,Y,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, Y,Y,N,Y,N,N,N,CSR.N,N,N,N,Y,N,N,N),
+ FMUL_D-> List(Y,Y,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, Y,Y,N,Y,N,N,N,CSR.N,N,N,N,Y,N,N,N),
+ FMADD_D-> List(Y,Y,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, Y,Y,Y,Y,N,N,N,CSR.N,N,N,N,Y,N,N,N),
+ FMSUB_D-> List(Y,Y,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, Y,Y,Y,Y,N,N,N,CSR.N,N,N,N,Y,N,N,N),
+ FNMADD_D-> List(Y,Y,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, Y,Y,Y,Y,N,N,N,CSR.N,N,N,N,Y,N,N,N),
+ FNMSUB_D-> List(Y,Y,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, Y,Y,Y,Y,N,N,N,CSR.N,N,N,N,Y,N,N,N),
+ FCLASS_D-> List(Y,Y,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, Y,N,N,N,N,N,Y,CSR.N,N,N,N,Y,N,N,N),
+ FCVT_W_D-> List(Y,Y,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, Y,N,N,N,N,N,Y,CSR.N,N,N,N,Y,N,N,N),
+ FCVT_WU_D-> List(Y,Y,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, Y,N,N,N,N,N,Y,CSR.N,N,N,N,Y,N,N,N),
+ FEQ_D-> List(Y,Y,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, Y,Y,N,N,N,N,Y,CSR.N,N,N,N,Y,N,N,N),
+ FLT_D-> List(Y,Y,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, Y,Y,N,N,N,N,Y,CSR.N,N,N,N,Y,N,N,N),
+ FLE_D-> List(Y,Y,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, Y,Y,N,N,N,N,Y,CSR.N,N,N,N,Y,N,N,N),
+ FCVT_D_W-> List(Y,Y,N,N,N,N,N,Y,N,A2_X, A1_RS1, IMM_X, DW_X, FN_X, N,M_X, N,N,N,Y,N,N,N,CSR.N,N,N,N,Y,N,N,N),
+ FCVT_D_WU-> List(Y,Y,N,N,N,N,N,Y,N,A2_X, A1_RS1, IMM_X, DW_X, FN_X, N,M_X, N,N,N,Y,N,N,N,CSR.N,N,N,N,Y,N,N,N),
+ FLD-> List(Y,Y,N,N,N,N,N,Y,N,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_ADD, Y,M_XRD, N,N,N,Y,N,N,N,CSR.N,N,N,N,Y,N,N,N),
+ FSD-> List(Y,Y,N,N,N,N,N,Y,N,A2_IMM, A1_RS1, IMM_S, DW_XPR,FN_ADD, Y,M_XWR, N,Y,N,N,N,N,N,CSR.N,N,N,N,Y,N,N,N),
+ FDIV_D-> List(Y,Y,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, Y,Y,N,Y,N,N,N,CSR.N,N,N,N,Y,N,N,N),
+ FSQRT_D-> List(Y,Y,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, Y,Y,N,Y,N,N,N,CSR.N,N,N,N,Y,N,N,N))
}
class F64Decode(implicit val p: Parameters) extends DecodeConstants
{
val table: Array[(BitPat, List[BitPat])] = Array(
- FCVT_L_S-> List(Y,Y,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, Y,N,N,N,N,N,Y,CSR.N,N,N,N,N),
- FCVT_LU_S-> List(Y,Y,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, Y,N,N,N,N,N,Y,CSR.N,N,N,N,N),
- FCVT_S_L-> List(Y,Y,N,N,N,N,N,Y,N,A2_X, A1_RS1, IMM_X, DW_X, FN_X, N,M_X, N,N,N,Y,N,N,N,CSR.N,N,N,N,N),
- FCVT_S_LU-> List(Y,Y,N,N,N,N,N,Y,N,A2_X, A1_RS1, IMM_X, DW_X, FN_X, N,M_X, N,N,N,Y,N,N,N,CSR.N,N,N,N,N))
+ FCVT_L_S-> List(Y,Y,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, Y,N,N,N,N,N,Y,CSR.N,N,N,N,N,N,N,N),
+ FCVT_LU_S-> List(Y,Y,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, Y,N,N,N,N,N,Y,CSR.N,N,N,N,N,N,N,N),
+ FCVT_S_L-> List(Y,Y,N,N,N,N,N,Y,N,A2_X, A1_RS1, IMM_X, DW_X, FN_X, N,M_X, N,N,N,Y,N,N,N,CSR.N,N,N,N,N,N,N,N),
+ FCVT_S_LU-> List(Y,Y,N,N,N,N,N,Y,N,A2_X, A1_RS1, IMM_X, DW_X, FN_X, N,M_X, N,N,N,Y,N,N,N,CSR.N,N,N,N,N,N,N,N))
}
class D64Decode(implicit val p: Parameters) extends DecodeConstants
{
val table: Array[(BitPat, List[BitPat])] = Array(
- FMV_X_D-> List(Y,Y,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, Y,N,N,N,N,N,Y,CSR.N,N,N,N,Y),
- FCVT_L_D-> List(Y,Y,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, Y,N,N,N,N,N,Y,CSR.N,N,N,N,Y),
- FCVT_LU_D-> List(Y,Y,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, Y,N,N,N,N,N,Y,CSR.N,N,N,N,Y),
- FMV_D_X-> List(Y,Y,N,N,N,N,N,Y,N,A2_X, A1_RS1, IMM_X, DW_X, FN_X, N,M_X, N,N,N,Y,N,N,N,CSR.N,N,N,N,Y),
- FCVT_D_L-> List(Y,Y,N,N,N,N,N,Y,N,A2_X, A1_RS1, IMM_X, DW_X, FN_X, N,M_X, N,N,N,Y,N,N,N,CSR.N,N,N,N,Y),
- FCVT_D_LU-> List(Y,Y,N,N,N,N,N,Y,N,A2_X, A1_RS1, IMM_X, DW_X, FN_X, N,M_X, N,N,N,Y,N,N,N,CSR.N,N,N,N,Y))
+ FMV_X_D-> List(Y,Y,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, Y,N,N,N,N,N,Y,CSR.N,N,N,N,Y,N,N,N),
+ FCVT_L_D-> List(Y,Y,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, Y,N,N,N,N,N,Y,CSR.N,N,N,N,Y,N,N,N),
+ FCVT_LU_D-> List(Y,Y,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, Y,N,N,N,N,N,Y,CSR.N,N,N,N,Y,N,N,N),
+ FMV_D_X-> List(Y,Y,N,N,N,N,N,Y,N,A2_X, A1_RS1, IMM_X, DW_X, FN_X, N,M_X, N,N,N,Y,N,N,N,CSR.N,N,N,N,Y,N,N,N),
+ FCVT_D_L-> List(Y,Y,N,N,N,N,N,Y,N,A2_X, A1_RS1, IMM_X, DW_X, FN_X, N,M_X, N,N,N,Y,N,N,N,CSR.N,N,N,N,Y,N,N,N),
+ FCVT_D_LU-> List(Y,Y,N,N,N,N,N,Y,N,A2_X, A1_RS1, IMM_X, DW_X, FN_X, N,M_X, N,N,N,Y,N,N,N,CSR.N,N,N,N,Y,N,N,N))
}
class SCIEDecode(implicit val p: Parameters) extends DecodeConstants
{
val table: Array[(BitPat, List[BitPat])] = Array(
- SCIE.opcode-> List(Y,N,N,N,N,N,Y,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_X, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N))
+ SCIE.opcode-> List(Y,N,N,N,N,N,Y,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_X, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N,N,N,N))
}
class RoCCDecode(implicit val p: Parameters) extends DecodeConstants
{
val table: Array[(BitPat, List[BitPat])] = Array(
- CUSTOM0-> List(Y,N,Y,N,N,N,N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, N,N,N,N,N,N,N,CSR.N,N,N,N,N),
- CUSTOM0_RS1-> List(Y,N,Y,N,N,N,N,Y,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, N,N,N,N,N,N,N,CSR.N,N,N,N,N),
- CUSTOM0_RS1_RS2-> List(Y,N,Y,N,N,N,Y,Y,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, N,N,N,N,N,N,N,CSR.N,N,N,N,N),
- CUSTOM0_RD-> List(Y,N,Y,N,N,N,N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
- CUSTOM0_RD_RS1-> List(Y,N,Y,N,N,N,N,Y,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
- CUSTOM0_RD_RS1_RS2->List(Y,N,Y,N,N,N,Y,Y,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
- CUSTOM1-> List(Y,N,Y,N,N,N,N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, N,N,N,N,N,N,N,CSR.N,N,N,N,N),
- CUSTOM1_RS1-> List(Y,N,Y,N,N,N,N,Y,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, N,N,N,N,N,N,N,CSR.N,N,N,N,N),
- CUSTOM1_RS1_RS2-> List(Y,N,Y,N,N,N,Y,Y,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, N,N,N,N,N,N,N,CSR.N,N,N,N,N),
- CUSTOM1_RD-> List(Y,N,Y,N,N,N,N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
- CUSTOM1_RD_RS1-> List(Y,N,Y,N,N,N,N,Y,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
- CUSTOM1_RD_RS1_RS2->List(Y,N,Y,N,N,N,Y,Y,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
- CUSTOM2-> List(Y,N,Y,N,N,N,N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, N,N,N,N,N,N,N,CSR.N,N,N,N,N),
- CUSTOM2_RS1-> List(Y,N,Y,N,N,N,N,Y,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, N,N,N,N,N,N,N,CSR.N,N,N,N,N),
- CUSTOM2_RS1_RS2-> List(Y,N,Y,N,N,N,Y,Y,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, N,N,N,N,N,N,N,CSR.N,N,N,N,N),
- CUSTOM2_RD-> List(Y,N,Y,N,N,N,N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
- CUSTOM2_RD_RS1-> List(Y,N,Y,N,N,N,N,Y,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
- CUSTOM2_RD_RS1_RS2->List(Y,N,Y,N,N,N,Y,Y,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
- CUSTOM3-> List(Y,N,Y,N,N,N,N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, N,N,N,N,N,N,N,CSR.N,N,N,N,N),
- CUSTOM3_RS1-> List(Y,N,Y,N,N,N,N,Y,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, N,N,N,N,N,N,N,CSR.N,N,N,N,N),
- CUSTOM3_RS1_RS2-> List(Y,N,Y,N,N,N,Y,Y,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, N,N,N,N,N,N,N,CSR.N,N,N,N,N),
- CUSTOM3_RD-> List(Y,N,Y,N,N,N,N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
- CUSTOM3_RD_RS1-> List(Y,N,Y,N,N,N,N,Y,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
- CUSTOM3_RD_RS1_RS2->List(Y,N,Y,N,N,N,Y,Y,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N))
+ CUSTOM0-> List(Y,N,Y,N,N,N,N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, N,N,N,N,N,N,N,CSR.N,N,N,N,N,N,N,N),
+ CUSTOM0_RS1-> List(Y,N,Y,N,N,N,N,Y,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, N,N,N,N,N,N,N,CSR.N,N,N,N,N,N,N,N),
+ CUSTOM0_RS1_RS2-> List(Y,N,Y,N,N,N,Y,Y,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, N,N,N,N,N,N,N,CSR.N,N,N,N,N,N,N,N),
+ CUSTOM0_RD-> List(Y,N,Y,N,N,N,N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N,N,N,N),
+ CUSTOM0_RD_RS1-> List(Y,N,Y,N,N,N,N,Y,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N,N,N,N),
+ CUSTOM0_RD_RS1_RS2->List(Y,N,Y,N,N,N,Y,Y,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N,N,N,N),
+ CUSTOM1-> List(Y,N,Y,N,N,N,N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, N,N,N,N,N,N,N,CSR.N,N,N,N,N,N,N,N),
+ CUSTOM1_RS1-> List(Y,N,Y,N,N,N,N,Y,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, N,N,N,N,N,N,N,CSR.N,N,N,N,N,N,N,N),
+ CUSTOM1_RS1_RS2-> List(Y,N,Y,N,N,N,Y,Y,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, N,N,N,N,N,N,N,CSR.N,N,N,N,N,N,N,N),
+ CUSTOM1_RD-> List(Y,N,Y,N,N,N,N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N,N,N,N),
+ CUSTOM1_RD_RS1-> List(Y,N,Y,N,N,N,N,Y,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N,N,N,N),
+ CUSTOM1_RD_RS1_RS2->List(Y,N,Y,N,N,N,Y,Y,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N,N,N,N),
+ CUSTOM2-> List(Y,N,Y,N,N,N,N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, N,N,N,N,N,N,N,CSR.N,N,N,N,N,N,N,N),
+ CUSTOM2_RS1-> List(Y,N,Y,N,N,N,N,Y,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, N,N,N,N,N,N,N,CSR.N,N,N,N,N,N,N,N),
+ CUSTOM2_RS1_RS2-> List(Y,N,Y,N,N,N,Y,Y,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, N,N,N,N,N,N,N,CSR.N,N,N,N,N,N,N,N),
+ CUSTOM2_RD-> List(Y,N,Y,N,N,N,N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N,N,N,N),
+ CUSTOM2_RD_RS1-> List(Y,N,Y,N,N,N,N,Y,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N,N,N,N),
+ CUSTOM2_RD_RS1_RS2->List(Y,N,Y,N,N,N,Y,Y,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N,N,N,N),
+ CUSTOM3-> List(Y,N,Y,N,N,N,N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, N,N,N,N,N,N,N,CSR.N,N,N,N,N,N,N,N),
+ CUSTOM3_RS1-> List(Y,N,Y,N,N,N,N,Y,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, N,N,N,N,N,N,N,CSR.N,N,N,N,N,N,N,N),
+ CUSTOM3_RS1_RS2-> List(Y,N,Y,N,N,N,Y,Y,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, N,N,N,N,N,N,N,CSR.N,N,N,N,N,N,N,N),
+ CUSTOM3_RD-> List(Y,N,Y,N,N,N,N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N,N,N,N),
+ CUSTOM3_RD_RS1-> List(Y,N,Y,N,N,N,N,Y,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N,N,N,N),
+ CUSTOM3_RD_RS1_RS2->List(Y,N,Y,N,N,N,Y,Y,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N,N,N,N))
}
+
+class VectorDecode(implicit val p :Parameters) extends DecodeConstants //ZFINX==false default
+{
+ val x = if (ZFINX) Y else N
+ val f = if (ZFINX) N else Y
+ val table: Array[(BitPat, List[BitPat])] = Array(
+ // jal renf1 fence.i
+ // val | jalr | renf2 |
+ // | fp_val| | renx2 | | renf3 |
+ // | | rocc| | | renx1 s_alu1 mem_val | | | wfd |
+ // | | | br| | | | s_alu2 | imm dw alu | mem_cmd | | | | mul | vp
+ // | | | | | | | | | | | | | | | | | | | | div | fence | vp_fp
+ // | | | | | | | | | | | | | | | | | | | | | wxd | | amo | | vp_mem
+ // | | | | | | | | scie | | | | | | | | | | | | | | | | dp| | |
+ VAIVV-> List(Y,N,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, N,N,N,N,N,N,N,CSR.N,N,N,N,N,Y,N,N),
+ VAIVX-> List(Y,N,N,N,N,N,N,Y,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, N,N,N,N,N,N,N,CSR.N,N,N,N,N,Y,N,N),
+ VAIVI-> List(Y,N,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, N,N,N,N,N,N,N,CSR.N,N,N,N,N,Y,N,N),
+ VAMVX-> List(Y,N,N,N,N,N,N,Y,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, N,N,N,N,N,N,N,CSR.N,N,N,N,N,Y,N,N),
+ VAFVF-> List(Y,N,N,N,N,N,N,x,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, f,N,N,N,N,N,N,CSR.N,N,N,N,N,Y,Y,N),
+ //csr insts
+ VSETVLI-> List(Y,N,N,N,N,N,N,Y,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N,Y,N,N),
+ VSETVL-> List(Y,N,N,N,N,N,Y,Y,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N,Y,N,N),
+ //VAMVV type insts
+ VREDSUM_VS-> List(Y,N,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, N,N,N,N,N,N,N,CSR.N,N,N,N,N,Y,N,N),
+ VREDAND_VS-> List(Y,N,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, N,N,N,N,N,N,N,CSR.N,N,N,N,N,Y,N,N),
+ VREDOR_VS-> List(Y,N,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, N,N,N,N,N,N,N,CSR.N,N,N,N,N,Y,N,N),
+ VREDXOR_VS-> List(Y,N,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, N,N,N,N,N,N,N,CSR.N,N,N,N,N,Y,N,N),
+ VREDMINU_VS-> List(Y,N,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, N,N,N,N,N,N,N,CSR.N,N,N,N,N,Y,N,N),
+ VREDMIN_VS-> List(Y,N,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, N,N,N,N,N,N,N,CSR.N,N,N,N,N,Y,N,N),
+ VREDMAXU_VS-> List(Y,N,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, N,N,N,N,N,N,N,CSR.N,N,N,N,N,Y,N,N),
+ VREDMAX_VS-> List(Y,N,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, N,N,N,N,N,N,N,CSR.N,N,N,N,N,Y,N,N),
+ VAADDU_VV-> List(Y,N,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, N,N,N,N,N,N,N,CSR.N,N,N,N,N,Y,N,N),
+ VAADD_VV-> List(Y,N,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, N,N,N,N,N,N,N,CSR.N,N,N,N,N,Y,N,N),
+ VASUBU_VV-> List(Y,N,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, N,N,N,N,N,N,N,CSR.N,N,N,N,N,Y,N,N),
+ VASUB_VV-> List(Y,N,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, N,N,N,N,N,N,N,CSR.N,N,N,N,N,Y,N,N),
+
+ VSCALARX-> List(Y,N,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N,Y,N,N), //VWXUNARY0
+
+ VMUNARY0-> List(Y,N,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, N,N,N,N,N,N,N,CSR.N,N,N,N,N,Y,N,N),
+ VCOMPRESS_VM-> List(Y,N,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, N,N,N,N,N,N,N,CSR.N,N,N,N,N,Y,N,N),
+ VMANDNOT_MM-> List(Y,N,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, N,N,N,N,N,N,N,CSR.N,N,N,N,N,Y,N,N),
+ VMAND_MM-> List(Y,N,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, N,N,N,N,N,N,N,CSR.N,N,N,N,N,Y,N,N),
+ VMOR_MM-> List(Y,N,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, N,N,N,N,N,N,N,CSR.N,N,N,N,N,Y,N,N),
+ VMXOR_MM-> List(Y,N,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, N,N,N,N,N,N,N,CSR.N,N,N,N,N,Y,N,N),
+ VMORNOT_MM-> List(Y,N,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, N,N,N,N,N,N,N,CSR.N,N,N,N,N,Y,N,N),
+ VMNAND_MM-> List(Y,N,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, N,N,N,N,N,N,N,CSR.N,N,N,N,N,Y,N,N),
+ VMNOR_MM-> List(Y,N,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, N,N,N,N,N,N,N,CSR.N,N,N,N,N,Y,N,N),
+ VMXNOR_MM-> List(Y,N,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, N,N,N,N,N,N,N,CSR.N,N,N,N,N,Y,N,N),
+ VDIVU_VV-> List(Y,N,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, N,N,N,N,N,N,N,CSR.N,N,N,N,N,Y,N,N),
+ VDIV_VV-> List(Y,N,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, N,N,N,N,N,N,N,CSR.N,N,N,N,N,Y,N,N),
+ VREMU_VV-> List(Y,N,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, N,N,N,N,N,N,N,CSR.N,N,N,N,N,Y,N,N),
+ VREM_VV-> List(Y,N,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, N,N,N,N,N,N,N,CSR.N,N,N,N,N,Y,N,N),
+ VMULHU_VV-> List(Y,N,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, N,N,N,N,N,N,N,CSR.N,N,N,N,N,Y,N,N),