mkdocs.yml

site_name: 数字电路教程
site_author: USTC Vlab
site_url: https://vlab.ustc.edu.cn/guide/
repo_name: USTC-vlab/guide
repo_url: https://github.com/USTC-vlab/guide
use_directory_urls: false

theme:
  name: material
  language: zh
  palette:
    - scheme: default
      media: "(prefers-color-scheme: light)"
      primary: blue
      accent: blue
      toggle:
        icon: material/toggle-switch-off-outline
        name: 切换至深色模式
    - scheme: slate
      media: "(prefers-color-scheme: dark)"
      primary: light blue
      accent: light blue
      toggle:
        icon: material/toggle-switch
        name: 切换至浅色模式
  icon:
    logo: material/book
    repo: octicons/mark-github-16
  features:
    - navigation.sections
    - navigation.top

markdown_extensions:
  - attr_list
  - def_list
  - pymdownx.arithmatex:
      generic: true
  - pymdownx.highlight
  - pymdownx.superfences
  - pymdownx.tilde

extra_javascript:
  - katex.js
  - https://unpkg.com/katex@0/dist/katex.min.js
  - https://unpkg.com/katex@0/dist/contrib/auto-render.min.js

extra_css:
  - https://unpkg.com/katex@0/dist/katex.min.css

extra:
  social:
    - icon: octicons/globe-16
      link: 'https://vlab.ustc.edu.cn/'
    - icon: octicons/mark-github-16
      link: 'https://github.com/USTC-vlab'
  analytics:
    provider: google
    property: UA-115907213-3

nav:
  - 课程介绍: index.md
  - LogiSim: doc_logisim.md
  - Verilog 语法: doc_verilog.md
  - FPGA 原理: doc_fpga.md
  - Nexys4DDR 开发板: doc_nexys.md
  - Vivado 介绍: doc_vivado.md
  - TestBench 编写及仿真: doc_testbench.md
  - 代码风格规范: coding_convention.md
  - 一些例子:
    - 基本逻辑门: doc_basic_logic.md
    - 简单组合逻辑电路: doc_simple_logic.md
    - 复杂组合逻辑电路: doc_complex_logic.md
    - 简单时序逻辑电路: doc_simple_timing.md
    - 复杂时序逻辑电路: doc_complex_timing.md
    - 有限状态机: doc_finite_state_machine.md