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Similar to the way we can set the include directories (include_dirs) for SystemVerilog files, we need a way to specify (the value of) a define in the argument of add_source_files().
The text was updated successfully, but these errors were encountered:
Similar to the way we can set the include directories (
include_dirs
) for SystemVerilog files, we need a way to specify (the value of) a define in the argument ofadd_source_files()
.The text was updated successfully, but these errors were encountered: