case sensitive parameter comparison

[swattor]

I've got a systemverilog testbench that I am trying to set a parameter on - however I get the following error:

WARNING - Generic 'test_generic' set to value '1' not found in entity 'lib.testbench'. Possible values are [TEST_GENERIC]

This is the line that I'm using to set the parameter:
testbench.set_parameter("TEST_GENERIC",1)

Can this comparison be made to be case insensitive? Or I may be doing something else wrong.

[swattor]

Looks like it's the name.lower() on line 380 of ui.py that is causing this.

[kraigher]

For VHDL we normalize everything to lower case. For Verilog this could cause problems. We will have to fix it.