Fix port type starting with signal

[eschmidscs]

Trying to fix #791.
I don't know/understand the replacement of "signal", so the padding with a space might not be the correct solution.

[dalex78]

@LarsAsplund, this looks good to me.

[dalex78]

I did not see the ''change requested". As I do not believe I can directly modify this PR, I will create a new one with the requested changes.

[eschmidscs]

@dalex78 I think I have fixed the requests - that's why I requested another review.

[dalex78]

@eschmidscs Unless I am mistaken, I see in test_vhdl_parser.vhd:

port (clk : in std_logic;
         data : out std_logic_vector(11-1 downto 0));
         data : out std_logic_vector(11-1 downto 0);
         signal_data2 : in std_logic;
         data3 : in signal_type;
         data4_signal : in std_logic;
         data5 : in type_signal
);

And Lars was asking to add something like that:

entity name is
port (
    clk : in std_logic;
    data : out std_logic_vector(11-1 downto 0);
    signal_data2 : in std_logic;
    data3 :\tin signal_type;
    data4_signal : in std_logic;
    data5\t: in type_signal;
    signal clk2 : in std_logic;
    signal\tdata7 : out std_logic_vector(11-1 downto 0);
    signal signal_data8 : in std_logic;
    signal data9 : in signal_type;
    signal data10_signal :\tin std_logic;\t
    signal data11 : in type_signal
);
end entity;

(I am not sure the '\t' can be added like that.)

[dalex78]

You can see the changes here also: https://github.com/dalex78/vunit/tree/port_type_signal

[eschmidscs]

@dalex78 Yes, sorry, I just realized that I have only fixed the regex, but not extended the test. But you can just as well go ahead and push your branch and close this one.

[dalex78]

Ok, I'll do that. Tests are running (locally) to see if everything works fine. Thank you.

[dalex78]

@LarsAsplund I suggest to close without merging this PR.
The new PR is #826.