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MIPS: Instruction Disassembly/Lifting Completion #4014
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Bug: In disassembling
The real interpretation in the "else" case should be |
This list is missing |
It's also missing (at least) |
Thanks for aggregating these -- makes it easier to track when we're working on them. If there's one in particular that is slowing you down versus the others please let us know, or you can subclass our architecture and implement it yourself even. See, eg: https://github.com/Vector35/binaryninja-api/tree/dev/examples/x86_extension |
Yep, just found that you had this generic issue. In my case the missing lifting is breaking the whole lifting for the function, so that one is the one that matters me the most. I just found out that you can do it yourself as you mention, so I might try that soon. |
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Thanks -- updated the original list. |
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Seems like the MIPS coprocessor registers aren't classified as "system registers", so e.g. HLIL optimizes a function full of side-effectful Also, maybe |
The CACHE instruction OP is not decoded correctly.
The cache op is 5 bits, 20:16, split into two subfields:
The above cases were (if my numbers are right):
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The following is the list of instructions which we currently disassemble and lift (Fully or Partially). If you have any instructions which differ from this table, there is likely a bug or a documentation failure, please let us know (also if you could provide the opcodes that would be great).
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