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testbench.sv
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testbench.sv
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`include "interface.sv"
`include "tb_pkg.sv"
module top;
import uvm_pkg::*;
import tb_pkg::*;
//----------------------------------------------------------------------------
intf i_intf();
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
add_sub_dut DUT(.in1(i_intf.in1),
.in2(i_intf.in2),
.add_sub(i_intf.add_sub),
.out(i_intf.out)
);
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
initial begin
$dumpfile("dumpfile.vcd");
$dumpvars;
end
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
initial begin
uvm_config_db#(virtual intf)::set(uvm_root::get(),"","vif",i_intf);
end
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
initial begin
run_test("add_sub_test");
end
//----------------------------------------------------------------------------
endmodule