You signed in with another tab or window. Reload to refresh your session.You signed out in another tab or window. Reload to refresh your session.You switched accounts on another tab or window. Reload to refresh your session.Dismiss alert
I'm trying to connect XDMA IP core to DDR. When I try to transfer a 1.2 MB file(I set the size to 1268736), I find the XDMA AXI interface split the data stream with an unknown len.
I have try other size, and finally I found this will happen when transfer size larger than 256.
This picture shows what will happen on AXI write channel when I set the size to 512, AXI_DWIDTH to 128. In fact, it will send 25(1*16+8+1)*128bit data when awlen gets 18(h). I have a lot of trouble on it because my memory interface has another data width and I must finish a gearbox on it.
I think this problem maybe come from XDMA linux driver or linux library functions.
I have try to split my data in xdma_rw.c, but it still no work when transfer for a time(about 5KB).
One more thing, AXI interface address indicates bytes address. It means one address corresponds to 8bit data, not your AXI data width.
The text was updated successfully, but these errors were encountered:
I'm trying to connect XDMA IP core to DDR. When I try to transfer a 1.2 MB file(I set the size to 1268736), I find the XDMA AXI interface split the data stream with an unknown len.
![axi_interface](https://private-user-images.githubusercontent.com/32798311/286629319-0b20c960-79cd-447c-ac3e-ce093665a7fb.png?jwt=eyJhbGciOiJIUzI1NiIsInR5cCI6IkpXVCJ9.eyJpc3MiOiJnaXRodWIuY29tIiwiYXVkIjoicmF3LmdpdGh1YnVzZXJjb250ZW50LmNvbSIsImtleSI6ImtleTUiLCJleHAiOjE3MTkwNzU1NzUsIm5iZiI6MTcxOTA3NTI3NSwicGF0aCI6Ii8zMjc5ODMxMS8yODY2MjkzMTktMGIyMGM5NjAtNzljZC00NDdjLWFjM2UtY2UwOTM2NjVhN2ZiLnBuZz9YLUFtei1BbGdvcml0aG09QVdTNC1ITUFDLVNIQTI1NiZYLUFtei1DcmVkZW50aWFsPUFLSUFWQ09EWUxTQTUzUFFLNFpBJTJGMjAyNDA2MjIlMkZ1cy1lYXN0LTElMkZzMyUyRmF3czRfcmVxdWVzdCZYLUFtei1EYXRlPTIwMjQwNjIyVDE2NTQzNVomWC1BbXotRXhwaXJlcz0zMDAmWC1BbXotU2lnbmF0dXJlPTkzNDdiOTI5ZTc4Nzk5Nzg3NzE1ZjZlMWE1YmZiNDA0ZjUzNDgzMWFiNTQ2MzVlODJjZTgxZTgyZjQwYzM2ZmUmWC1BbXotU2lnbmVkSGVhZGVycz1ob3N0JmFjdG9yX2lkPTAma2V5X2lkPTAmcmVwb19pZD0wIn0.3s56qjo1mNDVAPj5rqs6I4NfDhhmkM6kKeBIzTi7xC0)
I have try other size, and finally I found this will happen when transfer size larger than 256.
This picture shows what will happen on AXI write channel when I set the size to 512, AXI_DWIDTH to 128. In fact, it will send 25(1*16+8+1)*128bit data when awlen gets 18(h). I have a lot of trouble on it because my memory interface has another data width and I must finish a gearbox on it.
I think this problem maybe come from XDMA linux driver or linux library functions.
I have try to split my data in xdma_rw.c, but it still no work when transfer for a time(about 5KB).
One more thing, AXI interface address indicates bytes address. It means one address corresponds to 8bit data, not your AXI data width.
The text was updated successfully, but these errors were encountered: