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MacroAssemblerARM64.h
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MacroAssemblerARM64.h
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/*
* Copyright (C) 2012-2023 Apple Inc. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY APPLE INC. ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL APPLE INC. OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
* OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#pragma once
#if ENABLE(ASSEMBLER) && CPU(ARM64)
#include "ARM64Assembler.h"
#include "AbstractMacroAssembler.h"
#include "JITOperationValidation.h"
#include <wtf/MathExtras.h>
namespace JSC {
using Assembler = TARGET_ASSEMBLER;
class Reg;
class MacroAssemblerARM64 : public AbstractMacroAssembler<Assembler> {
public:
static constexpr unsigned numGPRs = 32;
static constexpr unsigned numFPRs = 32;
static constexpr size_t nearJumpRange = 128 * MB;
static constexpr RegisterID dataTempRegister = ARM64Registers::ip0;
static constexpr RegisterID memoryTempRegister = ARM64Registers::ip1;
static constexpr RegisterID InvalidGPRReg = ARM64Registers::InvalidGPRReg;
static constexpr ARM64Registers::FPRegisterID fpTempRegister = ARM64Registers::q31;
RegisterID scratchRegister()
{
RELEASE_ASSERT(m_allowScratchRegister);
return getCachedDataTempRegisterIDAndInvalidate();
}
protected:
static constexpr Assembler::SetFlags S = Assembler::S;
static constexpr int64_t maskHalfWord0 = 0xffffl;
static constexpr int64_t maskHalfWord1 = 0xffff0000l;
static constexpr int64_t maskUpperWord = 0xffffffff00000000l;
static constexpr size_t INSTRUCTION_SIZE = 4;
// N instructions to load the pointer + 1 call instruction.
static constexpr ptrdiff_t REPATCH_OFFSET_CALL_TO_POINTER = -((Assembler::MAX_POINTER_BITS / 16 + 1) * INSTRUCTION_SIZE);
public:
MacroAssemblerARM64()
: m_dataMemoryTempRegister(this, dataTempRegister)
, m_cachedMemoryTempRegister(this, memoryTempRegister)
, m_makeJumpPatchable(false)
{
}
typedef Assembler::LinkRecord LinkRecord;
typedef Assembler::JumpType JumpType;
typedef Assembler::JumpLinkType JumpLinkType;
typedef Assembler::Condition Condition;
static constexpr Assembler::Condition DefaultCondition = Assembler::ConditionInvalid;
static constexpr Assembler::JumpType DefaultJump = Assembler::JumpNoConditionFixedSize;
Vector<LinkRecord, 0, UnsafeVectorOverflow>& jumpsToLink() { return m_assembler.jumpsToLink(); }
static bool canCompact(JumpType jumpType) { return Assembler::canCompact(jumpType); }
static JumpLinkType computeJumpType(JumpType jumpType, const uint8_t* from, const uint8_t* to) { return Assembler::computeJumpType(jumpType, from, to); }
static JumpLinkType computeJumpType(LinkRecord& record, const uint8_t* from, const uint8_t* to) { return Assembler::computeJumpType(record, from, to); }
static int jumpSizeDelta(JumpType jumpType, JumpLinkType jumpLinkType) { return Assembler::jumpSizeDelta(jumpType, jumpLinkType); }
template <Assembler::CopyFunction copy>
ALWAYS_INLINE static void link(LinkRecord& record, uint8_t* from, const uint8_t* fromInstruction, uint8_t* to) { return Assembler::link<copy>(record, from, fromInstruction, to); }
static bool isCompactPtrAlignedAddressOffset(ptrdiff_t value)
{
// This is the largest 32-bit access allowed, aligned to 64-bit boundary.
return !(value & ~0x3ff8);
}
enum RelationalCondition {
Equal = Assembler::ConditionEQ,
NotEqual = Assembler::ConditionNE,
Above = Assembler::ConditionHI,
AboveOrEqual = Assembler::ConditionHS,
Below = Assembler::ConditionLO,
BelowOrEqual = Assembler::ConditionLS,
GreaterThan = Assembler::ConditionGT,
GreaterThanOrEqual = Assembler::ConditionGE,
LessThan = Assembler::ConditionLT,
LessThanOrEqual = Assembler::ConditionLE
};
enum ResultCondition {
Overflow = Assembler::ConditionVS,
Signed = Assembler::ConditionMI,
PositiveOrZero = Assembler::ConditionPL,
Zero = Assembler::ConditionEQ,
NonZero = Assembler::ConditionNE
};
enum ZeroCondition {
IsZero = Assembler::ConditionEQ,
IsNonZero = Assembler::ConditionNE
};
enum DoubleCondition {
// These conditions will only evaluate to true if the comparison is ordered - i.e. neither operand is NaN.
DoubleEqualAndOrdered = Assembler::ConditionEQ,
DoubleNotEqualAndOrdered = Assembler::ConditionVC, // Not the right flag! check for this & handle differently.
DoubleGreaterThanAndOrdered = Assembler::ConditionGT,
DoubleGreaterThanOrEqualAndOrdered = Assembler::ConditionGE,
DoubleLessThanAndOrdered = Assembler::ConditionLO,
DoubleLessThanOrEqualAndOrdered = Assembler::ConditionLS,
// If either operand is NaN, these conditions always evaluate to true.
DoubleEqualOrUnordered = Assembler::ConditionVS, // Not the right flag! check for this & handle differently.
DoubleNotEqualOrUnordered = Assembler::ConditionNE,
DoubleGreaterThanOrUnordered = Assembler::ConditionHI,
DoubleGreaterThanOrEqualOrUnordered = Assembler::ConditionHS,
DoubleLessThanOrUnordered = Assembler::ConditionLT,
DoubleLessThanOrEqualOrUnordered = Assembler::ConditionLE,
};
static constexpr RegisterID stackPointerRegister = ARM64Registers::sp;
static constexpr RegisterID framePointerRegister = ARM64Registers::fp;
static constexpr RegisterID linkRegister = ARM64Registers::lr;
// FIXME: Get reasonable implementations for these
static bool constexpr shouldBlindForSpecificArch(uint32_t value) { return value >= 0x00ffffff; }
static bool constexpr shouldBlindForSpecificArch(uint64_t value) { return value >= 0x00ffffff; }
// Integer operations:
void add32(RegisterID a, RegisterID b, RegisterID dest)
{
ASSERT(a != ARM64Registers::sp || b != ARM64Registers::sp);
if (b == ARM64Registers::sp)
std::swap(a, b);
m_assembler.add<32>(dest, a, b);
}
void add32(RegisterID src, RegisterID dest)
{
if (src == ARM64Registers::sp)
m_assembler.add<32>(dest, src, dest);
else
m_assembler.add<32>(dest, dest, src);
}
void add32(TrustedImm32 imm, RegisterID dest)
{
add32(imm, dest, dest);
}
void add32(TrustedImm32 imm, RegisterID src, RegisterID dest)
{
if (isUInt12(imm.m_value))
m_assembler.add<32>(dest, src, UInt12(imm.m_value));
else if (isUInt12(-imm.m_value))
m_assembler.sub<32>(dest, src, UInt12(-imm.m_value));
else if (src != dest) {
move(imm, dest);
add32(src, dest);
} else {
move(imm, getCachedDataTempRegisterIDAndInvalidate());
m_assembler.add<32>(dest, src, dataTempRegister);
}
}
void add32(TrustedImm32 imm, Address address)
{
load32(address, getCachedDataTempRegisterIDAndInvalidate());
if (isUInt12(imm.m_value))
m_assembler.add<32>(dataTempRegister, dataTempRegister, UInt12(imm.m_value));
else if (isUInt12(-imm.m_value))
m_assembler.sub<32>(dataTempRegister, dataTempRegister, UInt12(-imm.m_value));
else {
move(imm, getCachedMemoryTempRegisterIDAndInvalidate());
m_assembler.add<32>(dataTempRegister, dataTempRegister, memoryTempRegister);
}
store32(dataTempRegister, address);
}
void add32(TrustedImm32 imm, AbsoluteAddress address)
{
load32(address.m_ptr, getCachedDataTempRegisterIDAndInvalidate());
if (isUInt12(imm.m_value)) {
m_assembler.add<32>(dataTempRegister, dataTempRegister, UInt12(imm.m_value));
store32(dataTempRegister, address.m_ptr);
return;
}
if (isUInt12(-imm.m_value)) {
m_assembler.sub<32>(dataTempRegister, dataTempRegister, UInt12(-imm.m_value));
store32(dataTempRegister, address.m_ptr);
return;
}
move(imm, getCachedMemoryTempRegisterIDAndInvalidate());
m_assembler.add<32>(dataTempRegister, dataTempRegister, memoryTempRegister);
store32(dataTempRegister, address.m_ptr);
}
void add32(Address src, RegisterID dest)
{
load32(src, getCachedDataTempRegisterIDAndInvalidate());
add32(dataTempRegister, dest);
}
void add32(AbsoluteAddress src, RegisterID dest)
{
load32(src.m_ptr, getCachedDataTempRegisterIDAndInvalidate());
add32(dataTempRegister, dest);
}
void add64(RegisterID a, RegisterID b, RegisterID dest)
{
ASSERT(a != ARM64Registers::sp || b != ARM64Registers::sp);
if (b == ARM64Registers::sp)
std::swap(a, b);
m_assembler.add<64>(dest, a, b);
}
void add64(RegisterID src, RegisterID dest)
{
if (src == ARM64Registers::sp)
m_assembler.add<64>(dest, src, dest);
else
m_assembler.add<64>(dest, dest, src);
}
void add64(TrustedImm32 imm, RegisterID dest)
{
if (isUInt12(imm.m_value)) {
m_assembler.add<64>(dest, dest, UInt12(imm.m_value));
return;
}
if (isUInt12(-imm.m_value)) {
m_assembler.sub<64>(dest, dest, UInt12(-imm.m_value));
return;
}
signExtend32ToPtr(imm, getCachedDataTempRegisterIDAndInvalidate());
m_assembler.add<64>(dest, dest, dataTempRegister);
}
void add64(TrustedImm64 imm, RegisterID dest)
{
intptr_t immediate = imm.m_value;
if (isUInt12(immediate)) {
m_assembler.add<64>(dest, dest, UInt12(static_cast<int32_t>(immediate)));
return;
}
if (isUInt12(-immediate)) {
m_assembler.sub<64>(dest, dest, UInt12(static_cast<int32_t>(-immediate)));
return;
}
move(imm, getCachedDataTempRegisterIDAndInvalidate());
m_assembler.add<64>(dest, dest, dataTempRegister);
}
void add64(TrustedImm32 imm, RegisterID src, RegisterID dest)
{
if (isUInt12(imm.m_value)) {
m_assembler.add<64>(dest, src, UInt12(imm.m_value));
return;
}
if (isUInt12(-imm.m_value)) {
m_assembler.sub<64>(dest, src, UInt12(-imm.m_value));
return;
}
signExtend32ToPtr(imm, getCachedDataTempRegisterIDAndInvalidate());
m_assembler.add<64>(dest, src, dataTempRegister);
}
void add64(TrustedImm32 imm, Address address)
{
load64(address, getCachedDataTempRegisterIDAndInvalidate());
if (isUInt12(imm.m_value))
m_assembler.add<64>(dataTempRegister, dataTempRegister, UInt12(imm.m_value));
else if (isUInt12(-imm.m_value))
m_assembler.sub<64>(dataTempRegister, dataTempRegister, UInt12(-imm.m_value));
else {
signExtend32ToPtr(imm, getCachedMemoryTempRegisterIDAndInvalidate());
m_assembler.add<64>(dataTempRegister, dataTempRegister, memoryTempRegister);
}
store64(dataTempRegister, address);
}
void add64(TrustedImm32 imm, AbsoluteAddress address)
{
load64(address.m_ptr, getCachedDataTempRegisterIDAndInvalidate());
if (isUInt12(imm.m_value)) {
m_assembler.add<64>(dataTempRegister, dataTempRegister, UInt12(imm.m_value));
store64(dataTempRegister, address.m_ptr);
return;
}
if (isUInt12(-imm.m_value)) {
m_assembler.sub<64>(dataTempRegister, dataTempRegister, UInt12(-imm.m_value));
store64(dataTempRegister, address.m_ptr);
return;
}
signExtend32ToPtr(imm, getCachedMemoryTempRegisterIDAndInvalidate());
m_assembler.add<64>(dataTempRegister, dataTempRegister, memoryTempRegister);
store64(dataTempRegister, address.m_ptr);
}
void addZeroExtend64(RegisterID src, RegisterID srcExtend, RegisterID dest)
{
ASSERT(srcExtend != ARM64Registers::sp);
m_assembler.add<64>(dest, src, srcExtend, Assembler::UXTW, 0);
}
void addSignExtend64(RegisterID src, RegisterID srcExtend, RegisterID dest)
{
ASSERT(srcExtend != ARM64Registers::sp);
m_assembler.add<64>(dest, src, srcExtend, Assembler::SXTW, 0);
}
void addPtrNoFlags(TrustedImm32 imm, RegisterID srcDest)
{
add64(imm, srcDest);
}
void add64(Address src, RegisterID dest)
{
load64(src, getCachedDataTempRegisterIDAndInvalidate());
m_assembler.add<64>(dest, dest, dataTempRegister);
}
void add64(RegisterID src, Address dest)
{
load64(dest, getCachedDataTempRegisterIDAndInvalidate());
m_assembler.add<64>(src, dataTempRegister, dataTempRegister);
store64(dataTempRegister, dest);
}
void add64(AbsoluteAddress src, RegisterID dest)
{
load64(src.m_ptr, getCachedDataTempRegisterIDAndInvalidate());
m_assembler.add<64>(dest, dest, dataTempRegister);
}
void add8(TrustedImm32 imm, Address address)
{
load8(address, getCachedMemoryTempRegisterIDAndInvalidate());
add32(imm, memoryTempRegister, getCachedDataTempRegisterIDAndInvalidate());
store8(dataTempRegister, address);
}
void and32(RegisterID src, RegisterID dest)
{
and32(dest, src, dest);
}
void and32(RegisterID op1, RegisterID op2, RegisterID dest)
{
m_assembler.and_<32>(dest, op1, op2);
}
void and32(TrustedImm32 imm, RegisterID dest)
{
and32(imm, dest, dest);
}
void and32(TrustedImm32 imm, RegisterID src, RegisterID dest)
{
LogicalImmediate logicalImm = LogicalImmediate::create32(imm.m_value);
if (logicalImm.isValid()) {
m_assembler.and_<32>(dest, src, logicalImm);
return;
}
move(imm, getCachedDataTempRegisterIDAndInvalidate());
m_assembler.and_<32>(dest, src, dataTempRegister);
}
void and32(Address src, RegisterID dest)
{
load32(src, getCachedDataTempRegisterIDAndInvalidate());
and32(dataTempRegister, dest);
}
void and16(Address src, RegisterID dest)
{
load16(src, getCachedDataTempRegisterIDAndInvalidate());
and32(dataTempRegister, dest);
}
void and64(RegisterID src1, RegisterID src2, RegisterID dest)
{
m_assembler.and_<64>(dest, src1, src2);
}
void and64(TrustedImm64 imm, RegisterID src, RegisterID dest)
{
LogicalImmediate logicalImm = LogicalImmediate::create64(imm.m_value);
if (logicalImm.isValid()) {
m_assembler.and_<64>(dest, src, logicalImm);
return;
}
move(imm, getCachedDataTempRegisterIDAndInvalidate());
m_assembler.and_<64>(dest, src, dataTempRegister);
}
void and64(RegisterID src, RegisterID dest)
{
m_assembler.and_<64>(dest, dest, src);
}
void and64(TrustedImm32 imm, RegisterID dest)
{
LogicalImmediate logicalImm = LogicalImmediate::create64(static_cast<intptr_t>(static_cast<int64_t>(imm.m_value)));
if (logicalImm.isValid()) {
m_assembler.and_<64>(dest, dest, logicalImm);
return;
}
signExtend32ToPtr(imm, getCachedDataTempRegisterIDAndInvalidate());
m_assembler.and_<64>(dest, dest, dataTempRegister);
}
void and64(TrustedImmPtr imm, RegisterID dest)
{
intptr_t value = imm.asIntptr();
if constexpr (sizeof(void*) == sizeof(uint64_t))
and64(TrustedImm64(value), dest);
else
and64(TrustedImm32(static_cast<int32_t>(value)), dest);
}
void and64(TrustedImm64 imm, RegisterID dest)
{
LogicalImmediate logicalImm = LogicalImmediate::create64(bitwise_cast<uint64_t>(imm.m_value));
if (logicalImm.isValid()) {
m_assembler.and_<64>(dest, dest, logicalImm);
return;
}
move(imm, getCachedDataTempRegisterIDAndInvalidate());
m_assembler.and_<64>(dest, dest, dataTempRegister);
}
// Bit operations:
void extractUnsignedBitfield32(RegisterID src, TrustedImm32 lsb, TrustedImm32 width, RegisterID dest)
{
m_assembler.ubfx<32>(dest, src, lsb.m_value, width.m_value);
}
void extractUnsignedBitfield64(RegisterID src, TrustedImm32 lsb, TrustedImm32 width, RegisterID dest)
{
m_assembler.ubfx<64>(dest, src, lsb.m_value, width.m_value);
}
void insertUnsignedBitfieldInZero32(RegisterID src, TrustedImm32 lsb, TrustedImm32 width, RegisterID dest)
{
m_assembler.ubfiz<32>(dest, src, lsb.m_value, width.m_value);
}
void insertUnsignedBitfieldInZero64(RegisterID src, TrustedImm32 lsb, TrustedImm32 width, RegisterID dest)
{
m_assembler.ubfiz<64>(dest, src, lsb.m_value, width.m_value);
}
void insertBitField32(RegisterID source, TrustedImm32 lsb, TrustedImm32 width, RegisterID dest)
{
m_assembler.bfi<32>(dest, source, lsb.m_value, width.m_value);
}
void insertBitField64(RegisterID source, TrustedImm32 lsb, TrustedImm32 width, RegisterID dest)
{
m_assembler.bfi<64>(dest, source, lsb.m_value, width.m_value);
}
void clearBitField32(TrustedImm32 lsb, TrustedImm32 width, RegisterID dest)
{
m_assembler.bfc<32>(dest, lsb.m_value, width.m_value);
}
void clearBitField64(TrustedImm32 lsb, TrustedImm32 width, RegisterID dest)
{
m_assembler.bfc<64>(dest, lsb.m_value, width.m_value);
}
void clearBitsWithMask32(RegisterID src, RegisterID mask, RegisterID dest)
{
m_assembler.bic<32>(dest, src, mask);
}
void clearBitsWithMask64(RegisterID src, RegisterID mask, RegisterID dest)
{
m_assembler.bic<64>(dest, src, mask);
}
void orNot32(RegisterID src, RegisterID mask, RegisterID dest)
{
m_assembler.orn<32>(dest, src, mask);
}
void orNot64(RegisterID src, RegisterID mask, RegisterID dest)
{
m_assembler.orn<64>(dest, src, mask);
}
void xorNot32(RegisterID src, RegisterID mask, RegisterID dest)
{
m_assembler.eon<32>(dest, src, mask);
}
void xorNot64(RegisterID src, RegisterID mask, RegisterID dest)
{
m_assembler.eon<64>(dest, src, mask);
}
void xorNotLeftShift32(RegisterID n, RegisterID m, TrustedImm32 amount, RegisterID d)
{
m_assembler.eon<32>(d, n, m, Assembler::LSL, amount.m_value);
}
void xorNotRightShift32(RegisterID n, RegisterID m, TrustedImm32 amount, RegisterID d)
{
m_assembler.eon<32>(d, n, m, Assembler::ASR, amount.m_value);
}
void xorNotUnsignedRightShift32(RegisterID n, RegisterID m, TrustedImm32 amount, RegisterID d)
{
m_assembler.eon<32>(d, n, m, Assembler::LSR, amount.m_value);
}
void xorNotLeftShift64(RegisterID n, RegisterID m, TrustedImm32 amount, RegisterID d)
{
m_assembler.eon<64>(d, n, m, Assembler::LSL, amount.m_value);
}
void xorNotRightShift64(RegisterID n, RegisterID m, TrustedImm32 amount, RegisterID d)
{
m_assembler.eon<64>(d, n, m, Assembler::ASR, amount.m_value);
}
void xorNotUnsignedRightShift64(RegisterID n, RegisterID m, TrustedImm32 amount, RegisterID d)
{
m_assembler.eon<64>(d, n, m, Assembler::LSR, amount.m_value);
}
void extractInsertBitfieldAtLowEnd32(RegisterID src, TrustedImm32 lsb, TrustedImm32 width, RegisterID dest)
{
m_assembler.bfxil<32>(dest, src, lsb.m_value, width.m_value);
}
void extractInsertBitfieldAtLowEnd64(RegisterID src, TrustedImm32 lsb, TrustedImm32 width, RegisterID dest)
{
m_assembler.bfxil<64>(dest, src, lsb.m_value, width.m_value);
}
void insertSignedBitfieldInZero32(RegisterID src, TrustedImm32 lsb, TrustedImm32 width, RegisterID dest)
{
m_assembler.sbfiz<32>(dest, src, lsb.m_value, width.m_value);
}
void insertSignedBitfieldInZero64(RegisterID src, TrustedImm32 lsb, TrustedImm32 width, RegisterID dest)
{
m_assembler.sbfiz<64>(dest, src, lsb.m_value, width.m_value);
}
void extractSignedBitfield32(RegisterID src, TrustedImm32 lsb, TrustedImm32 width, RegisterID dest)
{
m_assembler.sbfx<32>(dest, src, lsb.m_value, width.m_value);
}
void extractSignedBitfield64(RegisterID src, TrustedImm32 lsb, TrustedImm32 width, RegisterID dest)
{
m_assembler.sbfx<64>(dest, src, lsb.m_value, width.m_value);
}
void extractRegister32(RegisterID n, RegisterID m, TrustedImm32 lsb, RegisterID d)
{
m_assembler.extr<32>(d, n, m, lsb.m_value);
}
void extractRegister64(RegisterID n, RegisterID m, TrustedImm32 lsb, RegisterID d)
{
m_assembler.extr<64>(d, n, m, lsb.m_value);
}
void addLeftShift32(RegisterID n, RegisterID m, TrustedImm32 amount, RegisterID d)
{
m_assembler.add<32>(d, n, m, Assembler::LSL, amount.m_value);
}
void addRightShift32(RegisterID n, RegisterID m, TrustedImm32 amount, RegisterID d)
{
m_assembler.add<32>(d, n, m, Assembler::ASR, amount.m_value);
}
void addUnsignedRightShift32(RegisterID n, RegisterID m, TrustedImm32 amount, RegisterID d)
{
m_assembler.add<32>(d, n, m, Assembler::LSR, amount.m_value);
}
void addLeftShift64(RegisterID n, RegisterID m, TrustedImm32 amount, RegisterID d)
{
m_assembler.add<64>(d, n, m, Assembler::LSL, amount.m_value);
}
void addRightShift64(RegisterID n, RegisterID m, TrustedImm32 amount, RegisterID d)
{
m_assembler.add<64>(d, n, m, Assembler::ASR, amount.m_value);
}
void addUnsignedRightShift64(RegisterID n, RegisterID m, TrustedImm32 amount, RegisterID d)
{
m_assembler.add<64>(d, n, m, Assembler::LSR, amount.m_value);
}
void subLeftShift32(RegisterID n, RegisterID m, TrustedImm32 amount, RegisterID d)
{
m_assembler.sub<32>(d, n, m, Assembler::LSL, amount.m_value);
}
void subRightShift32(RegisterID n, RegisterID m, TrustedImm32 amount, RegisterID d)
{
m_assembler.sub<32>(d, n, m, Assembler::ASR, amount.m_value);
}
void subUnsignedRightShift32(RegisterID n, RegisterID m, TrustedImm32 amount, RegisterID d)
{
m_assembler.sub<32>(d, n, m, Assembler::LSR, amount.m_value);
}
void subLeftShift64(RegisterID n, RegisterID m, TrustedImm32 amount, RegisterID d)
{
m_assembler.sub<64>(d, n, m, Assembler::LSL, amount.m_value);
}
void subRightShift64(RegisterID n, RegisterID m, TrustedImm32 amount, RegisterID d)
{
m_assembler.sub<64>(d, n, m, Assembler::ASR, amount.m_value);
}
void subUnsignedRightShift64(RegisterID n, RegisterID m, TrustedImm32 amount, RegisterID d)
{
m_assembler.sub<64>(d, n, m, Assembler::LSR, amount.m_value);
}
void andLeftShift32(RegisterID n, RegisterID m, TrustedImm32 amount, RegisterID d)
{
m_assembler.and_<32>(d, n, m, Assembler::LSL, amount.m_value);
}
void andRightShift32(RegisterID n, RegisterID m, TrustedImm32 amount, RegisterID d)
{
m_assembler.and_<32>(d, n, m, Assembler::ASR, amount.m_value);
}
void andUnsignedRightShift32(RegisterID n, RegisterID m, TrustedImm32 amount, RegisterID d)
{
m_assembler.and_<32>(d, n, m, Assembler::LSR, amount.m_value);
}
void andLeftShift64(RegisterID n, RegisterID m, TrustedImm32 amount, RegisterID d)
{
m_assembler.and_<64>(d, n, m, Assembler::LSL, amount.m_value);
}
void andRightShift64(RegisterID n, RegisterID m, TrustedImm32 amount, RegisterID d)
{
m_assembler.and_<64>(d, n, m, Assembler::ASR, amount.m_value);
}
void andUnsignedRightShift64(RegisterID n, RegisterID m, TrustedImm32 amount, RegisterID d)
{
m_assembler.and_<64>(d, n, m, Assembler::LSR, amount.m_value);
}
void xorLeftShift32(RegisterID n, RegisterID m, TrustedImm32 amount, RegisterID d)
{
m_assembler.eor<32>(d, n, m, Assembler::LSL, amount.m_value);
}
void xorRightShift32(RegisterID n, RegisterID m, TrustedImm32 amount, RegisterID d)
{
m_assembler.eor<32>(d, n, m, Assembler::ASR, amount.m_value);
}
void xorUnsignedRightShift32(RegisterID n, RegisterID m, TrustedImm32 amount, RegisterID d)
{
m_assembler.eor<32>(d, n, m, Assembler::LSR, amount.m_value);
}
void xorLeftShift64(RegisterID n, RegisterID m, TrustedImm32 amount, RegisterID d)
{
m_assembler.eor<64>(d, n, m, Assembler::LSL, amount.m_value);
}
void xorRightShift64(RegisterID n, RegisterID m, TrustedImm32 amount, RegisterID d)
{
m_assembler.eor<64>(d, n, m, Assembler::ASR, amount.m_value);
}
void xorUnsignedRightShift64(RegisterID n, RegisterID m, TrustedImm32 amount, RegisterID d)
{
m_assembler.eor<64>(d, n, m, Assembler::LSR, amount.m_value);
}
void orLeftShift32(RegisterID n, RegisterID m, TrustedImm32 amount, RegisterID d)
{
m_assembler.orr<32>(d, n, m, Assembler::LSL, amount.m_value);
}
void orRightShift32(RegisterID n, RegisterID m, TrustedImm32 amount, RegisterID d)
{
m_assembler.orr<32>(d, n, m, Assembler::ASR, amount.m_value);
}
void orUnsignedRightShift32(RegisterID n, RegisterID m, TrustedImm32 amount, RegisterID d)
{
m_assembler.orr<32>(d, n, m, Assembler::LSR, amount.m_value);
}
void orLeftShift64(RegisterID n, RegisterID m, TrustedImm32 amount, RegisterID d)
{
m_assembler.orr<64>(d, n, m, Assembler::LSL, amount.m_value);
}
void orRightShift64(RegisterID n, RegisterID m, TrustedImm32 amount, RegisterID d)
{
m_assembler.orr<64>(d, n, m, Assembler::ASR, amount.m_value);
}
void orUnsignedRightShift64(RegisterID n, RegisterID m, TrustedImm32 amount, RegisterID d)
{
m_assembler.orr<64>(d, n, m, Assembler::LSR, amount.m_value);
}
void clearBit64(RegisterID bitToClear, RegisterID dest, RegisterID scratchForMask = InvalidGPRReg)
{
if (scratchForMask == InvalidGPRReg)
scratchForMask = scratchRegister();
move(TrustedImm32(1), scratchForMask);
lshift64(bitToClear, scratchForMask);
clearBits64WithMask(scratchForMask, dest);
}
enum class ClearBitsAttributes {
OKToClobberMask,
MustPreserveMask
};
void clearBits64WithMask(RegisterID mask, RegisterID dest, ClearBitsAttributes = ClearBitsAttributes::OKToClobberMask)
{
clearBits64WithMask(dest, mask, dest);
}
void clearBits64WithMask(RegisterID src, RegisterID mask, RegisterID dest, ClearBitsAttributes = ClearBitsAttributes::OKToClobberMask)
{
m_assembler.bic<64>(dest, src, mask);
}
void countLeadingZeros32(RegisterID src, RegisterID dest)
{
m_assembler.clz<32>(dest, src);
}
void countLeadingZeros64(RegisterID src, RegisterID dest)
{
m_assembler.clz<64>(dest, src);
}
void countTrailingZeros32(RegisterID src, RegisterID dest)
{
// Arm does not have a count trailing zeros only a count leading zeros.
m_assembler.rbit<32>(dest, src);
m_assembler.clz<32>(dest, dest);
}
void countTrailingZeros64(RegisterID src, RegisterID dest)
{
// Arm does not have a count trailing zeros only a count leading zeros.
m_assembler.rbit<64>(dest, src);
m_assembler.clz<64>(dest, dest);
}
void countTrailingZeros64WithoutNullCheck(RegisterID src, RegisterID dest)
{
#if ASSERT_ENABLED
Jump notZero = branchTest64(NonZero, src);
abortWithReason(MacroAssemblerOops, __LINE__);
notZero.link(this);
#endif
// Arm did not need an explicit null check to begin with. So, we can do
// exactly the same thing as in countTrailingZeros64().
countTrailingZeros64(src, dest);
}
void byteSwap16(RegisterID dst)
{
m_assembler.rev16<32>(dst, dst);
zeroExtend16To32(dst, dst);
}
void byteSwap32(RegisterID dst)
{
m_assembler.rev<32>(dst, dst);
}
void byteSwap64(RegisterID dst)
{
m_assembler.rev<64>(dst, dst);
}
// Only used for testing purposes.
void illegalInstruction()
{
m_assembler.illegalInstruction();
}
void lshift32(RegisterID src, RegisterID shiftAmount, RegisterID dest)
{
m_assembler.lsl<32>(dest, src, shiftAmount);
}
void lshift32(RegisterID src, TrustedImm32 imm, RegisterID dest)
{
m_assembler.lsl<32>(dest, src, imm.m_value & 0x1f);
}
void lshift32(RegisterID shiftAmount, RegisterID dest)
{
lshift32(dest, shiftAmount, dest);
}
void lshift32(TrustedImm32 imm, RegisterID dest)
{
lshift32(dest, imm, dest);
}
void lshift32(Address src, RegisterID shiftAmount, RegisterID dest)
{
load32(src, getCachedDataTempRegisterIDAndInvalidate());
m_assembler.lsl<32>(dest, dataTempRegister, shiftAmount);
}
void lshift64(RegisterID src, RegisterID shiftAmount, RegisterID dest)
{
m_assembler.lsl<64>(dest, src, shiftAmount);
}
void lshift64(RegisterID src, TrustedImm32 imm, RegisterID dest)
{
m_assembler.lsl<64>(dest, src, imm.m_value & 0x3f);
}
void lshift64(RegisterID shiftAmount, RegisterID dest)
{
lshift64(dest, shiftAmount, dest);
}
void lshift64(TrustedImm32 imm, RegisterID dest)
{
lshift64(dest, imm, dest);
}
void lshift64(Address src, RegisterID shiftAmount, RegisterID dest)
{
load64(src, getCachedDataTempRegisterIDAndInvalidate());
m_assembler.lsl<64>(dest, dataTempRegister, shiftAmount);
}
void mul32(RegisterID left, RegisterID right, RegisterID dest)
{
m_assembler.mul<32>(dest, left, right);
}
void mul32(RegisterID src, RegisterID dest)
{
m_assembler.mul<32>(dest, dest, src);
}
void mul32(TrustedImm32 imm, RegisterID src, RegisterID dest)
{
move(imm, getCachedDataTempRegisterIDAndInvalidate());
m_assembler.mul<32>(dest, src, dataTempRegister);
}
void mul64(RegisterID src, RegisterID dest)
{
m_assembler.mul<64>(dest, dest, src);
}
void mul64(RegisterID left, RegisterID right, RegisterID dest)
{
m_assembler.mul<64>(dest, left, right);
}
void multiplyAdd32(RegisterID mulLeft, RegisterID mulRight, RegisterID summand, RegisterID dest)
{
m_assembler.madd<32>(dest, mulLeft, mulRight, summand);
}
void multiplySub32(RegisterID mulLeft, RegisterID mulRight, RegisterID minuend, RegisterID dest)
{
m_assembler.msub<32>(dest, mulLeft, mulRight, minuend);
}
void multiplyNeg32(RegisterID mulLeft, RegisterID mulRight, RegisterID dest)
{
m_assembler.mneg<32>(dest, mulLeft, mulRight);
}
void multiplyAdd64(RegisterID mulLeft, RegisterID mulRight, RegisterID summand, RegisterID dest)
{
m_assembler.madd<64>(dest, mulLeft, mulRight, summand);
}
void multiplyAddSignExtend32(RegisterID mulLeft, RegisterID mulRight, RegisterID summand, RegisterID dest)
{
m_assembler.smaddl(dest, mulLeft, mulRight, summand);
}
void multiplyAddZeroExtend32(RegisterID mulLeft, RegisterID mulRight, RegisterID summand, RegisterID dest)
{
m_assembler.umaddl(dest, mulLeft, mulRight, summand);
}
void multiplySub64(RegisterID mulLeft, RegisterID mulRight, RegisterID minuend, RegisterID dest)
{
m_assembler.msub<64>(dest, mulLeft, mulRight, minuend);
}
void multiplySubSignExtend32(RegisterID mulLeft, RegisterID mulRight, RegisterID minuend, RegisterID dest)
{
m_assembler.smsubl(dest, mulLeft, mulRight, minuend);
}
void multiplySubZeroExtend32(RegisterID mulLeft, RegisterID mulRight, RegisterID minuend, RegisterID dest)
{
m_assembler.umsubl(dest, mulLeft, mulRight, minuend);
}
void multiplyNeg64(RegisterID mulLeft, RegisterID mulRight, RegisterID dest)
{
m_assembler.mneg<64>(dest, mulLeft, mulRight);
}
void multiplyNegSignExtend32(RegisterID mulLeft, RegisterID mulRight, RegisterID dest)
{
m_assembler.smnegl(dest, mulLeft, mulRight);
}
void multiplyNegZeroExtend32(RegisterID mulLeft, RegisterID mulRight, RegisterID dest)
{
m_assembler.umnegl(dest, mulLeft, mulRight);
}
void multiplySignExtend32(RegisterID left, RegisterID right, RegisterID dest)
{
m_assembler.smull(dest, left, right);
}
void multiplyZeroExtend32(RegisterID left, RegisterID right, RegisterID dest)
{
m_assembler.umull(dest, left, right);