/
AirOpcode.opcodes
1490 lines (1160 loc) · 34.4 KB
/
AirOpcode.opcodes
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
# Copyright (C) 2015-2017 Apple Inc. All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
# are met:
# 1. Redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer.
# 2. Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution.
#
# THIS SOFTWARE IS PROVIDED BY APPLE INC. AND ITS CONTRIBUTORS ``AS IS''
# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL APPLE INC. OR ITS CONTRIBUTORS
# BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
# THE POSSIBILITY OF SUCH DAMAGE.
# Syllabus:
#
# Examples of some roles, types, and widths:
# U:G:32 => use of the low 32 bits of a general-purpose register or value
# D:G:32 => def of the low 32 bits of a general-purpose register or value
# UD:G:32 => use and def of the low 32 bits of a general-purpose register or value
# U:G:64 => use of the low 64 bits of a general-purpose register or value
# ZD:G:32 => def of all bits of a general-purpose register, where all but the low 32 bits are guaranteed to be zeroed.
# UA:G:Ptr => UseAddr (see comment in Arg.h)
# U:F:32 => use of a float register or value
# U:F:64 => use of a double register or value
# D:F:32 => def of a float register or value
# UD:F:32 => use and def of a float register or value
# S:F:32 => scratch float register.
#
# Argument kinds:
# Tmp => temporary or register
# Imm => 32-bit immediate int
# BigImm => TrustedImm64
# Addr => address as temporary/register+offset
# Index => BaseIndex address
# Abs => AbsoluteAddress
#
# The parser views these things as keywords, and understands that they fall into two distinct classes
# of things. So, although this file uses a particular indentation style, none of the whitespace or
# even newlines are meaningful to the parser. For example, you could write:
#
# Foo42 U:G:32, UD:F:32 Imm, Tmp Addr, Tmp
#
# And the parser would know that this is the same as:
#
# Foo42 U:G:32, UD:F:32
# Imm, Tmp
# Addr, Tmp
#
# I.e. a two-form instruction that uses a GPR or an int immediate and uses+defs a float register.
#
# Any opcode or opcode form can be preceded with an architecture list, which restricts the opcode to the
# union of those architectures. For example, if this is the only overload of the opcode, then it makes the
# opcode only available on x86_64:
#
# x86_64: Fuzz UD:G:64, D:G:64
# Tmp, Tmp
# Tmp, Addr
#
# But this only restricts the two-operand form, the other form is allowed on all architectures:
#
# x86_64: Fuzz UD:G:64, D:G:64
# Tmp, Tmp
# Tmp, Addr
# Fuzz UD:G:Ptr, D:G:Ptr, U:F:Ptr
# Tmp, Tmp, Tmp
# Tmp, Addr, Tmp
#
# And you can also restrict individual forms:
#
# Thingy UD:G:32, D:G:32
# Tmp, Tmp
# arm64: Tmp, Addr
#
# Additionally, you can have an intersection between the architectures of the opcode overload and the
# form. In this example, the version that takes an address is only available on armv7 while the other
# versions are available on armv7 or x86_64:
#
# x86_64 armv7: Buzz U:G:32, UD:F:32
# Tmp, Tmp
# Imm, Tmp
# armv7: Addr, Tmp
#
# Finally, you can specify architectures using helpful architecture groups. Here are all of the
# architecture keywords that we support:
#
# x86: means x86-32 or x86-64.
# x86_32: means just x86-32.
# x86_64: means just x86-64.
# arm: means armv7 or arm64.
# armv7: means just armv7.
# arm64: means just arm64.
# 32: means x86-32 or armv7.
# 64: means x86-64 or arm64.
# Note that the opcodes here have a leading capital (Add32) but must correspond to MacroAssembler
# API that has a leading lower-case (add32).
Nop
Add32 U:G:32, U:G:32, ZD:G:32
Imm, Tmp, Tmp
Tmp, Tmp, Tmp
Add32 U:G:32, UZD:G:32
Tmp, Tmp
x86: Imm, Addr
x86: Imm, Index
Imm, Tmp
x86: Addr, Tmp
x86: Index, Tmp
x86: Tmp, Addr
x86: Tmp, Index
x86: Add8 U:G:8, UD:G:8
Imm, Addr
Imm, Index
Tmp, Addr
Tmp, Index
x86: Add16 U:G:16, UD:G:16
Imm, Addr
Imm, Index
Tmp, Addr
Tmp, Index
64: Add64 U:G:64, UD:G:64
Tmp, Tmp
x86: Imm, Addr
x86: Imm, Index
Imm, Tmp
x86: Addr, Tmp
x86: Index, Tmp
x86: Tmp, Addr
x86: Tmp, Index
64: Add64 U:G:64, U:G:64, D:G:64
Imm, Tmp, Tmp
Tmp, Tmp, Tmp
AddDouble U:F:64, U:F:64, D:F:64
Tmp, Tmp, Tmp
x86: Addr, Tmp, Tmp
x86: Tmp, Addr, Tmp
x86: Index, Tmp, Tmp
x86: AddDouble U:F:64, UD:F:64
Tmp, Tmp
Addr, Tmp
AddFloat U:F:32, U:F:32, D:F:32
Tmp, Tmp, Tmp
x86: Addr, Tmp, Tmp
x86: Tmp, Addr, Tmp
x86: Index, Tmp, Tmp
x86: AddFloat U:F:32, UD:F:32
Tmp, Tmp
Addr, Tmp
Sub32 U:G:32, UZD:G:32
Tmp, Tmp
x86: Imm, Addr
x86: Imm, Index
Imm, Tmp
x86: Addr, Tmp
x86: Index, Tmp
x86: Tmp, Addr
x86: Tmp, Index
arm64: Sub32 U:G:32, U:G:32, ZD:G:32
Tmp, Tmp, Tmp
Tmp, Imm, Tmp
64: Sub64 U:G:64, UD:G:64
Tmp, Tmp
x86: Imm, Addr
x86: Imm, Index
Imm, Tmp
x86: Addr, Tmp
x86: Index, Tmp
x86: Tmp, Addr
x86: Tmp, Index
arm64: Sub64 U:G:64, U:G:64, D:G:64
Tmp, Tmp, Tmp
Tmp, Imm, Tmp
SubDouble U:F:64, U:F:64, D:F:64
arm64: Tmp, Tmp, Tmp
x86: Tmp, Addr, Tmp
x86: Tmp, Index, Tmp
x86: SubDouble U:F:64, UD:F:64
Tmp, Tmp
Addr, Tmp
SubFloat U:F:32, U:F:32, D:F:32
arm64: Tmp, Tmp, Tmp
x86: Tmp, Addr, Tmp
x86: Tmp, Index, Tmp
x86: SubFloat U:F:32, UD:F:32
Tmp, Tmp
Addr, Tmp
Neg32 UZD:G:32
Tmp
x86: Addr
x86: Index
64: Neg64 UD:G:64
Tmp
x86: Addr
x86: Index
arm64: NegateDouble U:F:64, D:F:64
Tmp, Tmp
arm64: NegateFloat U:F:32, D:F:32
Tmp, Tmp
Mul32 U:G:32, UZD:G:32
Tmp, Tmp
x86: Addr, Tmp
Mul32 U:G:32, U:G:32, ZD:G:32
Tmp, Tmp, Tmp
x86: Addr, Tmp, Tmp
x86: Tmp, Addr, Tmp
x86: Imm, Tmp, Tmp
64: Mul64 U:G:64, UD:G:64
Tmp, Tmp
Mul64 U:G:64, U:G:64, D:G:64
Tmp, Tmp, Tmp
arm64: MultiplyAdd32 U:G:32, U:G:32, U:G:32, ZD:G:32
Tmp, Tmp, Tmp, Tmp
arm64: MultiplyAdd64 U:G:64, U:G:64, U:G:64, D:G:64
Tmp, Tmp, Tmp, Tmp
arm64: MultiplyAddSignExtend32 U:G:32, U:G:32, U:G:64, D:G:64
Tmp, Tmp, Tmp, Tmp
arm64: MultiplySub32 U:G:32, U:G:32, U:G:32, ZD:G:32
Tmp, Tmp, Tmp, Tmp
arm64: MultiplySub64 U:G:64, U:G:64, U:G:64, D:G:64
Tmp, Tmp, Tmp, Tmp
arm64: MultiplySubSignExtend32 U:G:32, U:G:32, U:G:64, D:G:64
Tmp, Tmp, Tmp, Tmp
arm64: MultiplyNeg32 U:G:32, U:G:32, ZD:G:32
Tmp, Tmp, Tmp
arm64: MultiplyNeg64 U:G:64, U:G:64, ZD:G:64
Tmp, Tmp, Tmp
arm64: MultiplySignExtend32 U:G:32, U:G:32, ZD:G:64
Tmp, Tmp, Tmp
arm64: Div32 U:G:32, U:G:32, ZD:G:32
Tmp, Tmp, Tmp
arm64: UDiv32 U:G:32, U:G:32, ZD:G:32
Tmp, Tmp, Tmp
arm64: Div64 U:G:64, U:G:64, D:G:64
Tmp, Tmp, Tmp
arm64: UDiv64 U:G:64, U:G:64, D:G:64
Tmp, Tmp, Tmp
MulDouble U:F:64, U:F:64, D:F:64
Tmp, Tmp, Tmp
x86: Addr, Tmp, Tmp
x86: Tmp, Addr, Tmp
x86: Index, Tmp, Tmp
x86: MulDouble U:F:64, UD:F:64
Tmp, Tmp
Addr, Tmp
MulFloat U:F:32, U:F:32, D:F:32
Tmp, Tmp, Tmp
x86: Addr, Tmp, Tmp
x86: Tmp, Addr, Tmp
x86: Index, Tmp, Tmp
x86: MulFloat U:F:32, UD:F:32
Tmp, Tmp
Addr, Tmp
arm64: DivDouble U:F:64, U:F:32, D:F:64
Tmp, Tmp, Tmp
x86: DivDouble U:F:64, UD:F:64
Tmp, Tmp
Addr, Tmp
arm64: DivFloat U:F:32, U:F:32, D:F:32
Tmp, Tmp, Tmp
x86: DivFloat U:F:32, UD:F:32
Tmp, Tmp
Addr, Tmp
x86: X86ConvertToDoubleWord32 U:G:32, ZD:G:32
Tmp*, Tmp*
x86_64: X86ConvertToQuadWord64 U:G:64, D:G:64
Tmp*, Tmp*
x86: X86Div32 UZD:G:32, UZD:G:32, U:G:32
Tmp*, Tmp*, Tmp
x86: X86UDiv32 UZD:G:32, UZD:G:32, U:G:32
Tmp*, Tmp*, Tmp
x86_64: X86Div64 UZD:G:64, UZD:G:64, U:G:64
Tmp*, Tmp*, Tmp
x86_64: X86UDiv64 UZD:G:64, UZD:G:64, U:G:64
Tmp*, Tmp*, Tmp
# If we add other things like Lea that are UA, we may need to lower
# them on arm64 similarly to how we do for Lea. In lowerStackArgs,
# we lower Lea to add on arm64.
Lea32 UA:G:32, D:G:32
Addr, Tmp
x86: Index, Tmp as x86Lea32
Lea64 UA:G:64, D:G:64
Addr, Tmp
x86: Index, Tmp as x86Lea64
And32 U:G:32, U:G:32, ZD:G:32
Tmp, Tmp, Tmp
arm64: BitImm, Tmp, Tmp
x86: Tmp, Addr, Tmp
x86: Addr, Tmp, Tmp
And32 U:G:32, UZD:G:32
Tmp, Tmp
x86: Imm, Tmp
x86: Tmp, Addr
x86: Tmp, Index
x86: Addr, Tmp
x86: Index, Tmp
x86: Imm, Addr
x86: Imm, Index
64: And64 U:G:64, U:G:64, D:G:64
Tmp, Tmp, Tmp
arm64: BitImm64, Tmp, Tmp
x86_64: And64 U:G:64, UD:G:64
Tmp, Tmp
Imm, Tmp
Imm, Addr
Imm, Index
Tmp, Addr
Tmp, Index
Addr, Tmp
Index, Tmp
AndDouble U:F:64, U:F:64, D:F:64
Tmp, Tmp, Tmp
x86: AndDouble U:F:64, UD:F:64
Tmp, Tmp
AndFloat U:F:32, U:F:32, D:F:32
Tmp, Tmp, Tmp
x86: AndFloat U:F:32, UD:F:32
Tmp, Tmp
OrDouble U:F:64, U:F:64, D:F:64
Tmp, Tmp, Tmp
x86: OrDouble U:F:64, UD:F:64
Tmp, Tmp
OrFloat U:F:32, U:F:32, D:F:32
Tmp, Tmp, Tmp
x86: OrFloat U:F:32, UD:F:32
Tmp, Tmp
x86: XorDouble U:F:64, U:F:64, D:F:64
Tmp, Tmp, Tmp
x86: XorDouble U:F:64, UD:F:64
Tmp, Tmp
x86: XorFloat U:F:32, U:F:32, D:F:32
Tmp, Tmp, Tmp
x86: XorFloat U:F:32, UD:F:32
Tmp, Tmp
arm64: Lshift32 U:G:32, U:G:32, ZD:G:32
Tmp, Tmp, Tmp
Tmp, Imm, Tmp
x86:Lshift32 U:G:32, UZD:G:32
Tmp*, Tmp
Imm, Tmp
arm64: Lshift64 U:G:64, U:G:64, D:G:64
Tmp, Tmp, Tmp
Tmp, Imm, Tmp
x86_64: Lshift64 U:G:64, UD:G:64
Tmp*, Tmp
Imm, Tmp
arm64: Rshift32 U:G:32, U:G:32, ZD:G:32
Tmp, Tmp, Tmp
Tmp, Imm, Tmp
x86: Rshift32 U:G:32, UZD:G:32
Tmp*, Tmp
Imm, Tmp
arm64: Rshift64 U:G:64, U:G:64, D:G:64
Tmp, Tmp, Tmp
Tmp, Imm, Tmp
x86_64: Rshift64 U:G:64, UD:G:64
Tmp*, Tmp
Imm, Tmp
arm64: Urshift32 U:G:32, U:G:32, ZD:G:32
Tmp, Tmp, Tmp
Tmp, Imm, Tmp
x86: Urshift32 U:G:32, UZD:G:32
Tmp*, Tmp
Imm, Tmp
arm64: Urshift64 U:G:64, U:G:64, D:G:64
Tmp, Tmp, Tmp
Tmp, Imm, Tmp
x86_64: Urshift64 U:G:64, UD:G:64
Tmp*, Tmp
Imm, Tmp
x86_64: RotateRight32 U:G:32, UZD:G:32
Tmp*, Tmp
Imm, Tmp
arm64: RotateRight32 U:G:32, U:G:32, ZD:G:32
Tmp, Tmp, Tmp
Tmp, Imm, Tmp
x86_64: RotateRight64 U:G:64, UD:G:64
Tmp*, Tmp
Imm, Tmp
arm64: RotateRight64 U:G:64, U:G:64, D:G:64
Tmp, Tmp, Tmp
Tmp, Imm, Tmp
x86_64: RotateLeft32 U:G:32, UZD:G:32
Tmp*, Tmp
Imm, Tmp
x86_64: RotateLeft64 U:G:64, UD:G:64
Tmp*, Tmp
Imm, Tmp
Or32 U:G:32, U:G:32, ZD:G:32
Tmp, Tmp, Tmp
arm64: BitImm, Tmp, Tmp
x86: Tmp, Addr, Tmp
x86: Addr, Tmp, Tmp
Or32 U:G:32, UZD:G:32
Tmp, Tmp
x86: Imm, Tmp
x86: Tmp, Addr
x86: Tmp, Index
x86: Addr, Tmp
x86: Index, Tmp
x86: Imm, Addr
x86: Imm, Index
64: Or64 U:G:64, U:G:64, D:G:64
Tmp, Tmp, Tmp
arm64: BitImm64, Tmp, Tmp
64: Or64 U:G:64, UD:G:64
Tmp, Tmp
x86: Imm, Tmp
x86: Imm, Addr
x86: Imm, Index
x86: Tmp, Addr
x86: Tmp, Index
x86: Addr, Tmp
x86: Index, Tmp
Xor32 U:G:32, U:G:32, ZD:G:32
Tmp, Tmp, Tmp
arm64: BitImm, Tmp, Tmp
x86: Tmp, Addr, Tmp
x86: Addr, Tmp, Tmp
Xor32 U:G:32, UZD:G:32
Tmp, Tmp
x86: Imm, Tmp
x86: Tmp, Addr
x86: Tmp, Index
x86: Addr, Tmp
x86: Index, Tmp
x86: Imm, Addr
x86: Imm, Index
64: Xor64 U:G:64, U:G:64, D:G:64
Tmp, Tmp, Tmp
arm64: BitImm64, Tmp, Tmp
64: Xor64 U:G:64, UD:G:64
Tmp, Tmp
x86: Tmp, Addr
x86: Tmp, Index
x86: Addr, Tmp
x86: Index, Tmp
x86: Imm, Addr
x86: Imm, Index
x86: Imm, Tmp
arm64: Not32 U:G:32, ZD:G:32
Tmp, Tmp
x86: Not32 UZD:G:32
Tmp
Addr
Index
arm64: Not64 U:G:64, D:G:64
Tmp, Tmp
x86_64: Not64 UD:G:64
Tmp
Addr
Index
arm64: AbsDouble U:F:64, D:F:64
Tmp, Tmp
arm64: AbsFloat U:F:32, D:F:32
Tmp, Tmp
CeilDouble U:F:64, D:F:64
Tmp, Tmp
x86: Addr, Tmp
CeilFloat U:F:32, D:F:32
Tmp, Tmp
x86: Addr, Tmp
FloorDouble U:F:64, D:F:64
Tmp, Tmp
x86: Addr, Tmp
FloorFloat U:F:32, D:F:32
Tmp, Tmp
x86: Addr, Tmp
SqrtDouble U:F:64, D:F:64
Tmp, Tmp
x86: Addr, Tmp
SqrtFloat U:F:32, D:F:32
Tmp, Tmp
x86: Addr, Tmp
ConvertInt32ToDouble U:G:32, D:F:64
Tmp, Tmp
x86: Addr, Tmp
64: ConvertInt64ToDouble U:G:64, D:F:64
Tmp, Tmp
x86_64: Addr, Tmp
ConvertInt32ToFloat U:G:32, D:F:32
Tmp, Tmp
x86: Addr, Tmp
64: ConvertInt64ToFloat U:G:64, D:F:32
Tmp, Tmp
x86_64: Addr, Tmp
CountLeadingZeros32 U:G:32, ZD:G:32
Tmp, Tmp
x86: Addr, Tmp
64: CountLeadingZeros64 U:G:64, D:G:64
Tmp, Tmp
x86: Addr, Tmp
ConvertDoubleToFloat U:F:64, D:F:32
Tmp, Tmp
x86: Addr, Tmp
ConvertFloatToDouble U:F:32, D:F:64
Tmp, Tmp
x86: Addr, Tmp
# Note that Move operates over the full register size, which is either 32-bit or 64-bit depending on
# the platform. I'm not entirely sure that this is a good thing; it might be better to just have a
# Move64 instruction. OTOH, our MacroAssemblers already have this notion of "move()" that basically
# means movePtr.
Move U:G:Ptr, D:G:Ptr
Tmp, Tmp
Imm, Tmp as signExtend32ToPtr
BigImm, Tmp
Addr, Tmp as loadPtr # This means that "Move Addr, Tmp" is code-generated as "load" not "move".
Index, Tmp as loadPtr
Tmp, Addr as storePtr
Tmp, Index as storePtr
x86: Imm, Addr as storePtr
# This is for moving between spill slots.
Move U:G:Ptr, D:G:Ptr, S:G:Ptr
Addr, Addr, Tmp
x86: Swap32 UD:G:32, UD:G:32
Tmp, Tmp
Tmp, Addr
x86_64: Swap64 UD:G:64, UD:G:64
Tmp, Tmp
Tmp, Addr
Move32 U:G:32, ZD:G:32
Tmp, Tmp as zeroExtend32ToWord
Addr, Tmp as load32
Index, Tmp as load32
Tmp, Addr as store32
Tmp, Index as store32
x86: Imm, Tmp as zeroExtend32ToWord
x86: Imm, Addr as store32
x86: Imm, Index as store32
# This is for moving between spill slots.
Move32 U:G:32, ZD:G:32, S:G:32
Addr, Addr, Tmp
# FIXME: StoreZero32 and StoreZero64 are hacks on ARM64, we can do better: https://bugs.webkit.org/show_bug.cgi?id=174821
StoreZero32 D:G:32
Addr
Index
64: StoreZero64 D:G:64
Addr
Index
SignExtend32ToPtr U:G:32, D:G:Ptr
Tmp, Tmp
ZeroExtend8To32 U:G:8, ZD:G:32
Tmp, Tmp
x86: Addr, Tmp as load8
x86: Index, Tmp as load8
SignExtend8To32 U:G:8, ZD:G:32
Tmp, Tmp
x86: Addr, Tmp as load8SignedExtendTo32
x86: Index, Tmp as load8SignedExtendTo32
ZeroExtend16To32 U:G:16, ZD:G:32
Tmp, Tmp
x86: Addr, Tmp as load16
x86: Index, Tmp as load16
SignExtend16To32 U:G:16, ZD:G:32
Tmp, Tmp
x86: Addr, Tmp as load16SignedExtendTo32
x86: Index, Tmp as load16SignedExtendTo32
MoveFloat U:F:32, D:F:32
Tmp, Tmp as moveDouble
Addr, Tmp as loadFloat
Index, Tmp as loadFloat
Tmp, Addr as storeFloat
Tmp, Index as storeFloat
MoveFloat U:F:32, D:F:32, S:F:32
Addr, Addr, Tmp
MoveDouble U:F:64, D:F:64
Tmp, Tmp
Addr, Tmp as loadDouble
Index, Tmp as loadDouble
Tmp, Addr as storeDouble
Tmp, Index as storeDouble
MoveDouble U:F:64, D:F:64, S:F:64
Addr, Addr, Tmp
MoveZeroToDouble D:F:64
Tmp
64: Move64ToDouble U:G:64, D:F:64
Tmp, Tmp
x86: Addr, Tmp as loadDouble
Index, Tmp as loadDouble
Move32ToFloat U:G:32, D:F:32
Tmp, Tmp
x86: Addr, Tmp as loadFloat
Index, Tmp as loadFloat
64: MoveDoubleTo64 U:F:64, D:G:64
Tmp, Tmp
Addr, Tmp as load64
Index, Tmp as load64
MoveFloatTo32 U:F:32, D:G:32
Tmp, Tmp
Addr, Tmp as load32
Index, Tmp as load32
Load8 U:G:8, ZD:G:32
Addr, Tmp
Index, Tmp
arm: LoadAcq8 U:G:8, ZD:G:32 /effects
SimpleAddr, Tmp
Store8 U:G:8, D:G:8
Tmp, Index
Tmp, Addr
x86: Imm, Index
x86: Imm, Addr
arm: StoreRel8 U:G:8, D:G:8 /effects
Tmp, SimpleAddr
Load8SignedExtendTo32 U:G:8, ZD:G:32
Addr, Tmp
Index, Tmp
arm: LoadAcq8SignedExtendTo32 U:G:8, ZD:G:32 /effects
SimpleAddr, Tmp
Load16 U:G:16, ZD:G:32
Addr, Tmp
Index, Tmp
arm: LoadAcq16 U:G:16, ZD:G:32 /effects
SimpleAddr, Tmp
Load16SignedExtendTo32 U:G:16, ZD:G:32
Addr, Tmp
Index, Tmp
arm: LoadAcq16SignedExtendTo32 U:G:16, ZD:G:32 /effects
SimpleAddr, Tmp
Store16 U:G:16, D:G:16
Tmp, Index
Tmp, Addr
x86: Imm, Index
x86: Imm, Addr
arm: StoreRel16 U:G:16, D:G:16 /effects
Tmp, SimpleAddr
arm: LoadAcq32 U:G:32, ZD:G:32 /effects
SimpleAddr, Tmp
arm: StoreRel32 U:G:32, ZD:G:32 /effects
Tmp, SimpleAddr
arm64: LoadAcq64 U:G:64, ZD:G:64 /effects
SimpleAddr, Tmp
arm64: StoreRel64 U:G:64, ZD:G:64 /effects
Tmp, SimpleAddr
x86: Xchg8 UD:G:8, UD:G:8 /effects
Tmp, Addr
Tmp, Index
x86: Xchg16 UD:G:16, UD:G:16 /effects
Tmp, Addr
Tmp, Index
x86: Xchg32 UD:G:32, UD:G:32 /effects
Tmp, Addr
Tmp, Index
x86_64: Xchg64 UD:G:64, UD:G:64 /effects
Tmp, Addr
Tmp, Index
arm64: ExtractUnsignedBitfield32 U:G:32, U:G:32, U:G:32, ZD:G:32
Tmp, Imm, Imm, Tmp
arm64: ExtractUnsignedBitfield64 U:G:64, U:G:32, U:G:32, D:G:64
Tmp, Imm, Imm, Tmp
arm64: InsertUnsignedBitfieldInZero32 U:G:32, U:G:32, U:G:32, ZD:G:32
Tmp, Imm, Imm, Tmp
arm64: InsertUnsignedBitfieldInZero64 U:G:64, U:G:32, U:G:32, D:G:64
Tmp, Imm, Imm, Tmp
arm64: InsertBitField32 U:G:32, U:G:32, U:G:32, UZD:G:32
Tmp, Imm, Imm, Tmp
arm64: InsertBitField64 U:G:64, U:G:32, U:G:32, UD:G:64
Tmp, Imm, Imm, Tmp
arm64: ClearBitField32 U:G:32, U:G:32, ZD:G:32
Imm, Imm, Tmp
arm64: ClearBitField64 U:G:32, U:G:32, D:G:64
Imm, Imm, Tmp
arm64: ClearBitsWithMask32 U:G:32, U:G:32, ZD:G:32
Tmp, Tmp, Tmp
arm64: ClearBitsWithMask64 U:G:64, U:G:64, D:G:64
Tmp, Tmp, Tmp
arm64: OrNot32 U:G:32, U:G:32, ZD:G:32
Tmp, Tmp, Tmp
arm64: OrNot64 U:G:64, U:G:64, D:G:64
Tmp, Tmp, Tmp
arm64: ExtractInsertBitfieldAtLowEnd32 U:G:32, U:G:32, U:G:32, UZD:G:32
Tmp, Imm, Imm, Tmp
arm64: ExtractInsertBitfieldAtLowEnd64 U:G:64, U:G:32, U:G:32, UD:G:64
Tmp, Imm, Imm, Tmp
arm64: InsertSignedBitfieldInZero32 U:G:32, U:G:32, U:G:32, ZD:G:32
Tmp, Imm, Imm, Tmp
arm64: InsertSignedBitfieldInZero64 U:G:64, U:G:32, U:G:32, D:G:64
Tmp, Imm, Imm, Tmp
arm64: ExtractSignedBitfield32 U:G:32, U:G:32, U:G:32, ZD:G:32
Tmp, Imm, Imm, Tmp
arm64: ExtractSignedBitfield64 U:G:64, U:G:32, U:G:32, D:G:64
Tmp, Imm, Imm, Tmp
arm64: ExtractRegister32 U:G:32, U:G:32, U:G:32, ZD:G:32
Tmp, Tmp, Imm, Tmp
arm64: ExtractRegister64 U:G:64, U:G:32, U:G:32, D:G:64
Tmp, Tmp, Imm, Tmp
# The first operand is rax.
# FIXME: This formulation means that the boolean result cannot be put in eax, even though all users
# of this would be OK with that.
# https://bugs.webkit.org/show_bug.cgi?id=169254
x86: AtomicStrongCAS8 U:G:32, UD:G:8, U:G:8, UD:G:8, ZD:G:8 /effects
StatusCond, Tmp*, Tmp, Addr, Tmp
StatusCond, Tmp*, Tmp, Index, Tmp
x86: AtomicStrongCAS16 U:G:32, UD:G:16, U:G:32, UD:G:16, ZD:G:8 /effects
StatusCond, Tmp*, Tmp, Addr, Tmp
StatusCond, Tmp*, Tmp, Index, Tmp
x86: AtomicStrongCAS32 U:G:32, UD:G:32, U:G:32, UD:G:32, ZD:G:8 /effects
StatusCond, Tmp*, Tmp, Addr, Tmp
StatusCond, Tmp*, Tmp, Index, Tmp
x86_64: AtomicStrongCAS64 U:G:32, UD:G:64, U:G:64, UD:G:64, ZD:G:8 /effects
StatusCond, Tmp*, Tmp, Addr, Tmp
StatusCond, Tmp*, Tmp, Index, Tmp
x86 arm64e: AtomicStrongCAS8 UD:G:8, U:G:8, UD:G:8 /effects
x86: Tmp*, Tmp, Addr
x86: Tmp*, Tmp, Index
arm64e: Tmp, Tmp, SimpleAddr
x86 arm64e: AtomicStrongCAS16 UD:G:16, U:G:32, UD:G:16 /effects
x86: Tmp*, Tmp, Addr
x86: Tmp*, Tmp, Index
arm64e: Tmp, Tmp, SimpleAddr
x86 arm64e: AtomicStrongCAS32 UD:G:32, U:G:32, UD:G:32 /effects
x86: Tmp*, Tmp, Addr
x86: Tmp*, Tmp, Index
arm64e: Tmp, Tmp, SimpleAddr
x86_64 arm64e: AtomicStrongCAS64 UD:G:64, U:G:64, UD:G:64 /effects
x86_64: Tmp*, Tmp, Addr
x86_64: Tmp*, Tmp, Index
arm64e: Tmp, Tmp, SimpleAddr
x86: BranchAtomicStrongCAS8 U:G:32, UD:G:8, U:G:8, UD:G:8 /branch /effects
StatusCond, Tmp*, Tmp, Addr
StatusCond, Tmp*, Tmp, Index
x86: BranchAtomicStrongCAS16 U:G:32, UD:G:16, U:G:32, UD:G:16 /branch /effects
StatusCond, Tmp*, Tmp, Addr
StatusCond, Tmp*, Tmp, Index
x86: BranchAtomicStrongCAS32 U:G:32, UD:G:32, U:G:32, UD:G:32 /branch /effects
StatusCond, Tmp*, Tmp, Addr
StatusCond, Tmp*, Tmp, Index
x86_64: BranchAtomicStrongCAS64 U:G:32, UD:G:64, U:G:64, UD:G:64 /branch /effects
StatusCond, Tmp*, Tmp, Addr
StatusCond, Tmp*, Tmp, Index
x86: AtomicAdd8 U:G:8, UD:G:8 /effects
Imm, Addr
Imm, Index
Tmp, Addr
Tmp, Index
x86: AtomicAdd16 U:G:16, UD:G:16 /effects
Imm, Addr
Imm, Index
Tmp, Addr
Tmp, Index
x86: AtomicAdd32 U:G:32, UD:G:32 /effects
Imm, Addr
Imm, Index
Tmp, Addr
Tmp, Index
x86_64: AtomicAdd64 U:G:64, UD:G:64 /effects
Imm, Addr
Imm, Index
Tmp, Addr
Tmp, Index
x86: AtomicSub8 U:G:8, UD:G:8 /effects
Imm, Addr
Imm, Index
Tmp, Addr
Tmp, Index
x86: AtomicSub16 U:G:16, UD:G:16 /effects
Imm, Addr
Imm, Index
Tmp, Addr
Tmp, Index
x86: AtomicSub32 U:G:32, UD:G:32 /effects
Imm, Addr
Imm, Index
Tmp, Addr
Tmp, Index
x86_64: AtomicSub64 U:G:64, UD:G:64 /effects
Imm, Addr
Imm, Index
Tmp, Addr
Tmp, Index
x86: AtomicAnd8 U:G:8, UD:G:8 /effects
Imm, Addr
Imm, Index
Tmp, Addr
Tmp, Index
x86: AtomicAnd16 U:G:16, UD:G:16 /effects
Imm, Addr
Imm, Index
Tmp, Addr
Tmp, Index
x86: AtomicAnd32 U:G:32, UD:G:32 /effects
Imm, Addr
Imm, Index
Tmp, Addr
Tmp, Index
x86_64: AtomicAnd64 U:G:64, UD:G:64 /effects
Imm, Addr
Imm, Index
Tmp, Addr