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RadeonInit2.cpp
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RadeonInit2.cpp
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#include "RadeonInfo.h"
#include "RadeonInit.h"
#include <SupportDefs.h>
#include <stdio.h>
#include <string.h>
#include <algorithm>
#include <bit>
#include "gfx_6_0_d.h"
//#include "gfx_7_2_enum.h"
#include "gfx_6_0.h"
#include "dce_6_0_d.h"
#include "bif_3_0_d.h"
#include "bif_3_0.h"
#include "oss_1_0_d.h"
#include "oss_1_0.h"
#include "gmc_6_0_d.h"
#include "gmc_6_0.h"
//#include "si_enums.h"
#include "sid_amdgpu.h"
union GbTileMode {
struct {
uint32 microTileMode: 2;
uint32 arrayMode: 4;
uint32 pipeConfig: 5;
uint32 tileSplit: 3;
uint32 bankWidth: 2;
uint32 bankHeight: 2;
uint32 macroTileAspect: 2;
uint32 numBanks: 2;
uint32 microTileModeNew: 3;
uint32 sampleSplit: 2;
uint32 altPipeConfig: 5;
};
uint32 val;
};
#define DRM_ERROR(format...) printf(format)
inline void WARN_ON(bool cond) {if (cond) abort();}
inline void BUG() {abort();}
static inline uint32 amdgpu_gfx_create_bitmask(uint32 bit_width)
{
return (uint32)((1ULL << bit_width) - 1);
}
static void amdgpu_gfx_parse_disable_cu(unsigned *mask, unsigned max_se, unsigned max_sh)
{
memset(mask, 0, sizeof(*mask) * max_se * max_sh);
}
static void gfx_v6_0_select_se_sh(struct amdgpu_device *adev, uint32 seNum, uint32 shNum, uint32 instance)
{
GrbmGfxIndex data{};
if (seNum == 0xffffffff)
data.seBroadcastWrites = 1;
else
data.seIndex = seNum;
if (shNum == 0xffffffff)
data.shBroadcastWrites = 1;
else
data.shIndex = shNum;
if (instance == 0xffffffff)
data.instanceBroadcastWrites = 1;
else
data.instanceIndex = instance;
WriteReg4AmdGpu(mmGRBM_GFX_INDEX, data.val);
}
static uint32 gfx_v6_0_get_rb_active_bitmap(struct amdgpu_device *adev)
{
uint32 data, mask;
data = ReadReg4AmdGpu(mmCC_RB_BACKEND_DISABLE) |
ReadReg4AmdGpu(mmGC_USER_RB_BACKEND_DISABLE);
data = GcUserRbBackendDisable{.val = data}.backendDisable /*REG_GET_FIELD(data, GC_USER_RB_BACKEND_DISABLE, BACKEND_DISABLE)*/;
mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se/
adev->gfx.config.max_sh_per_se);
return ~data & mask;
}
static void gfx_v6_0_raster_config(struct amdgpu_device *adev, uint32 *rconf)
{
switch (adev->asic_type) {
case CHIP_TAHITI:
case CHIP_PITCAIRN:
*rconf |= PaScRasterConfig{
.rbXsel2 = 2,
.rbXsel = 1,
.pkrMap = 2,
.pkrYsel = 1,
.seMap = 2,
.seXsel = 2,
.seYsel = 2
}.val;
break;
case CHIP_VERDE:
*rconf |= PaScRasterConfig{
.rbXsel = 1,
.pkrMap = 2,
.pkrYsel = 1
}.val;
break;
case CHIP_OLAND:
*rconf |= PaScRasterConfig{
.pkrYsel = 1
}.val;
break;
case CHIP_HAINAN:
*rconf |= 0x0;
break;
default:
DRM_ERROR("unknown asic: 0x%x\n", adev->asic_type);
break;
}
}
static void gfx_v6_0_write_harvested_raster_configs(struct amdgpu_device *adev,
uint32 raster_config, unsigned rb_mask,
unsigned num_rb)
{
unsigned sh_per_se = std::max<unsigned>(adev->gfx.config.max_sh_per_se, 1);
unsigned num_se = std::max<unsigned>(adev->gfx.config.max_shader_engines, 1);
unsigned rb_per_pkr = std::min<unsigned>(num_rb / num_se / sh_per_se, 2);
unsigned rb_per_se = num_rb / num_se;
unsigned se_mask[4];
unsigned se;
se_mask[0] = ((1 << rb_per_se) - 1) & rb_mask;
se_mask[1] = (se_mask[0] << rb_per_se) & rb_mask;
se_mask[2] = (se_mask[1] << rb_per_se) & rb_mask;
se_mask[3] = (se_mask[2] << rb_per_se) & rb_mask;
WARN_ON(!(num_se == 1 || num_se == 2 || num_se == 4));
WARN_ON(!(sh_per_se == 1 || sh_per_se == 2));
WARN_ON(!(rb_per_pkr == 1 || rb_per_pkr == 2));
for (se = 0; se < num_se; se++) {
PaScRasterConfig raster_config_se{.val = raster_config};
unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se);
unsigned pkr1_mask = pkr0_mask << rb_per_pkr;
int idx = (se / 2) * 2;
if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) {
if (!se_mask[idx])
raster_config_se.seMap = RASTER_CONFIG_SE_MAP_3;
else
raster_config_se.seMap = RASTER_CONFIG_SE_MAP_0;
}
pkr0_mask &= rb_mask;
pkr1_mask &= rb_mask;
if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) {
if (!pkr0_mask)
raster_config_se.pkrMap = RASTER_CONFIG_PKR_MAP_3;
else
raster_config_se.pkrMap = RASTER_CONFIG_PKR_MAP_0;
}
if (rb_per_se >= 2) {
unsigned rb0_mask = 1 << (se * rb_per_se);
unsigned rb1_mask = rb0_mask << 1;
rb0_mask &= rb_mask;
rb1_mask &= rb_mask;
if (!rb0_mask || !rb1_mask) {
if (!rb0_mask)
raster_config_se.rbMapPkr0 = RASTER_CONFIG_RB_MAP_3;
else
raster_config_se.rbMapPkr0 = RASTER_CONFIG_RB_MAP_0;
}
if (rb_per_se > 2) {
rb0_mask = 1 << (se * rb_per_se + rb_per_pkr);
rb1_mask = rb0_mask << 1;
rb0_mask &= rb_mask;
rb1_mask &= rb_mask;
if (!rb0_mask || !rb1_mask) {
if (!rb0_mask)
raster_config_se.rbMapPkr1 = RASTER_CONFIG_RB_MAP_3;
else
raster_config_se.rbMapPkr1 = RASTER_CONFIG_RB_MAP_0;
}
}
}
/* GRBM_GFX_INDEX has a different offset on SI */
gfx_v6_0_select_se_sh(adev, se, 0xffffffff, 0xffffffff);
WriteReg4AmdGpu(mmPA_SC_RASTER_CONFIG, raster_config_se.val);
}
/* GRBM_GFX_INDEX has a different offset on SI */
gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
}
static uint32 gfx_v6_0_get_cu_enabled(struct amdgpu_device *adev)
{
uint32 data, mask;
data = ReadReg4AmdGpu(mmCC_GC_SHADER_ARRAY_CONFIG) | ReadReg4AmdGpu(mmGC_USER_SHADER_ARRAY_CONFIG);
mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh);
return ~CcGcShaderArrayConfig{.val = data}.inactiveCus/*REG_GET_FIELD(data, CC_GC_SHADER_ARRAY_CONFIG, INACTIVE_CUS)*/ & mask;
}
static void gfx_v6_0_set_user_cu_inactive_bitmap(struct amdgpu_device *adev, uint32 bitmap)
{
if (!bitmap)
return;
WriteReg4AmdGpu(mmGC_USER_SHADER_ARRAY_CONFIG, GcUserShaderArrayConfig{.inactiveCus = bitmap}.val);
}
// #pragma mark -
static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev)
{
const uint32 num_tile_mode_states = B_COUNT_OF(adev->gfx.config.tile_mode_array);
uint32 reg_offset, split_equal_to_row_size, *tilemode;
memset(adev->gfx.config.tile_mode_array, 0, sizeof(adev->gfx.config.tile_mode_array));
tilemode = adev->gfx.config.tile_mode_array;
switch (adev->gfx.config.mem_row_size_in_kb) {
case 1:
split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_1KB;
break;
case 2:
default:
split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_2KB;
break;
case 4:
split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_4KB;
break;
}
switch (adev->asic_type) {
case CHIP_VERDE:
tilemode[0] = GbTileMode {
.microTileMode = ADDR_SURF_DEPTH_MICRO_TILING,
.arrayMode = ARRAY_2D_TILED_THIN1,
.pipeConfig = ADDR_SURF_P4_8x16,
.tileSplit = ADDR_SURF_TILE_SPLIT_64B,
.bankWidth = ADDR_SURF_BANK_WIDTH_1,
.bankHeight = ADDR_SURF_BANK_HEIGHT_4,
.macroTileAspect = ADDR_SURF_MACRO_ASPECT_4,
.numBanks = ADDR_SURF_16_BANK
}.val;
tilemode[1] = GbTileMode {
.microTileMode = ADDR_SURF_DEPTH_MICRO_TILING,
.arrayMode = ARRAY_2D_TILED_THIN1,
.pipeConfig = ADDR_SURF_P4_8x16,
.tileSplit = ADDR_SURF_TILE_SPLIT_128B,
.bankWidth = ADDR_SURF_BANK_WIDTH_1,
.bankHeight = ADDR_SURF_BANK_HEIGHT_4,
.macroTileAspect = ADDR_SURF_MACRO_ASPECT_4,
.numBanks = ADDR_SURF_16_BANK
}.val;
tilemode[2] = GbTileMode {
.microTileMode = ADDR_SURF_DEPTH_MICRO_TILING,
.arrayMode = ARRAY_2D_TILED_THIN1,
.pipeConfig = ADDR_SURF_P4_8x16,
.tileSplit = ADDR_SURF_TILE_SPLIT_256B,
.bankWidth = ADDR_SURF_BANK_WIDTH_1,
.bankHeight = ADDR_SURF_BANK_HEIGHT_4,
.macroTileAspect = ADDR_SURF_MACRO_ASPECT_4,
.numBanks = ADDR_SURF_16_BANK
}.val;
tilemode[3] = GbTileMode {
.microTileMode = ADDR_SURF_DEPTH_MICRO_TILING,
.arrayMode = ARRAY_2D_TILED_THIN1,
.pipeConfig = ADDR_SURF_P4_8x16,
.tileSplit = split_equal_to_row_size,
.bankWidth = ADDR_SURF_BANK_WIDTH_1,
.bankHeight = ADDR_SURF_BANK_HEIGHT_2,
.macroTileAspect = ADDR_SURF_MACRO_ASPECT_1,
.numBanks = ADDR_SURF_8_BANK
}.val;
tilemode[4] = GbTileMode {
.microTileMode = ADDR_SURF_DEPTH_MICRO_TILING,
.arrayMode = ARRAY_1D_TILED_THIN1,
.pipeConfig = ADDR_SURF_P4_8x16
}.val;
tilemode[5] = GbTileMode {
.microTileMode = ADDR_SURF_DEPTH_MICRO_TILING,
.arrayMode = ARRAY_2D_TILED_THIN1,
.pipeConfig = ADDR_SURF_P4_8x16,
.tileSplit = ADDR_SURF_TILE_SPLIT_512B,
.bankWidth = ADDR_SURF_BANK_WIDTH_1,
.bankHeight = ADDR_SURF_BANK_HEIGHT_2,
.macroTileAspect = ADDR_SURF_MACRO_ASPECT_1,
.numBanks = ADDR_SURF_4_BANK
}.val;
tilemode[6] = GbTileMode {
.microTileMode = ADDR_SURF_DEPTH_MICRO_TILING,
.arrayMode = ARRAY_2D_TILED_THIN1,
.pipeConfig = ADDR_SURF_P4_8x16,
.tileSplit = ADDR_SURF_TILE_SPLIT_256B,
.bankWidth = ADDR_SURF_BANK_WIDTH_1,
.bankHeight = ADDR_SURF_BANK_HEIGHT_4,
.macroTileAspect = ADDR_SURF_MACRO_ASPECT_1,
.numBanks = ADDR_SURF_4_BANK
}.val;
tilemode[7] = GbTileMode {
.microTileMode = ADDR_SURF_DEPTH_MICRO_TILING,
.arrayMode = ARRAY_2D_TILED_THIN1,
.pipeConfig = ADDR_SURF_P4_8x16,
.tileSplit = ADDR_SURF_TILE_SPLIT_1KB,
.bankWidth = ADDR_SURF_BANK_WIDTH_1,
.bankHeight = ADDR_SURF_BANK_HEIGHT_4,
.macroTileAspect = ADDR_SURF_MACRO_ASPECT_1,
.numBanks = ADDR_SURF_2_BANK
}.val;
tilemode[8] = GbTileMode {
.arrayMode = ARRAY_LINEAR_ALIGNED
}.val;
tilemode[9] = GbTileMode {
.microTileMode = ADDR_SURF_DISPLAY_MICRO_TILING,
.arrayMode = ARRAY_1D_TILED_THIN1,
.pipeConfig = ADDR_SURF_P4_8x16
}.val;
tilemode[10] = GbTileMode {
.microTileMode = ADDR_SURF_DISPLAY_MICRO_TILING,
.arrayMode = ARRAY_2D_TILED_THIN1,
.pipeConfig = ADDR_SURF_P4_8x16,
.tileSplit = ADDR_SURF_TILE_SPLIT_256B,
.bankWidth = ADDR_SURF_BANK_WIDTH_1,
.bankHeight = ADDR_SURF_BANK_HEIGHT_4,
.macroTileAspect = ADDR_SURF_MACRO_ASPECT_4,
.numBanks = ADDR_SURF_16_BANK
}.val;
tilemode[11] = GbTileMode {
.microTileMode = ADDR_SURF_DISPLAY_MICRO_TILING,
.arrayMode = ARRAY_2D_TILED_THIN1,
.pipeConfig = ADDR_SURF_P4_8x16,
.tileSplit = ADDR_SURF_TILE_SPLIT_256B,
.bankWidth = ADDR_SURF_BANK_WIDTH_1,
.bankHeight = ADDR_SURF_BANK_HEIGHT_2,
.macroTileAspect = ADDR_SURF_MACRO_ASPECT_2,
.numBanks = ADDR_SURF_16_BANK
}.val;
tilemode[12] = GbTileMode {
.microTileMode = ADDR_SURF_DISPLAY_MICRO_TILING,
.arrayMode = ARRAY_2D_TILED_THIN1,
.pipeConfig = ADDR_SURF_P4_8x16,
.tileSplit = ADDR_SURF_TILE_SPLIT_512B,
.bankWidth = ADDR_SURF_BANK_WIDTH_1,
.bankHeight = ADDR_SURF_BANK_HEIGHT_1,
.macroTileAspect = ADDR_SURF_MACRO_ASPECT_2,
.numBanks = ADDR_SURF_16_BANK
}.val;
tilemode[13] = GbTileMode {
.microTileMode = ADDR_SURF_THIN_MICRO_TILING,
.arrayMode = ARRAY_1D_TILED_THIN1,
.pipeConfig = ADDR_SURF_P4_8x16
}.val;
tilemode[14] = GbTileMode {
.microTileMode = ADDR_SURF_THIN_MICRO_TILING,
.arrayMode = ARRAY_2D_TILED_THIN1,
.pipeConfig = ADDR_SURF_P4_8x16,
.tileSplit = ADDR_SURF_TILE_SPLIT_256B,
.bankWidth = ADDR_SURF_BANK_WIDTH_1,
.bankHeight = ADDR_SURF_BANK_HEIGHT_4,
.macroTileAspect = ADDR_SURF_MACRO_ASPECT_2,
.numBanks = ADDR_SURF_16_BANK
}.val;
tilemode[15] = GbTileMode {
.microTileMode = ADDR_SURF_THIN_MICRO_TILING,
.arrayMode = ARRAY_2D_TILED_THIN1,
.pipeConfig = ADDR_SURF_P4_8x16,
.tileSplit = ADDR_SURF_TILE_SPLIT_256B,
.bankWidth = ADDR_SURF_BANK_WIDTH_1,
.bankHeight = ADDR_SURF_BANK_HEIGHT_2,
.macroTileAspect = ADDR_SURF_MACRO_ASPECT_2,
.numBanks = ADDR_SURF_16_BANK
}.val;
tilemode[16] = GbTileMode {
.microTileMode = ADDR_SURF_THIN_MICRO_TILING,
.arrayMode = ARRAY_2D_TILED_THIN1,
.pipeConfig = ADDR_SURF_P4_8x16,
.tileSplit = ADDR_SURF_TILE_SPLIT_512B,
.bankWidth = ADDR_SURF_BANK_WIDTH_1,
.bankHeight = ADDR_SURF_BANK_HEIGHT_1,
.macroTileAspect = ADDR_SURF_MACRO_ASPECT_2,
.numBanks = ADDR_SURF_16_BANK
}.val;
tilemode[17] = GbTileMode {
.microTileMode = ADDR_SURF_THIN_MICRO_TILING,
.arrayMode = ARRAY_2D_TILED_THIN1,
.pipeConfig = ADDR_SURF_P4_8x16,
.tileSplit = split_equal_to_row_size,
.bankWidth = ADDR_SURF_BANK_WIDTH_1,
.bankHeight = ADDR_SURF_BANK_HEIGHT_1,
.macroTileAspect = ADDR_SURF_MACRO_ASPECT_2,
.numBanks = ADDR_SURF_16_BANK
}.val;
tilemode[18] = GbTileMode {
.microTileMode = ADDR_SURF_THIN_MICRO_TILING,
.arrayMode = ARRAY_1D_TILED_THICK,
.pipeConfig = ADDR_SURF_P4_8x16
}.val;
tilemode[19] = GbTileMode {
.microTileMode = ADDR_SURF_THIN_MICRO_TILING,
.arrayMode = ARRAY_2D_TILED_XTHICK,
.pipeConfig = ADDR_SURF_P4_8x16,
.tileSplit = split_equal_to_row_size,
.bankWidth = ADDR_SURF_BANK_WIDTH_1,
.bankHeight = ADDR_SURF_BANK_HEIGHT_1,
.macroTileAspect = ADDR_SURF_MACRO_ASPECT_2,
.numBanks = ADDR_SURF_16_BANK
}.val;
tilemode[20] = GbTileMode {
.microTileMode = ADDR_SURF_THIN_MICRO_TILING,
.arrayMode = ARRAY_2D_TILED_THICK,
.pipeConfig = ADDR_SURF_P4_8x16,
.tileSplit = split_equal_to_row_size,
.bankWidth = ADDR_SURF_BANK_WIDTH_1,
.bankHeight = ADDR_SURF_BANK_HEIGHT_1,
.macroTileAspect = ADDR_SURF_MACRO_ASPECT_2,
.numBanks = ADDR_SURF_16_BANK
}.val;
tilemode[21] = GbTileMode {
.microTileMode = ADDR_SURF_THIN_MICRO_TILING,
.arrayMode = ARRAY_2D_TILED_THIN1,
.pipeConfig = ADDR_SURF_P4_8x16,
.tileSplit = ADDR_SURF_TILE_SPLIT_256B,
.bankWidth = ADDR_SURF_BANK_WIDTH_1,
.bankHeight = ADDR_SURF_BANK_HEIGHT_4,
.macroTileAspect = ADDR_SURF_MACRO_ASPECT_1,
.numBanks = ADDR_SURF_8_BANK
}.val;
tilemode[22] = GbTileMode {
.microTileMode = ADDR_SURF_THIN_MICRO_TILING,
.arrayMode = ARRAY_2D_TILED_THIN1,
.pipeConfig = ADDR_SURF_P4_8x16,
.tileSplit = ADDR_SURF_TILE_SPLIT_256B,
.bankWidth = ADDR_SURF_BANK_WIDTH_1,
.bankHeight = ADDR_SURF_BANK_HEIGHT_2,
.macroTileAspect = ADDR_SURF_MACRO_ASPECT_1,
.numBanks = ADDR_SURF_8_BANK
}.val;
tilemode[23] = GbTileMode {
.microTileMode = ADDR_SURF_THIN_MICRO_TILING,
.arrayMode = ARRAY_2D_TILED_THIN1,
.pipeConfig = ADDR_SURF_P4_8x16,
.tileSplit = ADDR_SURF_TILE_SPLIT_256B,
.bankWidth = ADDR_SURF_BANK_WIDTH_1,
.bankHeight = ADDR_SURF_BANK_HEIGHT_4,
.macroTileAspect = ADDR_SURF_MACRO_ASPECT_1,
.numBanks = ADDR_SURF_4_BANK
}.val;
tilemode[24] = GbTileMode {
.microTileMode = ADDR_SURF_THIN_MICRO_TILING,
.arrayMode = ARRAY_2D_TILED_THIN1,
.pipeConfig = ADDR_SURF_P4_8x16,
.tileSplit = ADDR_SURF_TILE_SPLIT_512B,
.bankWidth = ADDR_SURF_BANK_WIDTH_1,
.bankHeight = ADDR_SURF_BANK_HEIGHT_2,
.macroTileAspect = ADDR_SURF_MACRO_ASPECT_1,
.numBanks = ADDR_SURF_4_BANK
}.val;
tilemode[25] = GbTileMode {
.microTileMode = ADDR_SURF_THIN_MICRO_TILING,
.arrayMode = ARRAY_2D_TILED_THIN1,
.pipeConfig = ADDR_SURF_P4_8x16,
.tileSplit = ADDR_SURF_TILE_SPLIT_1KB,
.bankWidth = ADDR_SURF_BANK_WIDTH_1,
.bankHeight = ADDR_SURF_BANK_HEIGHT_4,
.macroTileAspect = ADDR_SURF_MACRO_ASPECT_1,
.numBanks = ADDR_SURF_2_BANK
}.val;
tilemode[26] = GbTileMode {
.microTileMode = ADDR_SURF_THIN_MICRO_TILING,
.arrayMode = ARRAY_2D_TILED_THIN1,
.pipeConfig = ADDR_SURF_P4_8x16,
.tileSplit = ADDR_SURF_TILE_SPLIT_1KB,
.bankWidth = ADDR_SURF_BANK_WIDTH_1,
.bankHeight = ADDR_SURF_BANK_HEIGHT_4,
.macroTileAspect = ADDR_SURF_MACRO_ASPECT_1,
.numBanks = ADDR_SURF_2_BANK
}.val;
tilemode[27] = GbTileMode {
.microTileMode = ADDR_SURF_THIN_MICRO_TILING,
.arrayMode = ARRAY_2D_TILED_THIN1,
.pipeConfig = ADDR_SURF_P4_8x16,
.tileSplit = ADDR_SURF_TILE_SPLIT_1KB,
.bankWidth = ADDR_SURF_BANK_WIDTH_1,
.bankHeight = ADDR_SURF_BANK_HEIGHT_4,
.macroTileAspect = ADDR_SURF_MACRO_ASPECT_1,
.numBanks = ADDR_SURF_2_BANK
}.val;
tilemode[28] = GbTileMode {
.microTileMode = ADDR_SURF_THIN_MICRO_TILING,
.arrayMode = ARRAY_2D_TILED_THIN1,
.pipeConfig = ADDR_SURF_P4_8x16,
.tileSplit = ADDR_SURF_TILE_SPLIT_1KB,
.bankWidth = ADDR_SURF_BANK_WIDTH_1,
.bankHeight = ADDR_SURF_BANK_HEIGHT_4,
.macroTileAspect = ADDR_SURF_MACRO_ASPECT_1,
.numBanks = ADDR_SURF_2_BANK
}.val;
tilemode[29] = GbTileMode {
.microTileMode = ADDR_SURF_THIN_MICRO_TILING,
.arrayMode = ARRAY_2D_TILED_THIN1,
.pipeConfig = ADDR_SURF_P4_8x16,
.tileSplit = ADDR_SURF_TILE_SPLIT_1KB,
.bankWidth = ADDR_SURF_BANK_WIDTH_1,
.bankHeight = ADDR_SURF_BANK_HEIGHT_4,
.macroTileAspect = ADDR_SURF_MACRO_ASPECT_1,
.numBanks = ADDR_SURF_2_BANK
}.val;
tilemode[30] = GbTileMode {
.microTileMode = ADDR_SURF_THIN_MICRO_TILING,
.arrayMode = ARRAY_2D_TILED_THIN1,
.pipeConfig = ADDR_SURF_P4_8x16,
.tileSplit = ADDR_SURF_TILE_SPLIT_2KB,
.bankWidth = ADDR_SURF_BANK_WIDTH_1,
.bankHeight = ADDR_SURF_BANK_HEIGHT_2,
.macroTileAspect = ADDR_SURF_MACRO_ASPECT_1,
.numBanks = ADDR_SURF_2_BANK
}.val;
break;
case CHIP_HAINAN:
tilemode[0] = GbTileMode {
.microTileMode = ADDR_SURF_DEPTH_MICRO_TILING,
.arrayMode = ARRAY_2D_TILED_THIN1,
.pipeConfig = ADDR_SURF_P2,
.tileSplit = ADDR_SURF_TILE_SPLIT_64B,
.bankWidth = ADDR_SURF_BANK_WIDTH_1,
.bankHeight = ADDR_SURF_BANK_HEIGHT_4,
.macroTileAspect = ADDR_SURF_MACRO_ASPECT_4,
.numBanks = ADDR_SURF_16_BANK
}.val;
tilemode[1] = GbTileMode {
.microTileMode = ADDR_SURF_DEPTH_MICRO_TILING,
.arrayMode = ARRAY_2D_TILED_THIN1,
.pipeConfig = ADDR_SURF_P2,
.tileSplit = ADDR_SURF_TILE_SPLIT_128B,
.bankWidth = ADDR_SURF_BANK_WIDTH_1,
.bankHeight = ADDR_SURF_BANK_HEIGHT_4,
.macroTileAspect = ADDR_SURF_MACRO_ASPECT_4,
.numBanks = ADDR_SURF_16_BANK
}.val;
tilemode[2] = GbTileMode {
.microTileMode = ADDR_SURF_DEPTH_MICRO_TILING,
.arrayMode = ARRAY_2D_TILED_THIN1,
.pipeConfig = ADDR_SURF_P2,
.tileSplit = ADDR_SURF_TILE_SPLIT_256B,
.bankWidth = ADDR_SURF_BANK_WIDTH_1,
.bankHeight = ADDR_SURF_BANK_HEIGHT_4,
.macroTileAspect = ADDR_SURF_MACRO_ASPECT_4,
.numBanks = ADDR_SURF_16_BANK
}.val;
tilemode[3] = GbTileMode {
.microTileMode = ADDR_SURF_DEPTH_MICRO_TILING,
.arrayMode = ARRAY_2D_TILED_THIN1,
.pipeConfig = ADDR_SURF_P2,
.tileSplit = split_equal_to_row_size,
.bankWidth = ADDR_SURF_BANK_WIDTH_1,
.bankHeight = ADDR_SURF_BANK_HEIGHT_2,
.macroTileAspect = ADDR_SURF_MACRO_ASPECT_1,
.numBanks = ADDR_SURF_8_BANK
}.val;
tilemode[4] = GbTileMode {
.microTileMode = ADDR_SURF_DEPTH_MICRO_TILING,
.arrayMode = ARRAY_1D_TILED_THIN1,
.pipeConfig = ADDR_SURF_P2
}.val;
tilemode[5] = GbTileMode {
.microTileMode = ADDR_SURF_DEPTH_MICRO_TILING,
.arrayMode = ARRAY_2D_TILED_THIN1,
.pipeConfig = ADDR_SURF_P2,
.tileSplit = ADDR_SURF_TILE_SPLIT_512B,
.bankWidth = ADDR_SURF_BANK_WIDTH_1,
.bankHeight = ADDR_SURF_BANK_HEIGHT_1,
.macroTileAspect = ADDR_SURF_MACRO_ASPECT_1,
.numBanks = ADDR_SURF_8_BANK
}.val;
tilemode[6] = GbTileMode {
.microTileMode = ADDR_SURF_DEPTH_MICRO_TILING,
.arrayMode = ARRAY_2D_TILED_THIN1,
.pipeConfig = ADDR_SURF_P2,
.tileSplit = ADDR_SURF_TILE_SPLIT_256B,
.bankWidth = ADDR_SURF_BANK_WIDTH_1,
.bankHeight = ADDR_SURF_BANK_HEIGHT_2,
.macroTileAspect = ADDR_SURF_MACRO_ASPECT_1,
.numBanks = ADDR_SURF_8_BANK
}.val;
tilemode[7] = GbTileMode {
.microTileMode = ADDR_SURF_DEPTH_MICRO_TILING,
.arrayMode = ARRAY_2D_TILED_THIN1,
.pipeConfig = ADDR_SURF_P2,
.tileSplit = ADDR_SURF_TILE_SPLIT_1KB,
.bankWidth = ADDR_SURF_BANK_WIDTH_1,
.bankHeight = ADDR_SURF_BANK_HEIGHT_2,
.macroTileAspect = ADDR_SURF_MACRO_ASPECT_1,
.numBanks = ADDR_SURF_4_BANK
}.val;
tilemode[8] = GbTileMode {
.arrayMode = ARRAY_LINEAR_ALIGNED
}.val;
tilemode[9] = GbTileMode {
.microTileMode = ADDR_SURF_DISPLAY_MICRO_TILING,
.arrayMode = ARRAY_1D_TILED_THIN1,
.pipeConfig = ADDR_SURF_P2
}.val;
tilemode[10] = GbTileMode {
.microTileMode = ADDR_SURF_DISPLAY_MICRO_TILING,
.arrayMode = ARRAY_2D_TILED_THIN1,
.pipeConfig = ADDR_SURF_P2,
.tileSplit = ADDR_SURF_TILE_SPLIT_256B,
.bankWidth = ADDR_SURF_BANK_WIDTH_1,
.bankHeight = ADDR_SURF_BANK_HEIGHT_4,
.macroTileAspect = ADDR_SURF_MACRO_ASPECT_4,
.numBanks = ADDR_SURF_16_BANK
}.val;
tilemode[11] = GbTileMode {
.microTileMode = ADDR_SURF_DISPLAY_MICRO_TILING,
.arrayMode = ARRAY_2D_TILED_THIN1,
.pipeConfig = ADDR_SURF_P2,
.tileSplit = ADDR_SURF_TILE_SPLIT_256B,
.bankWidth = ADDR_SURF_BANK_WIDTH_1,
.bankHeight = ADDR_SURF_BANK_HEIGHT_2,
.macroTileAspect = ADDR_SURF_MACRO_ASPECT_2,
.numBanks = ADDR_SURF_16_BANK
}.val;
tilemode[12] = GbTileMode {
.microTileMode = ADDR_SURF_DISPLAY_MICRO_TILING,
.arrayMode = ARRAY_2D_TILED_THIN1,
.pipeConfig = ADDR_SURF_P2,
.tileSplit = ADDR_SURF_TILE_SPLIT_512B,
.bankWidth = ADDR_SURF_BANK_WIDTH_1,
.bankHeight = ADDR_SURF_BANK_HEIGHT_1,
.macroTileAspect = ADDR_SURF_MACRO_ASPECT_2,
.numBanks = ADDR_SURF_16_BANK
}.val;
tilemode[13] = GbTileMode {
.microTileMode = ADDR_SURF_THIN_MICRO_TILING,
.arrayMode = ARRAY_1D_TILED_THIN1,
.pipeConfig = ADDR_SURF_P2
}.val;
tilemode[14] = GbTileMode {
.microTileMode = ADDR_SURF_THIN_MICRO_TILING,
.arrayMode = ARRAY_2D_TILED_THIN1,
.pipeConfig = ADDR_SURF_P2,
.tileSplit = ADDR_SURF_TILE_SPLIT_256B,
.bankWidth = ADDR_SURF_BANK_WIDTH_1,
.bankHeight = ADDR_SURF_BANK_HEIGHT_4,
.macroTileAspect = ADDR_SURF_MACRO_ASPECT_2,
.numBanks = ADDR_SURF_16_BANK
}.val;
tilemode[15] = GbTileMode {
.microTileMode = ADDR_SURF_THIN_MICRO_TILING,
.arrayMode = ARRAY_2D_TILED_THIN1,
.pipeConfig = ADDR_SURF_P2,
.tileSplit = ADDR_SURF_TILE_SPLIT_256B,
.bankWidth = ADDR_SURF_BANK_WIDTH_1,
.bankHeight = ADDR_SURF_BANK_HEIGHT_2,
.macroTileAspect = ADDR_SURF_MACRO_ASPECT_2,
.numBanks = ADDR_SURF_16_BANK
}.val;
tilemode[16] = GbTileMode {
.microTileMode = ADDR_SURF_THIN_MICRO_TILING,
.arrayMode = ARRAY_2D_TILED_THIN1,
.pipeConfig = ADDR_SURF_P2,
.tileSplit = ADDR_SURF_TILE_SPLIT_512B,
.bankWidth = ADDR_SURF_BANK_WIDTH_1,
.bankHeight = ADDR_SURF_BANK_HEIGHT_1,
.macroTileAspect = ADDR_SURF_MACRO_ASPECT_2,
.numBanks = ADDR_SURF_16_BANK
}.val;
tilemode[17] = GbTileMode {
.microTileMode = ADDR_SURF_THIN_MICRO_TILING,
.arrayMode = ARRAY_2D_TILED_THIN1,
.pipeConfig = ADDR_SURF_P2,
.tileSplit = split_equal_to_row_size,
.bankWidth = ADDR_SURF_BANK_WIDTH_1,
.bankHeight = ADDR_SURF_BANK_HEIGHT_1,
.macroTileAspect = ADDR_SURF_MACRO_ASPECT_2,
.numBanks = ADDR_SURF_16_BANK
}.val;
tilemode[18] = GbTileMode {
.microTileMode = ADDR_SURF_THIN_MICRO_TILING,
.arrayMode = ARRAY_1D_TILED_THICK,
.pipeConfig = ADDR_SURF_P2
}.val;
tilemode[19] = GbTileMode {
.microTileMode = ADDR_SURF_THIN_MICRO_TILING,
.arrayMode = ARRAY_2D_TILED_XTHICK,
.pipeConfig = ADDR_SURF_P2,
.tileSplit = split_equal_to_row_size,
.bankWidth = ADDR_SURF_BANK_WIDTH_1,
.bankHeight = ADDR_SURF_BANK_HEIGHT_1,
.macroTileAspect = ADDR_SURF_MACRO_ASPECT_2,
.numBanks = ADDR_SURF_16_BANK
}.val;
tilemode[20] = GbTileMode {
.microTileMode = ADDR_SURF_THIN_MICRO_TILING,
.arrayMode = ARRAY_2D_TILED_THICK,
.pipeConfig = ADDR_SURF_P2,
.tileSplit = split_equal_to_row_size,
.bankWidth = ADDR_SURF_BANK_WIDTH_1,
.bankHeight = ADDR_SURF_BANK_HEIGHT_1,
.macroTileAspect = ADDR_SURF_MACRO_ASPECT_2,
.numBanks = ADDR_SURF_16_BANK
}.val;
tilemode[21] = GbTileMode {
.microTileMode = ADDR_SURF_THIN_MICRO_TILING,
.arrayMode = ARRAY_2D_TILED_THIN1,
.pipeConfig = ADDR_SURF_P2,
.tileSplit = ADDR_SURF_TILE_SPLIT_256B,
.bankWidth = ADDR_SURF_BANK_WIDTH_2,
.bankHeight = ADDR_SURF_BANK_HEIGHT_4,
.macroTileAspect = ADDR_SURF_MACRO_ASPECT_1,
.numBanks = ADDR_SURF_8_BANK
}.val;
tilemode[22] = GbTileMode {
.microTileMode = ADDR_SURF_THIN_MICRO_TILING,
.arrayMode = ARRAY_2D_TILED_THIN1,
.pipeConfig = ADDR_SURF_P2,
.tileSplit = ADDR_SURF_TILE_SPLIT_256B,
.bankWidth = ADDR_SURF_BANK_WIDTH_2,
.bankHeight = ADDR_SURF_BANK_HEIGHT_2,
.macroTileAspect = ADDR_SURF_MACRO_ASPECT_1,
.numBanks = ADDR_SURF_8_BANK
}.val;
tilemode[23] = GbTileMode {
.microTileMode = ADDR_SURF_THIN_MICRO_TILING,
.arrayMode = ARRAY_2D_TILED_THIN1,
.pipeConfig = ADDR_SURF_P2,
.tileSplit = ADDR_SURF_TILE_SPLIT_256B,
.bankWidth = ADDR_SURF_BANK_WIDTH_1,
.bankHeight = ADDR_SURF_BANK_HEIGHT_2,
.macroTileAspect = ADDR_SURF_MACRO_ASPECT_1,
.numBanks = ADDR_SURF_8_BANK
}.val;
tilemode[24] = GbTileMode {
.microTileMode = ADDR_SURF_THIN_MICRO_TILING,
.arrayMode = ARRAY_2D_TILED_THIN1,
.pipeConfig = ADDR_SURF_P2,
.tileSplit = ADDR_SURF_TILE_SPLIT_512B,
.bankWidth = ADDR_SURF_BANK_WIDTH_1,
.bankHeight = ADDR_SURF_BANK_HEIGHT_1,
.macroTileAspect = ADDR_SURF_MACRO_ASPECT_1,
.numBanks = ADDR_SURF_8_BANK
}.val;
tilemode[25] = GbTileMode {
.microTileMode = ADDR_SURF_THIN_MICRO_TILING,
.arrayMode = ARRAY_2D_TILED_THIN1,
.pipeConfig = ADDR_SURF_P2,
.tileSplit = ADDR_SURF_TILE_SPLIT_1KB,
.bankWidth = ADDR_SURF_BANK_WIDTH_1,
.bankHeight = ADDR_SURF_BANK_HEIGHT_2,
.macroTileAspect = ADDR_SURF_MACRO_ASPECT_1,
.numBanks = ADDR_SURF_4_BANK
}.val;
tilemode[26] = GbTileMode {
.microTileMode = ADDR_SURF_THIN_MICRO_TILING,
.arrayMode = ARRAY_2D_TILED_THIN1,
.pipeConfig = ADDR_SURF_P2,
.tileSplit = ADDR_SURF_TILE_SPLIT_1KB,
.bankWidth = ADDR_SURF_BANK_WIDTH_1,
.bankHeight = ADDR_SURF_BANK_HEIGHT_2,
.macroTileAspect = ADDR_SURF_MACRO_ASPECT_1,
.numBanks = ADDR_SURF_4_BANK
}.val;
tilemode[27] = GbTileMode {
.microTileMode = ADDR_SURF_THIN_MICRO_TILING,
.arrayMode = ARRAY_2D_TILED_THIN1,
.pipeConfig = ADDR_SURF_P2,
.tileSplit = ADDR_SURF_TILE_SPLIT_1KB,
.bankWidth = ADDR_SURF_BANK_WIDTH_1,
.bankHeight = ADDR_SURF_BANK_HEIGHT_2,
.macroTileAspect = ADDR_SURF_MACRO_ASPECT_1,
.numBanks = ADDR_SURF_4_BANK
}.val;
tilemode[28] = GbTileMode {
.microTileMode = ADDR_SURF_THIN_MICRO_TILING,
.arrayMode = ARRAY_2D_TILED_THIN1,
.pipeConfig = ADDR_SURF_P2,
.tileSplit = ADDR_SURF_TILE_SPLIT_1KB,
.bankWidth = ADDR_SURF_BANK_WIDTH_1,
.bankHeight = ADDR_SURF_BANK_HEIGHT_2,
.macroTileAspect = ADDR_SURF_MACRO_ASPECT_1,
.numBanks = ADDR_SURF_4_BANK
}.val;
tilemode[29] = GbTileMode {
.microTileMode = ADDR_SURF_THIN_MICRO_TILING,
.arrayMode = ARRAY_2D_TILED_THIN1,
.pipeConfig = ADDR_SURF_P2,
.tileSplit = ADDR_SURF_TILE_SPLIT_1KB,
.bankWidth = ADDR_SURF_BANK_WIDTH_1,
.bankHeight = ADDR_SURF_BANK_HEIGHT_2,
.macroTileAspect = ADDR_SURF_MACRO_ASPECT_1,
.numBanks = ADDR_SURF_4_BANK
}.val;
tilemode[30] = GbTileMode {
.microTileMode = ADDR_SURF_THIN_MICRO_TILING,
.arrayMode = ARRAY_2D_TILED_THIN1,
.pipeConfig = ADDR_SURF_P2,
.tileSplit = ADDR_SURF_TILE_SPLIT_2KB,
.bankWidth = ADDR_SURF_BANK_WIDTH_1,
.bankHeight = ADDR_SURF_BANK_HEIGHT_1,
.macroTileAspect = ADDR_SURF_MACRO_ASPECT_1,
.numBanks = ADDR_SURF_4_BANK
}.val;
break;
case CHIP_TAHITI:
case CHIP_PITCAIRN:
tilemode[0] = GbTileMode {
.microTileMode = ADDR_SURF_DEPTH_MICRO_TILING,
.arrayMode = ARRAY_2D_TILED_THIN1,
.pipeConfig = ADDR_SURF_P8_32x32_8x16,
.tileSplit = ADDR_SURF_TILE_SPLIT_64B,
.bankWidth = ADDR_SURF_BANK_WIDTH_1,
.bankHeight = ADDR_SURF_BANK_HEIGHT_4,
.macroTileAspect = ADDR_SURF_MACRO_ASPECT_2,
.numBanks = ADDR_SURF_16_BANK
}.val;
tilemode[1] = GbTileMode {
.microTileMode = ADDR_SURF_DEPTH_MICRO_TILING,
.arrayMode = ARRAY_2D_TILED_THIN1,
.pipeConfig = ADDR_SURF_P8_32x32_8x16,
.tileSplit = ADDR_SURF_TILE_SPLIT_128B,
.bankWidth = ADDR_SURF_BANK_WIDTH_1,
.bankHeight = ADDR_SURF_BANK_HEIGHT_4,
.macroTileAspect = ADDR_SURF_MACRO_ASPECT_2,
.numBanks = ADDR_SURF_16_BANK
}.val;
tilemode[2] = GbTileMode {
.microTileMode = ADDR_SURF_DEPTH_MICRO_TILING,
.arrayMode = ARRAY_2D_TILED_THIN1,
.pipeConfig = ADDR_SURF_P8_32x32_8x16,
.tileSplit = ADDR_SURF_TILE_SPLIT_256B,
.bankWidth = ADDR_SURF_BANK_WIDTH_1,
.bankHeight = ADDR_SURF_BANK_HEIGHT_4,
.macroTileAspect = ADDR_SURF_MACRO_ASPECT_2,
.numBanks = ADDR_SURF_16_BANK
}.val;
tilemode[3] = GbTileMode {
.microTileMode = ADDR_SURF_DEPTH_MICRO_TILING,
.arrayMode = ARRAY_2D_TILED_THIN1,
.pipeConfig = ADDR_SURF_P8_32x32_8x16,
.tileSplit = split_equal_to_row_size,
.bankWidth = ADDR_SURF_BANK_WIDTH_1,
.bankHeight = ADDR_SURF_BANK_HEIGHT_4,
.macroTileAspect = ADDR_SURF_MACRO_ASPECT_1,
.numBanks = ADDR_SURF_4_BANK
}.val;
tilemode[4] = GbTileMode {
.microTileMode = ADDR_SURF_DEPTH_MICRO_TILING,
.arrayMode = ARRAY_1D_TILED_THIN1,
.pipeConfig = ADDR_SURF_P8_32x32_8x16
}.val;
tilemode[5] = GbTileMode {
.microTileMode = ADDR_SURF_DEPTH_MICRO_TILING,
.arrayMode = ARRAY_2D_TILED_THIN1,
.pipeConfig = ADDR_SURF_P8_32x32_8x16,
.tileSplit = ADDR_SURF_TILE_SPLIT_512B,
.bankWidth = ADDR_SURF_BANK_WIDTH_1,
.bankHeight = ADDR_SURF_BANK_HEIGHT_4,
.macroTileAspect = ADDR_SURF_MACRO_ASPECT_1,
.numBanks = ADDR_SURF_2_BANK
}.val;
tilemode[6] = GbTileMode {
.microTileMode = ADDR_SURF_DEPTH_MICRO_TILING,
.arrayMode = ARRAY_2D_TILED_THIN1,
.pipeConfig = ADDR_SURF_P8_32x32_8x16,
.tileSplit = ADDR_SURF_TILE_SPLIT_256B,
.bankWidth = ADDR_SURF_BANK_WIDTH_1,
.bankHeight = ADDR_SURF_BANK_HEIGHT_8,
.macroTileAspect = ADDR_SURF_MACRO_ASPECT_1,
.numBanks = ADDR_SURF_2_BANK
}.val;
tilemode[7] = GbTileMode {
.microTileMode = ADDR_SURF_DEPTH_MICRO_TILING,
.arrayMode = ARRAY_2D_TILED_THIN1,
.pipeConfig = ADDR_SURF_P4_8x16,
.tileSplit = ADDR_SURF_TILE_SPLIT_1KB,
.bankWidth = ADDR_SURF_BANK_WIDTH_1,
.bankHeight = ADDR_SURF_BANK_HEIGHT_4,
.macroTileAspect = ADDR_SURF_MACRO_ASPECT_1,
.numBanks = ADDR_SURF_2_BANK
}.val;
tilemode[8] = GbTileMode {
.arrayMode = ARRAY_LINEAR_ALIGNED
}.val;
tilemode[9] = GbTileMode {
.microTileMode = ADDR_SURF_DISPLAY_MICRO_TILING,
.arrayMode = ARRAY_1D_TILED_THIN1,
.pipeConfig = ADDR_SURF_P8_32x32_8x16
}.val;
tilemode[10] = GbTileMode {
.microTileMode = ADDR_SURF_DISPLAY_MICRO_TILING,
.arrayMode = ARRAY_2D_TILED_THIN1,
.pipeConfig = ADDR_SURF_P8_32x32_8x16,
.tileSplit = ADDR_SURF_TILE_SPLIT_256B,
.bankWidth = ADDR_SURF_BANK_WIDTH_1,
.bankHeight = ADDR_SURF_BANK_HEIGHT_4,
.macroTileAspect = ADDR_SURF_MACRO_ASPECT_2,
.numBanks = ADDR_SURF_16_BANK
}.val;
tilemode[11] = GbTileMode {
.microTileMode = ADDR_SURF_DISPLAY_MICRO_TILING,
.arrayMode = ARRAY_2D_TILED_THIN1,
.pipeConfig = ADDR_SURF_P8_32x32_8x16,
.tileSplit = ADDR_SURF_TILE_SPLIT_256B,
.bankWidth = ADDR_SURF_BANK_WIDTH_1,
.bankHeight = ADDR_SURF_BANK_HEIGHT_2,
.macroTileAspect = ADDR_SURF_MACRO_ASPECT_2,
.numBanks = ADDR_SURF_16_BANK
}.val;
tilemode[12] = GbTileMode {
.microTileMode = ADDR_SURF_DISPLAY_MICRO_TILING,
.arrayMode = ARRAY_2D_TILED_THIN1,
.pipeConfig = ADDR_SURF_P8_32x32_8x16,
.tileSplit = ADDR_SURF_TILE_SPLIT_512B,
.bankWidth = ADDR_SURF_BANK_WIDTH_1,
.bankHeight = ADDR_SURF_BANK_HEIGHT_1,
.macroTileAspect = ADDR_SURF_MACRO_ASPECT_1,
.numBanks = ADDR_SURF_16_BANK
}.val;
tilemode[13] = GbTileMode {
.microTileMode = ADDR_SURF_THIN_MICRO_TILING,
.arrayMode = ARRAY_1D_TILED_THIN1,
.pipeConfig = ADDR_SURF_P8_32x32_8x16
}.val;
tilemode[14] = GbTileMode {
.microTileMode = ADDR_SURF_THIN_MICRO_TILING,
.arrayMode = ARRAY_2D_TILED_THIN1,
.pipeConfig = ADDR_SURF_P8_32x32_8x16,
.tileSplit = ADDR_SURF_TILE_SPLIT_256B,
.bankWidth = ADDR_SURF_BANK_WIDTH_1,
.bankHeight = ADDR_SURF_BANK_HEIGHT_4,
.macroTileAspect = ADDR_SURF_MACRO_ASPECT_1,
.numBanks = ADDR_SURF_16_BANK
}.val;
tilemode[15] = GbTileMode {
.microTileMode = ADDR_SURF_THIN_MICRO_TILING,
.arrayMode = ARRAY_2D_TILED_THIN1,
.pipeConfig = ADDR_SURF_P8_32x32_8x16,
.tileSplit = ADDR_SURF_TILE_SPLIT_256B,
.bankWidth = ADDR_SURF_BANK_WIDTH_1,
.bankHeight = ADDR_SURF_BANK_HEIGHT_2,
.macroTileAspect = ADDR_SURF_MACRO_ASPECT_1,
.numBanks = ADDR_SURF_16_BANK
}.val;
tilemode[16] = GbTileMode {
.microTileMode = ADDR_SURF_THIN_MICRO_TILING,
.arrayMode = ARRAY_2D_TILED_THIN1,
.pipeConfig = ADDR_SURF_P8_32x32_8x16,
.tileSplit = ADDR_SURF_TILE_SPLIT_512B,
.bankWidth = ADDR_SURF_BANK_WIDTH_1,
.bankHeight = ADDR_SURF_BANK_HEIGHT_1,
.macroTileAspect = ADDR_SURF_MACRO_ASPECT_1,
.numBanks = ADDR_SURF_16_BANK
}.val;
tilemode[17] = GbTileMode {
.microTileMode = ADDR_SURF_THIN_MICRO_TILING,
.arrayMode = ARRAY_2D_TILED_THIN1,
.pipeConfig = ADDR_SURF_P8_32x32_8x16,
.tileSplit = split_equal_to_row_size,
.bankWidth = ADDR_SURF_BANK_WIDTH_1,
.bankHeight = ADDR_SURF_BANK_HEIGHT_1,
.macroTileAspect = ADDR_SURF_MACRO_ASPECT_1,
.numBanks = ADDR_SURF_16_BANK
}.val;
tilemode[18] = GbTileMode {
.microTileMode = ADDR_SURF_THIN_MICRO_TILING,
.arrayMode = ARRAY_1D_TILED_THICK,
.pipeConfig = ADDR_SURF_P8_32x32_8x16
}.val;
tilemode[19] = GbTileMode {
.microTileMode = ADDR_SURF_THIN_MICRO_TILING,
.arrayMode = ARRAY_2D_TILED_XTHICK,
.pipeConfig = ADDR_SURF_P8_32x32_8x16,
.tileSplit = split_equal_to_row_size,
.bankWidth = ADDR_SURF_BANK_WIDTH_1,
.bankHeight = ADDR_SURF_BANK_HEIGHT_1,
.macroTileAspect = ADDR_SURF_MACRO_ASPECT_1,
.numBanks = ADDR_SURF_16_BANK
}.val;
tilemode[20] = GbTileMode {
.microTileMode = ADDR_SURF_THIN_MICRO_TILING,
.arrayMode = ARRAY_2D_TILED_THICK,
.pipeConfig = ADDR_SURF_P8_32x32_8x16,
.tileSplit = split_equal_to_row_size,
.bankWidth = ADDR_SURF_BANK_WIDTH_1,