forked from openjdk/jdk
/
asmtest.out.h
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/
asmtest.out.h
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// BEGIN Generated code -- do not edit
// Generated by aarch64-asmtest.py
Label back, forth;
__ bind(back);
// ArithOp
__ add(r26, r23, r13, Assembler::LSL, 32); // add x26, x23, x13, LSL #32
__ sub(r12, r24, r9, Assembler::LSR, 37); // sub x12, x24, x9, LSR #37
__ adds(r28, r15, r8, Assembler::ASR, 39); // adds x28, x15, x8, ASR #39
__ subs(r7, r28, r30, Assembler::ASR, 57); // subs x7, x28, x30, ASR #57
__ addw(r9, r22, r27, Assembler::ASR, 15); // add w9, w22, w27, ASR #15
__ subw(r3, r13, r17, Assembler::ASR, 30); // sub w3, w13, w17, ASR #30
__ addsw(r14, r26, r8, Assembler::ASR, 17); // adds w14, w26, w8, ASR #17
__ subsw(r0, r22, r12, Assembler::ASR, 21); // subs w0, w22, w12, ASR #21
__ andr(r0, r15, r26, Assembler::LSL, 20); // and x0, x15, x26, LSL #20
__ orr(r26, r5, r17, Assembler::LSL, 61); // orr x26, x5, x17, LSL #61
__ eor(r24, r13, r2, Assembler::LSL, 32); // eor x24, x13, x2, LSL #32
__ ands(r28, r3, r17, Assembler::ASR, 35); // ands x28, x3, x17, ASR #35
__ andw(r25, r16, r29, Assembler::LSR, 18); // and w25, w16, w29, LSR #18
__ orrw(r13, r17, r11, Assembler::LSR, 9); // orr w13, w17, w11, LSR #9
__ eorw(r5, r5, r17, Assembler::LSR, 15); // eor w5, w5, w17, LSR #15
__ andsw(r2, r23, r27, Assembler::ASR, 26); // ands w2, w23, w27, ASR #26
__ bic(r27, r28, r16, Assembler::LSR, 45); // bic x27, x28, x16, LSR #45
__ orn(r8, r25, r26, Assembler::ASR, 37); // orn x8, x25, x26, ASR #37
__ eon(r29, r17, r13, Assembler::LSR, 63); // eon x29, x17, x13, LSR #63
__ bics(r28, r24, r2, Assembler::LSR, 31); // bics x28, x24, x2, LSR #31
__ bicw(r19, r26, r7, Assembler::ASR, 3); // bic w19, w26, w7, ASR #3
__ ornw(r6, r24, r10, Assembler::ASR, 3); // orn w6, w24, w10, ASR #3
__ eonw(r4, r21, r1, Assembler::LSR, 29); // eon w4, w21, w1, LSR #29
__ bicsw(r16, r21, r0, Assembler::LSR, 19); // bics w16, w21, w0, LSR #19
// AddSubImmOp
__ addw(r17, r12, 379u); // add w17, w12, #379
__ addsw(r30, r1, 22u); // adds w30, w1, #22
__ subw(r29, r5, 126u); // sub w29, w5, #126
__ subsw(r6, r24, 960u); // subs w6, w24, #960
__ add(r0, r13, 104u); // add x0, x13, #104
__ adds(r8, r6, 663u); // adds x8, x6, #663
__ sub(r10, r5, 516u); // sub x10, x5, #516
__ subs(r1, r3, 1012u); // subs x1, x3, #1012
// LogicalImmOp
__ andw(r6, r11, 4294049777ull); // and w6, w11, #0xfff1fff1
__ orrw(r28, r5, 4294966791ull); // orr w28, w5, #0xfffffe07
__ eorw(r1, r20, 134217216ull); // eor w1, w20, #0x7fffe00
__ andsw(r7, r17, 1048576ull); // ands w7, w17, #0x100000
__ andr(r14, r12, 9223372036854775808ull); // and x14, x12, #0x8000000000000000
__ orr(r9, r11, 562675075514368ull); // orr x9, x11, #0x1ffc000000000
__ eor(r17, r0, 18014398509481728ull); // eor x17, x0, #0x3fffffffffff00
__ ands(r1, r8, 18446744073705357315ull); // ands x1, x8, #0xffffffffffc00003
// AbsOp
__ b(__ pc()); // b .
__ b(back); // b back
__ b(forth); // b forth
__ bl(__ pc()); // bl .
__ bl(back); // bl back
__ bl(forth); // bl forth
// RegAndAbsOp
__ cbzw(r10, __ pc()); // cbz w10, .
__ cbzw(r10, back); // cbz w10, back
__ cbzw(r10, forth); // cbz w10, forth
__ cbnzw(r8, __ pc()); // cbnz w8, .
__ cbnzw(r8, back); // cbnz w8, back
__ cbnzw(r8, forth); // cbnz w8, forth
__ cbz(r11, __ pc()); // cbz x11, .
__ cbz(r11, back); // cbz x11, back
__ cbz(r11, forth); // cbz x11, forth
__ cbnz(r29, __ pc()); // cbnz x29, .
__ cbnz(r29, back); // cbnz x29, back
__ cbnz(r29, forth); // cbnz x29, forth
__ adr(r19, __ pc()); // adr x19, .
__ adr(r19, back); // adr x19, back
__ adr(r19, forth); // adr x19, forth
__ _adrp(r19, __ pc()); // adrp x19, .
// RegImmAbsOp
__ tbz(r22, 6, __ pc()); // tbz x22, #6, .
__ tbz(r22, 6, back); // tbz x22, #6, back
__ tbz(r22, 6, forth); // tbz x22, #6, forth
__ tbnz(r12, 11, __ pc()); // tbnz x12, #11, .
__ tbnz(r12, 11, back); // tbnz x12, #11, back
__ tbnz(r12, 11, forth); // tbnz x12, #11, forth
// MoveWideImmOp
__ movnw(r0, 6301, 0); // movn w0, #6301, lsl 0
__ movzw(r7, 20886, 0); // movz w7, #20886, lsl 0
__ movkw(r27, 18617, 0); // movk w27, #18617, lsl 0
__ movn(r12, 22998, 16); // movn x12, #22998, lsl 16
__ movz(r20, 1532, 16); // movz x20, #1532, lsl 16
__ movk(r8, 5167, 32); // movk x8, #5167, lsl 32
// BitfieldOp
__ sbfm(r15, r17, 24, 28); // sbfm x15, x17, #24, #28
__ bfmw(r15, r9, 14, 25); // bfm w15, w9, #14, #25
__ ubfmw(r27, r25, 6, 31); // ubfm w27, w25, #6, #31
__ sbfm(r19, r2, 23, 31); // sbfm x19, x2, #23, #31
__ bfm(r12, r21, 10, 6); // bfm x12, x21, #10, #6
__ ubfm(r22, r0, 26, 16); // ubfm x22, x0, #26, #16
// ExtractOp
__ extrw(r3, r3, r20, 27); // extr w3, w3, w20, #27
__ extr(r8, r30, r3, 54); // extr x8, x30, x3, #54
// CondBranchOp
__ br(Assembler::EQ, __ pc()); // b.EQ .
__ br(Assembler::EQ, back); // b.EQ back
__ br(Assembler::EQ, forth); // b.EQ forth
__ br(Assembler::NE, __ pc()); // b.NE .
__ br(Assembler::NE, back); // b.NE back
__ br(Assembler::NE, forth); // b.NE forth
__ br(Assembler::HS, __ pc()); // b.HS .
__ br(Assembler::HS, back); // b.HS back
__ br(Assembler::HS, forth); // b.HS forth
__ br(Assembler::CS, __ pc()); // b.CS .
__ br(Assembler::CS, back); // b.CS back
__ br(Assembler::CS, forth); // b.CS forth
__ br(Assembler::LO, __ pc()); // b.LO .
__ br(Assembler::LO, back); // b.LO back
__ br(Assembler::LO, forth); // b.LO forth
__ br(Assembler::CC, __ pc()); // b.CC .
__ br(Assembler::CC, back); // b.CC back
__ br(Assembler::CC, forth); // b.CC forth
__ br(Assembler::MI, __ pc()); // b.MI .
__ br(Assembler::MI, back); // b.MI back
__ br(Assembler::MI, forth); // b.MI forth
__ br(Assembler::PL, __ pc()); // b.PL .
__ br(Assembler::PL, back); // b.PL back
__ br(Assembler::PL, forth); // b.PL forth
__ br(Assembler::VS, __ pc()); // b.VS .
__ br(Assembler::VS, back); // b.VS back
__ br(Assembler::VS, forth); // b.VS forth
__ br(Assembler::VC, __ pc()); // b.VC .
__ br(Assembler::VC, back); // b.VC back
__ br(Assembler::VC, forth); // b.VC forth
__ br(Assembler::HI, __ pc()); // b.HI .
__ br(Assembler::HI, back); // b.HI back
__ br(Assembler::HI, forth); // b.HI forth
__ br(Assembler::LS, __ pc()); // b.LS .
__ br(Assembler::LS, back); // b.LS back
__ br(Assembler::LS, forth); // b.LS forth
__ br(Assembler::GE, __ pc()); // b.GE .
__ br(Assembler::GE, back); // b.GE back
__ br(Assembler::GE, forth); // b.GE forth
__ br(Assembler::LT, __ pc()); // b.LT .
__ br(Assembler::LT, back); // b.LT back
__ br(Assembler::LT, forth); // b.LT forth
__ br(Assembler::GT, __ pc()); // b.GT .
__ br(Assembler::GT, back); // b.GT back
__ br(Assembler::GT, forth); // b.GT forth
__ br(Assembler::LE, __ pc()); // b.LE .
__ br(Assembler::LE, back); // b.LE back
__ br(Assembler::LE, forth); // b.LE forth
__ br(Assembler::AL, __ pc()); // b.AL .
__ br(Assembler::AL, back); // b.AL back
__ br(Assembler::AL, forth); // b.AL forth
__ br(Assembler::NV, __ pc()); // b.NV .
__ br(Assembler::NV, back); // b.NV back
__ br(Assembler::NV, forth); // b.NV forth
// ImmOp
__ svc(12999); // svc #12999
__ hvc(2665); // hvc #2665
__ smc(9002); // smc #9002
__ brk(14843); // brk #14843
__ hlt(25964); // hlt #25964
// Op
__ nop(); // nop
__ eret(); // eret
__ drps(); // drps
__ isb(); // isb
// SystemOp
__ dsb(Assembler::ST); // dsb ST
__ dmb(Assembler::OSHST); // dmb OSHST
// OneRegOp
__ br(r16); // br x16
__ blr(r20); // blr x20
// LoadStoreExclusiveOp
__ stxr(r10, r27, r8); // stxr w10, x27, [x8]
__ stlxr(r0, r1, r21); // stlxr w0, x1, [x21]
__ ldxr(r17, r29); // ldxr x17, [x29]
__ ldaxr(r29, r28); // ldaxr x29, [x28]
__ stlr(r1, r23); // stlr x1, [x23]
__ ldar(r21, r20); // ldar x21, [x20]
// LoadStoreExclusiveOp
__ stxrw(r22, r27, r19); // stxr w22, w27, [x19]
__ stlxrw(r11, r16, r6); // stlxr w11, w16, [x6]
__ ldxrw(r17, r0); // ldxr w17, [x0]
__ ldaxrw(r4, r10); // ldaxr w4, [x10]
__ stlrw(r24, r22); // stlr w24, [x22]
__ ldarw(r10, r19); // ldar w10, [x19]
// LoadStoreExclusiveOp
__ stxrh(r1, r5, r30); // stxrh w1, w5, [x30]
__ stlxrh(r8, r12, r17); // stlxrh w8, w12, [x17]
__ ldxrh(r9, r14); // ldxrh w9, [x14]
__ ldaxrh(r7, r1); // ldaxrh w7, [x1]
__ stlrh(r5, r16); // stlrh w5, [x16]
__ ldarh(r2, r12); // ldarh w2, [x12]
// LoadStoreExclusiveOp
__ stxrb(r10, r12, r3); // stxrb w10, w12, [x3]
__ stlxrb(r28, r14, r26); // stlxrb w28, w14, [x26]
__ ldxrb(r30, r10); // ldxrb w30, [x10]
__ ldaxrb(r14, r21); // ldaxrb w14, [x21]
__ stlrb(r13, r9); // stlrb w13, [x9]
__ ldarb(r22, r27); // ldarb w22, [x27]
// LoadStoreExclusiveOp
__ ldxp(r28, r19, r11); // ldxp x28, x19, [x11]
__ ldaxp(r30, r19, r2); // ldaxp x30, x19, [x2]
__ stxp(r2, r23, r1, r0); // stxp w2, x23, x1, [x0]
__ stlxp(r12, r16, r13, r15); // stlxp w12, x16, x13, [x15]
// LoadStoreExclusiveOp
__ ldxpw(r17, r21, r13); // ldxp w17, w21, [x13]
__ ldaxpw(r11, r30, r8); // ldaxp w11, w30, [x8]
__ stxpw(r24, r13, r11, r1); // stxp w24, w13, w11, [x1]
__ stlxpw(r26, r21, r27, r13); // stlxp w26, w21, w27, [x13]
// base_plus_unscaled_offset
// LoadStoreOp
__ str(r11, Address(r20, -103)); // str x11, [x20, -103]
__ strw(r28, Address(r16, 62)); // str w28, [x16, 62]
__ strb(r27, Address(r9, -9)); // strb w27, [x9, -9]
__ strh(r2, Address(r25, -50)); // strh w2, [x25, -50]
__ ldr(r4, Address(r2, -241)); // ldr x4, [x2, -241]
__ ldrw(r30, Address(r20, -31)); // ldr w30, [x20, -31]
__ ldrb(r17, Address(r23, -23)); // ldrb w17, [x23, -23]
__ ldrh(r29, Address(r26, -1)); // ldrh w29, [x26, -1]
__ ldrsb(r1, Address(r9, 6)); // ldrsb x1, [x9, 6]
__ ldrsh(r11, Address(r12, 19)); // ldrsh x11, [x12, 19]
__ ldrshw(r11, Address(r1, -50)); // ldrsh w11, [x1, -50]
__ ldrsw(r19, Address(r24, 41)); // ldrsw x19, [x24, 41]
__ ldrd(v24, Address(r24, 95)); // ldr d24, [x24, 95]
__ ldrs(v15, Address(r5, -43)); // ldr s15, [x5, -43]
__ strd(v21, Address(r27, 1)); // str d21, [x27, 1]
__ strs(v23, Address(r13, -107)); // str s23, [x13, -107]
// pre
// LoadStoreOp
__ str(r10, Address(__ pre(r0, 8))); // str x10, [x0, 8]!
__ strw(r3, Address(__ pre(r0, 29))); // str w3, [x0, 29]!
__ strb(r10, Address(__ pre(r14, 9))); // strb w10, [x14, 9]!
__ strh(r29, Address(__ pre(r25, -3))); // strh w29, [x25, -3]!
__ ldr(r12, Address(__ pre(r16, -144))); // ldr x12, [x16, -144]!
__ ldrw(r12, Address(__ pre(r22, -6))); // ldr w12, [x22, -6]!
__ ldrb(r13, Address(__ pre(r11, -10))); // ldrb w13, [x11, -10]!
__ ldrh(r0, Address(__ pre(r21, -21))); // ldrh w0, [x21, -21]!
__ ldrsb(r23, Address(__ pre(r6, 4))); // ldrsb x23, [x6, 4]!
__ ldrsh(r3, Address(__ pre(r7, -53))); // ldrsh x3, [x7, -53]!
__ ldrshw(r28, Address(__ pre(r4, -7))); // ldrsh w28, [x4, -7]!
__ ldrsw(r24, Address(__ pre(r8, -18))); // ldrsw x24, [x8, -18]!
__ ldrd(v14, Address(__ pre(r11, 12))); // ldr d14, [x11, 12]!
__ ldrs(v19, Address(__ pre(r12, -67))); // ldr s19, [x12, -67]!
__ strd(v20, Address(__ pre(r0, -253))); // str d20, [x0, -253]!
__ strs(v8, Address(__ pre(r0, 64))); // str s8, [x0, 64]!
// post
// LoadStoreOp
__ str(r3, Address(__ post(r28, -94))); // str x3, [x28], -94
__ strw(r11, Address(__ post(r7, -54))); // str w11, [x7], -54
__ strb(r27, Address(__ post(r10, -24))); // strb w27, [x10], -24
__ strh(r6, Address(__ post(r7, 27))); // strh w6, [x7], 27
__ ldr(r13, Address(__ post(r10, -202))); // ldr x13, [x10], -202
__ ldrw(r15, Address(__ post(r5, -41))); // ldr w15, [x5], -41
__ ldrb(r2, Address(__ post(r13, 9))); // ldrb w2, [x13], 9
__ ldrh(r28, Address(__ post(r13, -20))); // ldrh w28, [x13], -20
__ ldrsb(r9, Address(__ post(r13, -31))); // ldrsb x9, [x13], -31
__ ldrsh(r3, Address(__ post(r24, -36))); // ldrsh x3, [x24], -36
__ ldrshw(r20, Address(__ post(r3, 6))); // ldrsh w20, [x3], 6
__ ldrsw(r7, Address(__ post(r19, -1))); // ldrsw x7, [x19], -1
__ ldrd(v30, Address(__ post(r8, -130))); // ldr d30, [x8], -130
__ ldrs(v25, Address(__ post(r15, 21))); // ldr s25, [x15], 21
__ strd(v14, Address(__ post(r23, 90))); // str d14, [x23], 90
__ strs(v8, Address(__ post(r0, -33))); // str s8, [x0], -33
// base_plus_reg
// LoadStoreOp
__ str(r10, Address(r17, r21, Address::sxtw(3))); // str x10, [x17, w21, sxtw #3]
__ strw(r4, Address(r13, r22, Address::sxtw(2))); // str w4, [x13, w22, sxtw #2]
__ strb(r13, Address(r0, r19, Address::uxtw(0))); // strb w13, [x0, w19, uxtw #0]
__ strh(r12, Address(r27, r6, Address::sxtw(0))); // strh w12, [x27, w6, sxtw #0]
__ ldr(r0, Address(r8, r16, Address::lsl(0))); // ldr x0, [x8, x16, lsl #0]
__ ldrw(r0, Address(r4, r26, Address::sxtx(0))); // ldr w0, [x4, x26, sxtx #0]
__ ldrb(r14, Address(r25, r5, Address::sxtw(0))); // ldrb w14, [x25, w5, sxtw #0]
__ ldrh(r9, Address(r4, r17, Address::uxtw(0))); // ldrh w9, [x4, w17, uxtw #0]
__ ldrsb(r27, Address(r4, r7, Address::lsl(0))); // ldrsb x27, [x4, x7, lsl #0]
__ ldrsh(r15, Address(r17, r30, Address::sxtw(0))); // ldrsh x15, [x17, w30, sxtw #0]
__ ldrshw(r16, Address(r0, r22, Address::sxtw(0))); // ldrsh w16, [x0, w22, sxtw #0]
__ ldrsw(r22, Address(r10, r30, Address::sxtx(2))); // ldrsw x22, [x10, x30, sxtx #2]
__ ldrd(v29, Address(r21, r10, Address::sxtx(3))); // ldr d29, [x21, x10, sxtx #3]
__ ldrs(v3, Address(r11, r19, Address::uxtw(0))); // ldr s3, [x11, w19, uxtw #0]
__ strd(v13, Address(r28, r29, Address::uxtw(3))); // str d13, [x28, w29, uxtw #3]
__ strs(v23, Address(r29, r5, Address::sxtx(2))); // str s23, [x29, x5, sxtx #2]
// base_plus_scaled_offset
// LoadStoreOp
__ str(r5, Address(r8, 12600)); // str x5, [x8, 12600]
__ strw(r29, Address(r24, 7880)); // str w29, [x24, 7880]
__ strb(r19, Address(r17, 1566)); // strb w19, [x17, 1566]
__ strh(r13, Address(r19, 3984)); // strh w13, [x19, 3984]
__ ldr(r19, Address(r23, 13632)); // ldr x19, [x23, 13632]
__ ldrw(r23, Address(r29, 6264)); // ldr w23, [x29, 6264]
__ ldrb(r22, Address(r11, 2012)); // ldrb w22, [x11, 2012]
__ ldrh(r3, Address(r10, 3784)); // ldrh w3, [x10, 3784]
__ ldrsb(r8, Address(r16, 1951)); // ldrsb x8, [x16, 1951]
__ ldrsh(r23, Address(r20, 3346)); // ldrsh x23, [x20, 3346]
__ ldrshw(r2, Address(r1, 3994)); // ldrsh w2, [x1, 3994]
__ ldrsw(r4, Address(r17, 7204)); // ldrsw x4, [x17, 7204]
__ ldrd(v20, Address(r27, 14400)); // ldr d20, [x27, 14400]
__ ldrs(v25, Address(r14, 8096)); // ldr s25, [x14, 8096]
__ strd(v26, Address(r10, 15024)); // str d26, [x10, 15024]
__ strs(v9, Address(r3, 6936)); // str s9, [x3, 6936]
// pcrel
// LoadStoreOp
__ ldr(r27, forth); // ldr x27, forth
__ ldrw(r11, __ pc()); // ldr w11, .
// LoadStoreOp
__ prfm(Address(r3, -187)); // prfm PLDL1KEEP, [x3, -187]
// LoadStoreOp
__ prfm(__ pc()); // prfm PLDL1KEEP, .
// LoadStoreOp
__ prfm(Address(r29, r14, Address::lsl(0))); // prfm PLDL1KEEP, [x29, x14, lsl #0]
// LoadStoreOp
__ prfm(Address(r4, 13312)); // prfm PLDL1KEEP, [x4, 13312]
// AddSubCarryOp
__ adcw(r21, r1, r7); // adc w21, w1, w7
__ adcsw(r8, r5, r7); // adcs w8, w5, w7
__ sbcw(r7, r27, r14); // sbc w7, w27, w14
__ sbcsw(r27, r4, r17); // sbcs w27, w4, w17
__ adc(r0, r28, r0); // adc x0, x28, x0
__ adcs(r12, r24, r30); // adcs x12, x24, x30
__ sbc(r0, r25, r15); // sbc x0, x25, x15
__ sbcs(r1, r24, r3); // sbcs x1, x24, x3
// AddSubExtendedOp
__ addw(r17, r24, r20, ext::uxtb, 2); // add w17, w24, w20, uxtb #2
__ addsw(r13, r28, r10, ext::uxth, 1); // adds w13, w28, w10, uxth #1
__ sub(r15, r16, r2, ext::sxth, 2); // sub x15, x16, x2, sxth #2
__ subsw(r29, r13, r13, ext::uxth, 2); // subs w29, w13, w13, uxth #2
__ add(r12, r20, r12, ext::sxtw, 3); // add x12, x20, x12, sxtw #3
__ adds(r30, r27, r11, ext::sxtb, 1); // adds x30, x27, x11, sxtb #1
__ sub(r14, r7, r1, ext::sxtw, 2); // sub x14, x7, x1, sxtw #2
__ subs(r29, r3, r27, ext::sxth, 1); // subs x29, x3, x27, sxth #1
// ConditionalCompareOp
__ ccmnw(r0, r13, 14u, Assembler::MI); // ccmn w0, w13, #14, MI
__ ccmpw(r22, r17, 6u, Assembler::CC); // ccmp w22, w17, #6, CC
__ ccmn(r17, r30, 14u, Assembler::VS); // ccmn x17, x30, #14, VS
__ ccmp(r10, r19, 12u, Assembler::HI); // ccmp x10, x19, #12, HI
// ConditionalCompareImmedOp
__ ccmnw(r6, 18, 2, Assembler::LE); // ccmn w6, #18, #2, LE
__ ccmpw(r9, 13, 4, Assembler::HI); // ccmp w9, #13, #4, HI
__ ccmn(r21, 11, 11, Assembler::LO); // ccmn x21, #11, #11, LO
__ ccmp(r4, 13, 2, Assembler::VC); // ccmp x4, #13, #2, VC
// ConditionalSelectOp
__ cselw(r12, r2, r22, Assembler::HI); // csel w12, w2, w22, HI
__ csincw(r24, r16, r17, Assembler::HS); // csinc w24, w16, w17, HS
__ csinvw(r6, r7, r16, Assembler::LT); // csinv w6, w7, w16, LT
__ csnegw(r11, r27, r22, Assembler::LS); // csneg w11, w27, w22, LS
__ csel(r10, r3, r29, Assembler::LT); // csel x10, x3, x29, LT
__ csinc(r12, r26, r27, Assembler::CC); // csinc x12, x26, x27, CC
__ csinv(r15, r10, r21, Assembler::GT); // csinv x15, x10, x21, GT
__ csneg(r30, r23, r9, Assembler::GT); // csneg x30, x23, x9, GT
// TwoRegOp
__ rbitw(r30, r10); // rbit w30, w10
__ rev16w(r29, r15); // rev16 w29, w15
__ revw(r29, r30); // rev w29, w30
__ clzw(r25, r21); // clz w25, w21
__ clsw(r4, r0); // cls w4, w0
__ rbit(r17, r21); // rbit x17, x21
__ rev16(r29, r16); // rev16 x29, x16
__ rev32(r21, r20); // rev32 x21, x20
__ rev(r6, r19); // rev x6, x19
__ clz(r30, r3); // clz x30, x3
__ cls(r21, r19); // cls x21, x19
// ThreeRegOp
__ udivw(r11, r24, r0); // udiv w11, w24, w0
__ sdivw(r27, r25, r14); // sdiv w27, w25, w14
__ lslvw(r3, r14, r17); // lslv w3, w14, w17
__ lsrvw(r7, r15, r24); // lsrv w7, w15, w24
__ asrvw(r28, r17, r25); // asrv w28, w17, w25
__ rorvw(r2, r26, r28); // rorv w2, w26, w28
__ udiv(r5, r25, r26); // udiv x5, x25, x26
__ sdiv(r27, r16, r17); // sdiv x27, x16, x17
__ lslv(r6, r21, r12); // lslv x6, x21, x12
__ lsrv(r0, r4, r12); // lsrv x0, x4, x12
__ asrv(r27, r17, r28); // asrv x27, x17, x28
__ rorv(r28, r2, r17); // rorv x28, x2, x17
__ umulh(r10, r15, r14); // umulh x10, x15, x14
__ smulh(r14, r3, r25); // smulh x14, x3, x25
// FourRegMulOp
__ maddw(r15, r19, r14, r5); // madd w15, w19, w14, w5
__ msubw(r16, r4, r26, r25); // msub w16, w4, w26, w25
__ madd(r4, r2, r2, r12); // madd x4, x2, x2, x12
__ msub(r29, r17, r8, r7); // msub x29, x17, x8, x7
__ smaddl(r3, r4, r25, r4); // smaddl x3, w4, w25, x4
__ smsubl(r26, r25, r4, r17); // smsubl x26, w25, w4, x17
__ umaddl(r0, r26, r17, r23); // umaddl x0, w26, w17, x23
__ umsubl(r15, r21, r28, r17); // umsubl x15, w21, w28, x17
// ThreeRegFloatOp
__ fabds(v27, v10, v3); // fabd s27, s10, s3
__ fmuls(v0, v7, v25); // fmul s0, s7, s25
__ fdivs(v9, v6, v15); // fdiv s9, s6, s15
__ fadds(v29, v15, v10); // fadd s29, s15, s10
__ fsubs(v2, v17, v7); // fsub s2, s17, s7
__ fabdd(v11, v11, v23); // fabd d11, d11, d23
__ fmuld(v7, v29, v23); // fmul d7, d29, d23
__ fdivd(v14, v27, v11); // fdiv d14, d27, d11
__ faddd(v11, v4, v24); // fadd d11, d4, d24
__ fsubd(v12, v15, v14); // fsub d12, d15, d14
// FourRegFloatOp
__ fmadds(v20, v11, v28, v13); // fmadd s20, s11, s28, s13
__ fmsubs(v11, v12, v23, v30); // fmsub s11, s12, s23, s30
__ fnmadds(v26, v14, v9, v13); // fnmadd s26, s14, s9, s13
__ fnmadds(v10, v7, v5, v29); // fnmadd s10, s7, s5, s29
__ fmaddd(v15, v3, v11, v12); // fmadd d15, d3, d11, d12
__ fmsubd(v15, v30, v30, v17); // fmsub d15, d30, d30, d17
__ fnmaddd(v19, v20, v15, v15); // fnmadd d19, d20, d15, d15
__ fnmaddd(v9, v21, v2, v9); // fnmadd d9, d21, d2, d9
// TwoRegFloatOp
__ fmovs(v27, v7); // fmov s27, s7
__ fabss(v29, v30); // fabs s29, s30
__ fnegs(v17, v1); // fneg s17, s1
__ fsqrts(v2, v6); // fsqrt s2, s6
__ fcvts(v10, v3); // fcvt d10, s3
__ fmovd(v24, v11); // fmov d24, d11
__ fabsd(v7, v1); // fabs d7, d1
__ fnegd(v11, v0); // fneg d11, d0
__ fsqrtd(v3, v17); // fsqrt d3, d17
__ fcvtd(v28, v6); // fcvt s28, d6
// FloatConvertOp
__ fcvtzsw(r22, v6); // fcvtzs w22, s6
__ fcvtzs(r0, v27); // fcvtzs x0, s27
__ fcvtzdw(r26, v2); // fcvtzs w26, d2
__ fcvtzd(r5, v7); // fcvtzs x5, d7
__ scvtfws(v28, r11); // scvtf s28, w11
__ scvtfs(v25, r13); // scvtf s25, x13
__ scvtfwd(v11, r23); // scvtf d11, w23
__ scvtfd(v19, r8); // scvtf d19, x8
__ fmovs(r17, v21); // fmov w17, s21
__ fmovd(r25, v20); // fmov x25, d20
__ fmovs(v19, r17); // fmov s19, w17
__ fmovd(v2, r29); // fmov d2, x29
// TwoRegFloatOp
__ fcmps(v22, v8); // fcmp s22, s8
__ fcmpd(v21, v19); // fcmp d21, d19
__ fcmps(v20, 0.0); // fcmp s20, #0.0
__ fcmpd(v11, 0.0); // fcmp d11, #0.0
// LoadStorePairOp
__ stpw(r20, r6, Address(r15, -32)); // stp w20, w6, [x15, #-32]
__ ldpw(r27, r14, Address(r3, -208)); // ldp w27, w14, [x3, #-208]
__ ldpsw(r16, r10, Address(r11, -80)); // ldpsw x16, x10, [x11, #-80]
__ stp(r7, r7, Address(r14, 64)); // stp x7, x7, [x14, #64]
__ ldp(r12, r23, Address(r0, 112)); // ldp x12, x23, [x0, #112]
// LoadStorePairOp
__ stpw(r13, r7, Address(__ pre(r6, -80))); // stp w13, w7, [x6, #-80]!
__ ldpw(r30, r15, Address(__ pre(r2, -144))); // ldp w30, w15, [x2, #-144]!
__ ldpsw(r4, r1, Address(__ pre(r27, -144))); // ldpsw x4, x1, [x27, #-144]!
__ stp(r23, r14, Address(__ pre(r11, 64))); // stp x23, x14, [x11, #64]!
__ ldp(r29, r27, Address(__ pre(r21, -192))); // ldp x29, x27, [x21, #-192]!
// LoadStorePairOp
__ stpw(r22, r5, Address(__ post(r21, -48))); // stp w22, w5, [x21], #-48
__ ldpw(r27, r17, Address(__ post(r6, -32))); // ldp w27, w17, [x6], #-32
__ ldpsw(r16, r5, Address(__ post(r1, -80))); // ldpsw x16, x5, [x1], #-80
__ stp(r13, r20, Address(__ post(r22, -208))); // stp x13, x20, [x22], #-208
__ ldp(r30, r27, Address(__ post(r10, 80))); // ldp x30, x27, [x10], #80
// LoadStorePairOp
__ stnpw(r5, r17, Address(r11, 16)); // stnp w5, w17, [x11, #16]
__ ldnpw(r14, r4, Address(r26, -96)); // ldnp w14, w4, [x26, #-96]
__ stnp(r23, r29, Address(r12, 32)); // stnp x23, x29, [x12, #32]
__ ldnp(r0, r6, Address(r21, -80)); // ldnp x0, x6, [x21, #-80]
// LdStNEONOp
__ ld1(v15, __ T8B, Address(r26)); // ld1 {v15.8B}, [x26]
__ ld1(v23, v24, __ T16B, Address(__ post(r11, 32))); // ld1 {v23.16B, v24.16B}, [x11], 32
__ ld1(v8, v9, v10, __ T1D, Address(__ post(r23, r7))); // ld1 {v8.1D, v9.1D, v10.1D}, [x23], x7
__ ld1(v19, v20, v21, v22, __ T8H, Address(__ post(r25, 64))); // ld1 {v19.8H, v20.8H, v21.8H, v22.8H}, [x25], 64
__ ld1r(v29, __ T8B, Address(r17)); // ld1r {v29.8B}, [x17]
__ ld1r(v24, __ T4S, Address(__ post(r23, 4))); // ld1r {v24.4S}, [x23], 4
__ ld1r(v10, __ T1D, Address(__ post(r5, r25))); // ld1r {v10.1D}, [x5], x25
__ ld2(v17, v18, __ T2D, Address(r10)); // ld2 {v17.2D, v18.2D}, [x10]
__ ld2(v12, v13, __ T4H, Address(__ post(r15, 16))); // ld2 {v12.4H, v13.4H}, [x15], 16
__ ld2r(v25, v26, __ T16B, Address(r17)); // ld2r {v25.16B, v26.16B}, [x17]
__ ld2r(v1, v2, __ T2S, Address(__ post(r30, 8))); // ld2r {v1.2S, v2.2S}, [x30], 8
__ ld2r(v16, v17, __ T2D, Address(__ post(r17, r9))); // ld2r {v16.2D, v17.2D}, [x17], x9
__ ld3(v25, v26, v27, __ T4S, Address(__ post(r12, r2))); // ld3 {v25.4S, v26.4S, v27.4S}, [x12], x2
__ ld3(v26, v27, v28, __ T2S, Address(r19)); // ld3 {v26.2S, v27.2S, v28.2S}, [x19]
__ ld3r(v15, v16, v17, __ T8H, Address(r21)); // ld3r {v15.8H, v16.8H, v17.8H}, [x21]
__ ld3r(v25, v26, v27, __ T4S, Address(__ post(r13, 12))); // ld3r {v25.4S, v26.4S, v27.4S}, [x13], 12
__ ld3r(v14, v15, v16, __ T1D, Address(__ post(r28, r29))); // ld3r {v14.1D, v15.1D, v16.1D}, [x28], x29
__ ld4(v17, v18, v19, v20, __ T8H, Address(__ post(r29, 64))); // ld4 {v17.8H, v18.8H, v19.8H, v20.8H}, [x29], 64
__ ld4(v27, v28, v29, v30, __ T8B, Address(__ post(r7, r0))); // ld4 {v27.8B, v28.8B, v29.8B, v30.8B}, [x7], x0
__ ld4r(v24, v25, v26, v27, __ T8B, Address(r17)); // ld4r {v24.8B, v25.8B, v26.8B, v27.8B}, [x17]
__ ld4r(v0, v1, v2, v3, __ T4H, Address(__ post(r26, 8))); // ld4r {v0.4H, v1.4H, v2.4H, v3.4H}, [x26], 8
__ ld4r(v12, v13, v14, v15, __ T2S, Address(__ post(r25, r2))); // ld4r {v12.2S, v13.2S, v14.2S, v15.2S}, [x25], x2
// NEONReduceInstruction
__ addv(v22, __ T8B, v23); // addv b22, v23.8B
__ addv(v27, __ T16B, v28); // addv b27, v28.16B
__ addv(v4, __ T4H, v5); // addv h4, v5.4H
__ addv(v7, __ T8H, v8); // addv h7, v8.8H
__ addv(v6, __ T4S, v7); // addv s6, v7.4S
__ smaxv(v1, __ T8B, v2); // smaxv b1, v2.8B
__ smaxv(v26, __ T16B, v27); // smaxv b26, v27.16B
__ smaxv(v15, __ T4H, v16); // smaxv h15, v16.4H
__ smaxv(v2, __ T8H, v3); // smaxv h2, v3.8H
__ smaxv(v13, __ T4S, v14); // smaxv s13, v14.4S
__ fmaxv(v13, __ T4S, v14); // fmaxv s13, v14.4S
__ sminv(v24, __ T8B, v25); // sminv b24, v25.8B
__ uminv(v23, __ T8B, v24); // uminv b23, v24.8B
__ sminv(v4, __ T16B, v5); // sminv b4, v5.16B
__ uminv(v19, __ T16B, v20); // uminv b19, v20.16B
__ sminv(v15, __ T4H, v16); // sminv h15, v16.4H
__ uminv(v0, __ T4H, v1); // uminv h0, v1.4H
__ sminv(v4, __ T8H, v5); // sminv h4, v5.8H
__ uminv(v20, __ T8H, v21); // uminv h20, v21.8H
__ sminv(v11, __ T4S, v12); // sminv s11, v12.4S
__ uminv(v29, __ T4S, v30); // uminv s29, v30.4S
__ fminv(v15, __ T4S, v16); // fminv s15, v16.4S
__ fmaxp(v21, v22, __ S); // fmaxp s21, v22.2S
__ fmaxp(v4, v5, __ D); // fmaxp d4, v5.2D
__ fminp(v14, v15, __ S); // fminp s14, v15.2S
__ fminp(v22, v23, __ D); // fminp d22, v23.2D
// TwoRegNEONOp
__ absr(v25, __ T8B, v26); // abs v25.8B, v26.8B
__ absr(v6, __ T16B, v7); // abs v6.16B, v7.16B
__ absr(v12, __ T4H, v13); // abs v12.4H, v13.4H
__ absr(v14, __ T8H, v15); // abs v14.8H, v15.8H
__ absr(v13, __ T2S, v14); // abs v13.2S, v14.2S
__ absr(v14, __ T4S, v15); // abs v14.4S, v15.4S
__ absr(v9, __ T2D, v10); // abs v9.2D, v10.2D
__ fabs(v25, __ T2S, v26); // fabs v25.2S, v26.2S
__ fabs(v28, __ T4S, v29); // fabs v28.4S, v29.4S
__ fabs(v10, __ T2D, v11); // fabs v10.2D, v11.2D
__ fneg(v19, __ T2S, v20); // fneg v19.2S, v20.2S
__ fneg(v11, __ T4S, v12); // fneg v11.4S, v12.4S
__ fneg(v17, __ T2D, v18); // fneg v17.2D, v18.2D
__ fsqrt(v21, __ T2S, v22); // fsqrt v21.2S, v22.2S
__ fsqrt(v15, __ T4S, v16); // fsqrt v15.4S, v16.4S
__ fsqrt(v20, __ T2D, v21); // fsqrt v20.2D, v21.2D
__ notr(v23, __ T8B, v24); // not v23.8B, v24.8B
__ notr(v26, __ T16B, v27); // not v26.16B, v27.16B
// ThreeRegNEONOp
__ andr(v5, __ T8B, v6, v7); // and v5.8B, v6.8B, v7.8B
__ andr(v6, __ T16B, v7, v8); // and v6.16B, v7.16B, v8.16B
__ orr(v15, __ T8B, v16, v17); // orr v15.8B, v16.8B, v17.8B
__ orr(v15, __ T16B, v16, v17); // orr v15.16B, v16.16B, v17.16B
__ eor(v25, __ T8B, v26, v27); // eor v25.8B, v26.8B, v27.8B
__ eor(v16, __ T16B, v17, v18); // eor v16.16B, v17.16B, v18.16B
__ addv(v27, __ T8B, v28, v29); // add v27.8B, v28.8B, v29.8B
__ addv(v24, __ T16B, v25, v26); // add v24.16B, v25.16B, v26.16B
__ addv(v15, __ T4H, v16, v17); // add v15.4H, v16.4H, v17.4H
__ addv(v25, __ T8H, v26, v27); // add v25.8H, v26.8H, v27.8H
__ addv(v14, __ T2S, v15, v16); // add v14.2S, v15.2S, v16.2S
__ addv(v10, __ T4S, v11, v12); // add v10.4S, v11.4S, v12.4S
__ addv(v13, __ T2D, v14, v15); // add v13.2D, v14.2D, v15.2D
__ fadd(v14, __ T2S, v15, v16); // fadd v14.2S, v15.2S, v16.2S
__ fadd(v20, __ T4S, v21, v22); // fadd v20.4S, v21.4S, v22.4S
__ fadd(v1, __ T2D, v2, v3); // fadd v1.2D, v2.2D, v3.2D
__ subv(v22, __ T8B, v23, v24); // sub v22.8B, v23.8B, v24.8B
__ subv(v30, __ T16B, v31, v0); // sub v30.16B, v31.16B, v0.16B
__ subv(v14, __ T4H, v15, v16); // sub v14.4H, v15.4H, v16.4H
__ subv(v2, __ T8H, v3, v4); // sub v2.8H, v3.8H, v4.8H
__ subv(v6, __ T2S, v7, v8); // sub v6.2S, v7.2S, v8.2S
__ subv(v3, __ T4S, v4, v5); // sub v3.4S, v4.4S, v5.4S
__ subv(v7, __ T2D, v8, v9); // sub v7.2D, v8.2D, v9.2D
__ fsub(v24, __ T2S, v25, v26); // fsub v24.2S, v25.2S, v26.2S
__ fsub(v0, __ T4S, v1, v2); // fsub v0.4S, v1.4S, v2.4S
__ fsub(v27, __ T2D, v28, v29); // fsub v27.2D, v28.2D, v29.2D
__ mulv(v29, __ T8B, v30, v31); // mul v29.8B, v30.8B, v31.8B
__ mulv(v5, __ T16B, v6, v7); // mul v5.16B, v6.16B, v7.16B
__ mulv(v5, __ T4H, v6, v7); // mul v5.4H, v6.4H, v7.4H
__ mulv(v29, __ T8H, v30, v31); // mul v29.8H, v30.8H, v31.8H
__ mulv(v11, __ T2S, v12, v13); // mul v11.2S, v12.2S, v13.2S
__ mulv(v25, __ T4S, v26, v27); // mul v25.4S, v26.4S, v27.4S
__ fabd(v0, __ T2S, v1, v2); // fabd v0.2S, v1.2S, v2.2S
__ fabd(v30, __ T4S, v31, v0); // fabd v30.4S, v31.4S, v0.4S
__ fabd(v0, __ T2D, v1, v2); // fabd v0.2D, v1.2D, v2.2D
__ fmul(v17, __ T2S, v18, v19); // fmul v17.2S, v18.2S, v19.2S
__ fmul(v28, __ T4S, v29, v30); // fmul v28.4S, v29.4S, v30.4S
__ fmul(v25, __ T2D, v26, v27); // fmul v25.2D, v26.2D, v27.2D
__ mlav(v9, __ T4H, v10, v11); // mla v9.4H, v10.4H, v11.4H
__ mlav(v25, __ T8H, v26, v27); // mla v25.8H, v26.8H, v27.8H
__ mlav(v12, __ T2S, v13, v14); // mla v12.2S, v13.2S, v14.2S
__ mlav(v15, __ T4S, v16, v17); // mla v15.4S, v16.4S, v17.4S
__ fmla(v11, __ T2S, v12, v13); // fmla v11.2S, v12.2S, v13.2S
__ fmla(v10, __ T4S, v11, v12); // fmla v10.4S, v11.4S, v12.4S
__ fmla(v17, __ T2D, v18, v19); // fmla v17.2D, v18.2D, v19.2D
__ mlsv(v24, __ T4H, v25, v26); // mls v24.4H, v25.4H, v26.4H
__ mlsv(v21, __ T8H, v22, v23); // mls v21.8H, v22.8H, v23.8H
__ mlsv(v23, __ T2S, v24, v25); // mls v23.2S, v24.2S, v25.2S
__ mlsv(v0, __ T4S, v1, v2); // mls v0.4S, v1.4S, v2.4S
__ fmls(v16, __ T2S, v17, v18); // fmls v16.2S, v17.2S, v18.2S
__ fmls(v10, __ T4S, v11, v12); // fmls v10.4S, v11.4S, v12.4S
__ fmls(v6, __ T2D, v7, v8); // fmls v6.2D, v7.2D, v8.2D
__ fdiv(v28, __ T2S, v29, v30); // fdiv v28.2S, v29.2S, v30.2S
__ fdiv(v6, __ T4S, v7, v8); // fdiv v6.4S, v7.4S, v8.4S
__ fdiv(v5, __ T2D, v6, v7); // fdiv v5.2D, v6.2D, v7.2D
__ maxv(v5, __ T8B, v6, v7); // smax v5.8B, v6.8B, v7.8B
__ maxv(v20, __ T16B, v21, v22); // smax v20.16B, v21.16B, v22.16B
__ maxv(v17, __ T4H, v18, v19); // smax v17.4H, v18.4H, v19.4H
__ maxv(v15, __ T8H, v16, v17); // smax v15.8H, v16.8H, v17.8H
__ maxv(v17, __ T2S, v18, v19); // smax v17.2S, v18.2S, v19.2S
__ maxv(v29, __ T4S, v30, v31); // smax v29.4S, v30.4S, v31.4S
__ fmax(v26, __ T2S, v27, v28); // fmax v26.2S, v27.2S, v28.2S
__ fmax(v28, __ T4S, v29, v30); // fmax v28.4S, v29.4S, v30.4S
__ fmax(v1, __ T2D, v2, v3); // fmax v1.2D, v2.2D, v3.2D
__ minv(v27, __ T8B, v28, v29); // smin v27.8B, v28.8B, v29.8B
__ minv(v0, __ T16B, v1, v2); // smin v0.16B, v1.16B, v2.16B
__ minv(v20, __ T4H, v21, v22); // smin v20.4H, v21.4H, v22.4H
__ minv(v28, __ T8H, v29, v30); // smin v28.8H, v29.8H, v30.8H
__ minv(v15, __ T2S, v16, v17); // smin v15.2S, v16.2S, v17.2S
__ minv(v12, __ T4S, v13, v14); // smin v12.4S, v13.4S, v14.4S
__ fmin(v10, __ T2S, v11, v12); // fmin v10.2S, v11.2S, v12.2S
__ fmin(v28, __ T4S, v29, v30); // fmin v28.4S, v29.4S, v30.4S
__ fmin(v28, __ T2D, v29, v30); // fmin v28.2D, v29.2D, v30.2D
__ cmeq(v19, __ T8B, v20, v21); // cmeq v19.8B, v20.8B, v21.8B
__ cmeq(v22, __ T16B, v23, v24); // cmeq v22.16B, v23.16B, v24.16B
__ cmeq(v10, __ T4H, v11, v12); // cmeq v10.4H, v11.4H, v12.4H
__ cmeq(v4, __ T8H, v5, v6); // cmeq v4.8H, v5.8H, v6.8H
__ cmeq(v30, __ T2S, v31, v0); // cmeq v30.2S, v31.2S, v0.2S
__ cmeq(v20, __ T4S, v21, v22); // cmeq v20.4S, v21.4S, v22.4S
__ cmeq(v8, __ T2D, v9, v10); // cmeq v8.2D, v9.2D, v10.2D
__ fcmeq(v30, __ T2S, v31, v0); // fcmeq v30.2S, v31.2S, v0.2S
__ fcmeq(v17, __ T4S, v18, v19); // fcmeq v17.4S, v18.4S, v19.4S
__ fcmeq(v10, __ T2D, v11, v12); // fcmeq v10.2D, v11.2D, v12.2D
__ cmgt(v27, __ T8B, v28, v29); // cmgt v27.8B, v28.8B, v29.8B
__ cmgt(v2, __ T16B, v3, v4); // cmgt v2.16B, v3.16B, v4.16B
__ cmgt(v24, __ T4H, v25, v26); // cmgt v24.4H, v25.4H, v26.4H
__ cmgt(v4, __ T8H, v5, v6); // cmgt v4.8H, v5.8H, v6.8H
__ cmgt(v3, __ T2S, v4, v5); // cmgt v3.2S, v4.2S, v5.2S
__ cmgt(v8, __ T4S, v9, v10); // cmgt v8.4S, v9.4S, v10.4S
__ cmgt(v22, __ T2D, v23, v24); // cmgt v22.2D, v23.2D, v24.2D
__ fcmgt(v17, __ T2S, v18, v19); // fcmgt v17.2S, v18.2S, v19.2S
__ fcmgt(v13, __ T4S, v14, v15); // fcmgt v13.4S, v14.4S, v15.4S
__ fcmgt(v4, __ T2D, v5, v6); // fcmgt v4.2D, v5.2D, v6.2D
__ cmge(v28, __ T8B, v29, v30); // cmge v28.8B, v29.8B, v30.8B
__ cmge(v23, __ T16B, v24, v25); // cmge v23.16B, v24.16B, v25.16B
__ cmge(v21, __ T4H, v22, v23); // cmge v21.4H, v22.4H, v23.4H
__ cmge(v25, __ T8H, v26, v27); // cmge v25.8H, v26.8H, v27.8H
__ cmge(v24, __ T2S, v25, v26); // cmge v24.2S, v25.2S, v26.2S
__ cmge(v3, __ T4S, v4, v5); // cmge v3.4S, v4.4S, v5.4S
__ cmge(v23, __ T2D, v24, v25); // cmge v23.2D, v24.2D, v25.2D
__ fcmge(v26, __ T2S, v27, v28); // fcmge v26.2S, v27.2S, v28.2S
__ fcmge(v23, __ T4S, v24, v25); // fcmge v23.4S, v24.4S, v25.4S
__ fcmge(v14, __ T2D, v15, v16); // fcmge v14.2D, v15.2D, v16.2D
// SpecialCases
__ ccmn(zr, zr, 3u, Assembler::LE); // ccmn xzr, xzr, #3, LE
__ ccmnw(zr, zr, 5u, Assembler::EQ); // ccmn wzr, wzr, #5, EQ
__ ccmp(zr, 1, 4u, Assembler::NE); // ccmp xzr, 1, #4, NE
__ ccmpw(zr, 2, 2, Assembler::GT); // ccmp wzr, 2, #2, GT
__ extr(zr, zr, zr, 0); // extr xzr, xzr, xzr, 0
__ stlxp(r0, zr, zr, sp); // stlxp w0, xzr, xzr, [sp]
__ stlxpw(r2, zr, zr, r3); // stlxp w2, wzr, wzr, [x3]
__ stxp(r4, zr, zr, r5); // stxp w4, xzr, xzr, [x5]
__ stxpw(r6, zr, zr, sp); // stxp w6, wzr, wzr, [sp]
__ dup(v0, __ T16B, zr); // dup v0.16b, wzr
__ mov(v1, __ T1D, 0, zr); // mov v1.d[0], xzr
__ mov(v1, __ T2S, 1, zr); // mov v1.s[1], wzr
__ mov(v1, __ T4H, 2, zr); // mov v1.h[2], wzr
__ mov(v1, __ T8B, 3, zr); // mov v1.b[3], wzr
__ smov(r0, v1, __ S, 0); // smov x0, v1.s[0]
__ smov(r0, v1, __ H, 1); // smov x0, v1.h[1]
__ smov(r0, v1, __ B, 2); // smov x0, v1.b[2]
__ umov(r0, v1, __ D, 0); // umov x0, v1.d[0]
__ umov(r0, v1, __ S, 1); // umov w0, v1.s[1]
__ umov(r0, v1, __ H, 2); // umov w0, v1.h[2]
__ umov(r0, v1, __ B, 3); // umov w0, v1.b[3]
__ ld1(v31, v0, __ T2D, Address(__ post(r1, r0))); // ld1 {v31.2d, v0.2d}, [x1], x0
__ sve_cpy(z0, __ S, p0, v1); // mov z0.s, p0/m, s1
__ sve_inc(r0, __ S); // incw x0
__ sve_dec(r1, __ H); // dech x1
__ sve_lsl(z0, __ B, z1, 7); // lsl z0.b, z1.b, #7
__ sve_lsl(z21, __ H, z1, 15); // lsl z21.h, z1.h, #15
__ sve_lsl(z0, __ S, z1, 31); // lsl z0.s, z1.s, #31
__ sve_lsl(z0, __ D, z1, 63); // lsl z0.d, z1.d, #63
__ sve_lsr(z0, __ B, z1, 7); // lsr z0.b, z1.b, #7
__ sve_asr(z0, __ H, z11, 15); // asr z0.h, z11.h, #15
__ sve_lsr(z30, __ S, z1, 31); // lsr z30.s, z1.s, #31
__ sve_asr(z0, __ D, z1, 63); // asr z0.d, z1.d, #63
__ sve_addvl(sp, r0, 31); // addvl sp, x0, #31
__ sve_addpl(r1, sp, -32); // addpl x1, sp, -32
__ sve_cntp(r8, __ B, p0, p1); // cntp x8, p0, p1.b
__ sve_dup(z0, __ B, 127); // dup z0.b, 127
__ sve_dup(z1, __ H, -128); // dup z1.h, -128
__ sve_dup(z2, __ S, 32512); // dup z2.s, 32512
__ sve_dup(z7, __ D, -32768); // dup z7.d, -32768
__ sve_ld1b(z0, __ B, p0, Address(sp)); // ld1b {z0.b}, p0/z, [sp]
__ sve_ld1h(z10, __ H, p1, Address(sp, -8)); // ld1h {z10.h}, p1/z, [sp, #-8, MUL VL]
__ sve_ld1w(z20, __ S, p2, Address(r0, 7)); // ld1w {z20.s}, p2/z, [x0, #7, MUL VL]
__ sve_ld1b(z30, __ B, p3, Address(sp, r8)); // ld1b {z30.b}, p3/z, [sp, x8]
__ sve_ld1w(z0, __ S, p4, Address(sp, r28)); // ld1w {z0.s}, p4/z, [sp, x28, LSL #2]
__ sve_ld1d(z11, __ D, p5, Address(r0, r1)); // ld1d {z11.d}, p5/z, [x0, x1, LSL #3]
__ sve_st1b(z22, __ B, p6, Address(sp)); // st1b {z22.b}, p6, [sp]
__ sve_st1b(z31, __ B, p7, Address(sp, -8)); // st1b {z31.b}, p7, [sp, #-8, MUL VL]
__ sve_st1w(z0, __ S, p1, Address(r0, 7)); // st1w {z0.s}, p1, [x0, #7, MUL VL]
__ sve_st1b(z0, __ B, p2, Address(sp, r1)); // st1b {z0.b}, p2, [sp, x1]
__ sve_st1h(z0, __ H, p3, Address(sp, r8)); // st1h {z0.h}, p3, [sp, x8, LSL #1]
__ sve_st1d(z0, __ D, p4, Address(r0, r17)); // st1d {z0.d}, p4, [x0, x17, LSL #3]
__ sve_ldr(z0, Address(sp)); // ldr z0, [sp]
__ sve_ldr(z31, Address(sp, -256)); // ldr z31, [sp, #-256, MUL VL]
__ sve_str(z8, Address(r8, 255)); // str z8, [x8, #255, MUL VL]
// FloatImmediateOp
__ fmovd(v0, 2.0); // fmov d0, #2.0
__ fmovd(v0, 2.125); // fmov d0, #2.125
__ fmovd(v0, 4.0); // fmov d0, #4.0
__ fmovd(v0, 4.25); // fmov d0, #4.25
__ fmovd(v0, 8.0); // fmov d0, #8.0
__ fmovd(v0, 8.5); // fmov d0, #8.5
__ fmovd(v0, 16.0); // fmov d0, #16.0
__ fmovd(v0, 17.0); // fmov d0, #17.0
__ fmovd(v0, 0.125); // fmov d0, #0.125
__ fmovd(v0, 0.1328125); // fmov d0, #0.1328125
__ fmovd(v0, 0.25); // fmov d0, #0.25
__ fmovd(v0, 0.265625); // fmov d0, #0.265625
__ fmovd(v0, 0.5); // fmov d0, #0.5
__ fmovd(v0, 0.53125); // fmov d0, #0.53125
__ fmovd(v0, 1.0); // fmov d0, #1.0
__ fmovd(v0, 1.0625); // fmov d0, #1.0625
__ fmovd(v0, -2.0); // fmov d0, #-2.0
__ fmovd(v0, -2.125); // fmov d0, #-2.125
__ fmovd(v0, -4.0); // fmov d0, #-4.0
__ fmovd(v0, -4.25); // fmov d0, #-4.25
__ fmovd(v0, -8.0); // fmov d0, #-8.0
__ fmovd(v0, -8.5); // fmov d0, #-8.5
__ fmovd(v0, -16.0); // fmov d0, #-16.0
__ fmovd(v0, -17.0); // fmov d0, #-17.0
__ fmovd(v0, -0.125); // fmov d0, #-0.125
__ fmovd(v0, -0.1328125); // fmov d0, #-0.1328125
__ fmovd(v0, -0.25); // fmov d0, #-0.25
__ fmovd(v0, -0.265625); // fmov d0, #-0.265625
__ fmovd(v0, -0.5); // fmov d0, #-0.5
__ fmovd(v0, -0.53125); // fmov d0, #-0.53125
__ fmovd(v0, -1.0); // fmov d0, #-1.0
__ fmovd(v0, -1.0625); // fmov d0, #-1.0625
// LSEOp
__ swp(Assembler::xword, r21, r3, r24); // swp x21, x3, [x24]
__ ldadd(Assembler::xword, r8, r25, r20); // ldadd x8, x25, [x20]
__ ldbic(Assembler::xword, r16, r17, r2); // ldclr x16, x17, [x2]
__ ldeor(Assembler::xword, r1, r0, r24); // ldeor x1, x0, [x24]
__ ldorr(Assembler::xword, r4, r3, r12); // ldset x4, x3, [x12]
__ ldsmin(Assembler::xword, zr, r28, r10); // ldsmin xzr, x28, [x10]
__ ldsmax(Assembler::xword, r26, r2, r12); // ldsmax x26, x2, [x12]
__ ldumin(Assembler::xword, r16, zr, r1); // ldumin x16, xzr, [x1]
__ ldumax(Assembler::xword, r13, r29, r0); // ldumax x13, x29, [x0]
// LSEOp
__ swpa(Assembler::xword, r19, r12, r17); // swpa x19, x12, [x17]
__ ldadda(Assembler::xword, r22, r13, r28); // ldadda x22, x13, [x28]
__ ldbica(Assembler::xword, r30, zr, r1); // ldclra x30, xzr, [x1]
__ ldeora(Assembler::xword, r26, r28, r4); // ldeora x26, x28, [x4]
__ ldorra(Assembler::xword, r30, r4, r6); // ldseta x30, x4, [x6]
__ ldsmina(Assembler::xword, r30, r26, r15); // ldsmina x30, x26, [x15]
__ ldsmaxa(Assembler::xword, r9, r8, r12); // ldsmaxa x9, x8, [x12]
__ ldumina(Assembler::xword, r0, r20, r1); // ldumina x0, x20, [x1]
__ ldumaxa(Assembler::xword, r24, r2, r0); // ldumaxa x24, x2, [x0]
// LSEOp
__ swpal(Assembler::xword, r9, r24, r26); // swpal x9, x24, [x26]
__ ldaddal(Assembler::xword, r16, r30, r3); // ldaddal x16, x30, [x3]
__ ldbical(Assembler::xword, r10, r23, r10); // ldclral x10, x23, [x10]
__ ldeoral(Assembler::xword, r4, r16, r2); // ldeoral x4, x16, [x2]
__ ldorral(Assembler::xword, r11, r8, r10); // ldsetal x11, x8, [x10]
__ ldsminal(Assembler::xword, r15, r17, r2); // ldsminal x15, x17, [x2]
__ ldsmaxal(Assembler::xword, r10, r12, r12); // ldsmaxal x10, x12, [x12]
__ lduminal(Assembler::xword, r15, r13, r2); // lduminal x15, x13, [x2]
__ ldumaxal(Assembler::xword, r7, r20, r26); // ldumaxal x7, x20, [x26]
// LSEOp
__ swpl(Assembler::xword, r16, r4, r2); // swpl x16, x4, [x2]
__ ldaddl(Assembler::xword, r4, r12, r15); // ldaddl x4, x12, [x15]
__ ldbicl(Assembler::xword, r21, r16, r15); // ldclrl x21, x16, [x15]
__ ldeorl(Assembler::xword, r11, r21, r23); // ldeorl x11, x21, [x23]
__ ldorrl(Assembler::xword, r12, r26, r23); // ldsetl x12, x26, [x23]
__ ldsminl(Assembler::xword, r28, r14, r11); // ldsminl x28, x14, [x11]
__ ldsmaxl(Assembler::xword, r24, r1, r12); // ldsmaxl x24, x1, [x12]
__ lduminl(Assembler::xword, zr, r10, r16); // lduminl xzr, x10, [x16]
__ ldumaxl(Assembler::xword, r7, r2, r3); // ldumaxl x7, x2, [x3]
// LSEOp
__ swp(Assembler::word, r13, r19, r17); // swp w13, w19, [x17]
__ ldadd(Assembler::word, r16, r3, r1); // ldadd w16, w3, [x1]
__ ldbic(Assembler::word, r11, r30, r5); // ldclr w11, w30, [x5]
__ ldeor(Assembler::word, r8, r15, r29); // ldeor w8, w15, [x29]
__ ldorr(Assembler::word, r30, r0, r20); // ldset w30, w0, [x20]
__ ldsmin(Assembler::word, r7, r20, r23); // ldsmin w7, w20, [x23]
__ ldsmax(Assembler::word, r28, r21, r27); // ldsmax w28, w21, [x27]
__ ldumin(Assembler::word, r25, r5, r1); // ldumin w25, w5, [x1]
__ ldumax(Assembler::word, r23, r16, sp); // ldumax w23, w16, [sp]
// LSEOp
__ swpa(Assembler::word, r5, r12, r9); // swpa w5, w12, [x9]
__ ldadda(Assembler::word, r28, r15, r29); // ldadda w28, w15, [x29]
__ ldbica(Assembler::word, r22, zr, r19); // ldclra w22, wzr, [x19]
__ ldeora(Assembler::word, zr, r5, r14); // ldeora wzr, w5, [x14]
__ ldorra(Assembler::word, r16, zr, r15); // ldseta w16, wzr, [x15]
__ ldsmina(Assembler::word, r27, r20, r16); // ldsmina w27, w20, [x16]
__ ldsmaxa(Assembler::word, r12, r11, r9); // ldsmaxa w12, w11, [x9]
__ ldumina(Assembler::word, r6, r30, r17); // ldumina w6, w30, [x17]
__ ldumaxa(Assembler::word, r27, r28, r30); // ldumaxa w27, w28, [x30]
// LSEOp
__ swpal(Assembler::word, r7, r10, r20); // swpal w7, w10, [x20]
__ ldaddal(Assembler::word, r10, r4, r24); // ldaddal w10, w4, [x24]
__ ldbical(Assembler::word, r17, r17, r22); // ldclral w17, w17, [x22]
__ ldeoral(Assembler::word, r3, r29, r15); // ldeoral w3, w29, [x15]
__ ldorral(Assembler::word, r22, r19, r19); // ldsetal w22, w19, [x19]
__ ldsminal(Assembler::word, r22, r2, r15); // ldsminal w22, w2, [x15]
__ ldsmaxal(Assembler::word, r6, r12, r16); // ldsmaxal w6, w12, [x16]
__ lduminal(Assembler::word, r11, r13, r23); // lduminal w11, w13, [x23]
__ ldumaxal(Assembler::word, r1, r30, r19); // ldumaxal w1, w30, [x19]
// LSEOp
__ swpl(Assembler::word, r5, r17, r2); // swpl w5, w17, [x2]
__ ldaddl(Assembler::word, r16, r22, r13); // ldaddl w16, w22, [x13]
__ ldbicl(Assembler::word, r10, r21, r29); // ldclrl w10, w21, [x29]
__ ldeorl(Assembler::word, r27, r12, r27); // ldeorl w27, w12, [x27]
__ ldorrl(Assembler::word, r3, r1, sp); // ldsetl w3, w1, [sp]
__ ldsminl(Assembler::word, r24, r19, r17); // ldsminl w24, w19, [x17]
__ ldsmaxl(Assembler::word, r9, r28, r27); // ldsmaxl w9, w28, [x27]
__ lduminl(Assembler::word, r15, r7, r21); // lduminl w15, w7, [x21]
__ ldumaxl(Assembler::word, r23, zr, r25); // ldumaxl w23, wzr, [x25]
// SHA3SIMDOp
__ bcax(v2, __ T16B, v30, v26, v17); // bcax v2.16B, v30.16B, v26.16B, v17.16B
__ eor3(v10, __ T16B, v22, v17, v2); // eor3 v10.16B, v22.16B, v17.16B, v2.16B
__ rax1(v17, __ T2D, v0, v24); // rax1 v17.2D, v0.2D, v24.2D
__ xar(v25, __ T2D, v22, v2, 37); // xar v25.2D, v22.2D, v2.2D, #37
// SHA512SIMDOp
__ sha512h(v12, __ T2D, v3, v27); // sha512h q12, q3, v27.2D
__ sha512h2(v29, __ T2D, v28, v16); // sha512h2 q29, q28, v16.2D
__ sha512su0(v26, __ T2D, v6); // sha512su0 v26.2D, v6.2D
__ sha512su1(v9, __ T2D, v28, v17); // sha512su1 v9.2D, v28.2D, v17.2D
// SVEVectorOp
__ sve_add(z7, __ H, z4, z7); // add z7.h, z4.h, z7.h
__ sve_sub(z9, __ B, z22, z8); // sub z9.b, z22.b, z8.b
__ sve_fadd(z27, __ S, z20, z30); // fadd z27.s, z20.s, z30.s
__ sve_fmul(z26, __ S, z0, z16); // fmul z26.s, z0.s, z16.s
__ sve_fsub(z3, __ D, z25, z8); // fsub z3.d, z25.d, z8.d
__ sve_abs(z21, __ D, p6, z26); // abs z21.d, p6/m, z26.d
__ sve_add(z22, __ B, p0, z4); // add z22.b, p0/m, z22.b, z4.b
__ sve_asr(z17, __ H, p0, z3); // asr z17.h, p0/m, z17.h, z3.h
__ sve_cnt(z1, __ B, p2, z6); // cnt z1.b, p2/m, z6.b
__ sve_lsl(z9, __ S, p7, z7); // lsl z9.s, p7/m, z9.s, z7.s
__ sve_lsr(z22, __ H, p5, z5); // lsr z22.h, p5/m, z22.h, z5.h
__ sve_mul(z8, __ B, p4, z30); // mul z8.b, p4/m, z8.b, z30.b
__ sve_neg(z17, __ D, p0, z11); // neg z17.d, p0/m, z11.d
__ sve_not(z28, __ S, p0, z26); // not z28.s, p0/m, z26.s
__ sve_smax(z28, __ D, p3, z13); // smax z28.d, p3/m, z28.d, z13.d
__ sve_smin(z16, __ B, p6, z5); // smin z16.b, p6/m, z16.b, z5.b
__ sve_sub(z13, __ H, p2, z15); // sub z13.h, p2/m, z13.h, z15.h
__ sve_fabs(z26, __ S, p5, z11); // fabs z26.s, p5/m, z11.s
__ sve_fadd(z22, __ S, p4, z4); // fadd z22.s, p4/m, z22.s, z4.s
__ sve_fdiv(z19, __ S, p4, z17); // fdiv z19.s, p4/m, z19.s, z17.s
__ sve_fmax(z14, __ D, p3, z2); // fmax z14.d, p3/m, z14.d, z2.d
__ sve_fmin(z3, __ S, p5, z23); // fmin z3.s, p5/m, z3.s, z23.s
__ sve_fmul(z6, __ S, p1, z17); // fmul z6.s, p1/m, z6.s, z17.s
__ sve_fneg(z27, __ S, p4, z16); // fneg z27.s, p4/m, z16.s
__ sve_frintm(z2, __ S, p7, z3); // frintm z2.s, p7/m, z3.s
__ sve_frintn(z6, __ S, p4, z19); // frintn z6.s, p4/m, z19.s
__ sve_frintp(z12, __ D, p5, z8); // frintp z12.d, p5/m, z8.d
__ sve_fsqrt(z19, __ S, p4, z0); // fsqrt z19.s, p4/m, z0.s
__ sve_fsub(z23, __ D, p1, z19); // fsub z23.d, p1/m, z23.d, z19.d
__ sve_fmla(z13, __ S, p4, z6, z0); // fmla z13.s, p4/m, z6.s, z0.s
__ sve_fmls(z14, __ S, p4, z25, z8); // fmls z14.s, p4/m, z25.s, z8.s
__ sve_fnmla(z22, __ S, p5, z22, z27); // fnmla z22.s, p5/m, z22.s, z27.s
__ sve_fnmls(z3, __ S, p3, z17, z20); // fnmls z3.s, p3/m, z17.s, z20.s
__ sve_mla(z4, __ H, p7, z7, z0); // mla z4.h, p7/m, z7.h, z0.h
__ sve_mls(z16, __ S, p5, z22, z4); // mls z16.s, p5/m, z22.s, z4.s
__ sve_and(z9, z22, z11); // and z9.d, z22.d, z11.d
__ sve_eor(z5, z30, z16); // eor z5.d, z30.d, z16.d
__ sve_orr(z22, z11, z1); // orr z22.d, z11.d, z1.d
__ sve_bic(z8, z20, z16); // bic z8.d, z20.d, z16.d
// SVEReductionOp
__ sve_andv(v15, __ S, p1, z4); // andv s15, p1, z4.s
__ sve_orv(v8, __ B, p1, z29); // orv b8, p1, z29.b
__ sve_eorv(v28, __ D, p4, z29); // eorv d28, p4, z29.d
__ sve_smaxv(v9, __ H, p3, z2); // smaxv h9, p3, z2.h
__ sve_sminv(v28, __ B, p0, z7); // sminv b28, p0, z7.b
__ sve_fminv(v26, __ S, p5, z17); // fminv s26, p5, z17.s
__ sve_fmaxv(v8, __ D, p4, z21); // fmaxv d8, p4, z21.d
__ sve_fadda(v5, __ D, p5, z21); // fadda d5, p5, d5, z21.d
__ sve_uaddv(v22, __ S, p4, z29); // uaddv d22, p4, z29.s
__ bind(forth);
/*
*/
static const unsigned int insns[] =
{
0x8b0d82fa, 0xcb49970c, 0xab889dfc, 0xeb9ee787,
0x0b9b3ec9, 0x4b9179a3, 0x2b88474e, 0x6b8c56c0,
0x8a1a51e0, 0xaa11f4ba, 0xca0281b8, 0xea918c7c,
0x0a5d4a19, 0x2a4b262d, 0x4a513ca5, 0x6a9b6ae2,
0x8a70b79b, 0xaaba9728, 0xca6dfe3d, 0xea627f1c,
0x0aa70f53, 0x2aaa0f06, 0x4a6176a4, 0x6a604eb0,
0x1105ed91, 0x3100583e, 0x5101f8bd, 0x710f0306,
0x9101a1a0, 0xb10a5cc8, 0xd10810aa, 0xf10fd061,
0x120cb166, 0x321764bc, 0x52174681, 0x720c0227,
0x9241018e, 0xb25a2969, 0xd278b411, 0xf26aad01,
0x14000000, 0x17ffffd7, 0x140002e1, 0x94000000,
0x97ffffd4, 0x940002de, 0x3400000a, 0x34fffa2a,
0x34005b6a, 0x35000008, 0x35fff9c8, 0x35005b08,
0xb400000b, 0xb4fff96b, 0xb4005aab, 0xb500001d,
0xb5fff91d, 0xb5005a5d, 0x10000013, 0x10fff8b3,
0x100059f3, 0x90000013, 0x36300016, 0x3637f836,
0x36305976, 0x3758000c, 0x375ff7cc, 0x3758590c,
0x128313a0, 0x528a32c7, 0x7289173b, 0x92ab3acc,
0xd2a0bf94, 0xf2c285e8, 0x9358722f, 0x330e652f,
0x53067f3b, 0x93577c53, 0xb34a1aac, 0xd35a4016,
0x13946c63, 0x93c3dbc8, 0x54000000, 0x54fff5a0,
0x540056e0, 0x54000001, 0x54fff541, 0x54005681,
0x54000002, 0x54fff4e2, 0x54005622, 0x54000002,
0x54fff482, 0x540055c2, 0x54000003, 0x54fff423,
0x54005563, 0x54000003, 0x54fff3c3, 0x54005503,
0x54000004, 0x54fff364, 0x540054a4, 0x54000005,
0x54fff305, 0x54005445, 0x54000006, 0x54fff2a6,
0x540053e6, 0x54000007, 0x54fff247, 0x54005387,
0x54000008, 0x54fff1e8, 0x54005328, 0x54000009,
0x54fff189, 0x540052c9, 0x5400000a, 0x54fff12a,
0x5400526a, 0x5400000b, 0x54fff0cb, 0x5400520b,
0x5400000c, 0x54fff06c, 0x540051ac, 0x5400000d,
0x54fff00d, 0x5400514d, 0x5400000e, 0x54ffefae,
0x540050ee, 0x5400000f, 0x54ffef4f, 0x5400508f,
0xd40658e1, 0xd4014d22, 0xd4046543, 0xd4273f60,
0xd44cad80, 0xd503201f, 0xd69f03e0, 0xd6bf03e0,
0xd5033fdf, 0xd5033e9f, 0xd50332bf, 0xd61f0200,
0xd63f0280, 0xc80a7d1b, 0xc800fea1, 0xc85f7fb1,
0xc85fff9d, 0xc89ffee1, 0xc8dffe95, 0x88167e7b,
0x880bfcd0, 0x885f7c11, 0x885ffd44, 0x889ffed8,
0x88dffe6a, 0x48017fc5, 0x4808fe2c, 0x485f7dc9,
0x485ffc27, 0x489ffe05, 0x48dffd82, 0x080a7c6c,
0x081cff4e, 0x085f7d5e, 0x085ffeae, 0x089ffd2d,
0x08dfff76, 0xc87f4d7c, 0xc87fcc5e, 0xc8220417,
0xc82cb5f0, 0x887f55b1, 0x887ff90b, 0x88382c2d,
0x883aedb5, 0xf819928b, 0xb803e21c, 0x381f713b,
0x781ce322, 0xf850f044, 0xb85e129e, 0x385e92f1,
0x785ff35d, 0x39801921, 0x7881318b, 0x78dce02b,
0xb8829313, 0xfc45f318, 0xbc5d50af, 0xfc001375,
0xbc1951b7, 0xf8008c0a, 0xb801dc03, 0x38009dca,
0x781fdf3d, 0xf8570e0c, 0xb85faecc, 0x385f6d6d,
0x785ebea0, 0x38804cd7, 0x789cbce3, 0x78df9c9c,
0xb89eed18, 0xfc40cd6e, 0xbc5bdd93, 0xfc103c14,
0xbc040c08, 0xf81a2783, 0xb81ca4eb, 0x381e855b,
0x7801b4e6, 0xf853654d, 0xb85d74af, 0x384095a2,
0x785ec5bc, 0x389e15a9, 0x789dc703, 0x78c06474,
0xb89ff667, 0xfc57e51e, 0xbc4155f9, 0xfc05a6ee,
0xbc1df408, 0xf835da2a, 0xb836d9a4, 0x3833580d,
0x7826cb6c, 0xf8706900, 0xb87ae880, 0x3865db2e,
0x78714889, 0x38a7789b, 0x78beca2f, 0x78f6c810,
0xb8bef956, 0xfc6afabd, 0xbc734963, 0xfc3d5b8d,
0xbc25fbb7, 0xf9189d05, 0xb91ecb1d, 0x39187a33,
0x791f226d, 0xf95aa2f3, 0xb9587bb7, 0x395f7176,
0x795d9143, 0x399e7e08, 0x799a2697, 0x79df3422,
0xb99c2624, 0xfd5c2374, 0xbd5fa1d9, 0xfd1d595a,
0xbd1b1869, 0x580040db, 0x1800000b, 0xf8945060,
0xd8000000, 0xf8ae6ba0, 0xf99a0080, 0x1a070035,
0x3a0700a8, 0x5a0e0367, 0x7a11009b, 0x9a000380,
0xba1e030c, 0xda0f0320, 0xfa030301, 0x0b340b11,
0x2b2a278d, 0xcb22aa0f, 0x6b2d29bd, 0x8b2cce8c,
0xab2b877e, 0xcb21c8ee, 0xeb3ba47d, 0x3a4d400e,
0x7a5132c6, 0xba5e622e, 0xfa53814c, 0x3a52d8c2,
0x7a4d8924, 0xba4b3aab, 0xfa4d7882, 0x1a96804c,