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ef10.c
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ef10.c
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/***************************************************************************
* Driver for Solarflare network controllers and boards
* Copyright 2012-2017 Solarflare Communications Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation, incorporated herein by reference.
*/
#include "net_driver.h"
#include "ef10_regs.h"
#include "io.h"
#include "mcdi.h"
#include "mcdi_pcol.h"
#include "mcdi_port_common.h"
#include "nic.h"
#include "mcdi_filters.h"
#include "mcdi_functions.h"
#include "efx_common.h"
#include "efx_channels.h"
#include "rx_common.h"
#include "tx_common.h"
#include "workarounds.h"
#include "selftest.h"
#include "sriov.h"
#include "aoe.h"
#include "ef10_sriov.h"
#include <linux/in.h>
#include <linux/jhash.h>
#include <linux/wait.h>
#include <linux/workqueue.h>
#ifdef EFX_NOT_UPSTREAM
#include "efx_ioctl.h"
#endif
#include <linux/module.h>
#include "debugfs.h"
#include "emcdi.h"
#include "emcdicaps.h"
#include "fpgacaps.h"
#if defined(EFX_USE_KCOMPAT) && !defined(EFX_HAVE_HW_ENC_FEATURES)
#undef EFX_USE_OVERLAY_TX_CSUM
#endif
static unsigned int tx_push_max_fill = 0xffffffff;
module_param(tx_push_max_fill, uint, 0444);
MODULE_PARM_DESC(tx_push_max_fill,
"[SFC9100-family] Only use Tx push when the queue is below "
"this fill level; 0=>never push 1=>push when empty; "
"default always to push");
static bool tx_coalesce_doorbell = false;
module_param(tx_coalesce_doorbell, bool, 0444);
MODULE_PARM_DESC(tx_coalesce_doorbell,
"[SFC9100-family] Coalesce notification to NIC of pending TX"
"data when set this option sets tx_push_max_fill=0:"
":default=N");
static bool multicast_chaining = true;
module_param(multicast_chaining, bool, 0444);
MODULE_PARM_DESC(multicast_chaining,
"[SFC9100-family] Enabled multicast filter chaining in "
"firmware; default=Y");
#ifdef EFX_NOT_UPSTREAM
static bool monitor_hw_available = false;
module_param(monitor_hw_available, bool, 0644);
MODULE_PARM_DESC(monitor_hw_available,
"[SFC9100-family] Check hardware availability during periodic "
"monitor; default=N");
#endif
#ifdef EFX_NOT_UPSTREAM
static bool tx_non_csum_queue = false;
module_param(tx_non_csum_queue, bool, 0644);
MODULE_PARM_DESC(tx_non_csum_queue,
"[SFC9100-family] Allocate dedicated TX queues for traffic "
"not requiring checksum offload; default=N");
#endif
#ifdef EFX_NOT_UPSTREAM
/* A fixed key for RSS that has been tested and found to provide good
* spreading behaviour. It also has the desirable property of being
* symmetric.
*/
static const u8 efx_rss_fixed_key[40] = {
0x6d, 0x5a, 0x6d, 0x5a, 0x6d, 0x5a, 0x6d, 0x5a,
0x6d, 0x5a, 0x6d, 0x5a, 0x6d, 0x5a, 0x6d, 0x5a,
0x6d, 0x5a, 0x6d, 0x5a, 0x6d, 0x5a, 0x6d, 0x5a,
0x6d, 0x5a, 0x6d, 0x5a, 0x6d, 0x5a, 0x6d, 0x5a,
0x6d, 0x5a, 0x6d, 0x5a, 0x6d, 0x5a, 0x6d, 0x5a,
};
static bool efx_rss_use_fixed_key = true;
module_param_named(rss_use_fixed_key, efx_rss_use_fixed_key, bool, 0444);
MODULE_PARM_DESC(rss_use_fixed_key, "Use a fixed RSS hash key, "
"tested for reliable spreading across channels");
#endif
/* Hardware control for EF10 architecture including 'Huntington'. */
#define EFX_EF10_DRVGEN_EV 7
enum {
EFX_EF10_TEST = 1,
EFX_EF10_REFILL,
#ifdef EFX_NOT_UPSTREAM
EFX_EF10_RERING_RX_DOORBELL,
#endif
};
#ifdef EFX_NOT_UPSTREAM
#define EF10_ONLOAD_PF_VIS 240
#define EF10_ONLOAD_VF_VIS 0
#endif
#define MCDI_BUF_LEN (8 + MCDI_CTL_SDU_LEN_MAX)
static bool efx_ef10_hw_unavailable(struct efx_nic *efx);
static void _efx_ef10_rx_write(struct efx_rx_queue *rx_queue);
static int efx_ef10_set_udp_tnl_ports(struct efx_nic *efx, bool unloading)
__releases(nic_data->udp_tunnels_lock);
#ifdef CONFIG_SFC_SRIOV
static void efx_ef10_vf_update_stats_work(struct work_struct *data);
#endif
#ifdef EFX_NOT_UPSTREAM
static struct efx_tx_queue *
efx_ef10_select_tx_queue_non_csum(struct efx_channel *channel,
struct sk_buff *skb);
#endif
static struct efx_tx_queue *
efx_ef10_select_tx_queue(struct efx_channel *channel, struct sk_buff *skb);
#ifdef EFX_USE_OVERLAY_TX_CSUM
#ifdef EFX_NOT_UPSTREAM
static struct efx_tx_queue *
efx_ef10_select_tx_queue_non_csum_overlay(struct efx_channel *channel,
struct sk_buff *skb);
#endif
static struct efx_tx_queue *
efx_ef10_select_tx_queue_overlay(struct efx_channel *channel,
struct sk_buff *skb);
#endif /* EFX_USE_OVERLAY_TX_CSUM */
static bool efx_u25_check_cap(struct efx_ef10_nic_data *nic_data)
{
struct efx_nic *efx = nic_data->efx;
struct fpgacaps fpga;
bool u25 = false;
char version[5];
int rc = 1;
/* Checks for the eMCDI capability in the device. */
rc = check_emcdi_cap(efx);
if (rc) {
netif_err(efx, hw, efx->net_dev, "eMCDI capabilities are absent\n");
u25 = false;
} else {
netif_info(efx, drv, efx->net_dev, "Device has eMCDI capabilities\n");
netif_info(efx, drv, efx->net_dev, "Device is U25\n");
u25 = true;
}
/* If eMCDI is present, we check for FPGA version and external MAC and MAE
* support by the FPGA design. Also checking which flash the FPGA is
* currently booting from.
*/
if (u25) {
rc = get_fpga_caps(efx, &fpga);
if (rc != 0)
netif_err(efx, drv, efx->net_dev, "Error in obtaining FPGA capabilities\n");
else {
netif_info(efx, drv, efx->net_dev, "FPGA design %s MACs for network ports\n",
fpga.mac ? "supports" : "does not support");
netif_info(efx, drv, efx->net_dev, "FPGA design %s external MAE\n",
fpga.mae ? "supports" : "does not support");
}
memset(version, 0, sizeof(version));
rc = get_fpga_vers(efx, version);
if (rc != 0)
netif_err(efx, drv, efx->net_dev, "Error in obtaining FPGA version\n");
else {
netif_info(efx, drv, efx->net_dev, "FPGA Version: 0x%.2x%.2x%.2x%.2x\n",
version[3],
version[2],
version[1],
version[0]);
}
if (get_fpga_nvram(efx, &fpga) != 0) {
netif_err(efx, drv, efx->net_dev, "Unable to get FPGA flash information\n");
} else
netif_info(efx, drv, efx->net_dev, "FPGA is booting from %s flash\n",
fpga.nvram_id ? "secondary" : "primary");
}
return u25;
}
static u8 *efx_ef10_mcdi_buf(struct efx_nic *efx, u8 bufid,
dma_addr_t *dma_addr)
{
struct efx_ef10_nic_data *nic_data = efx->nic_data;
if (dma_addr)
*dma_addr = nic_data->mcdi_buf.dma_addr +
bufid * ALIGN(MCDI_BUF_LEN, 256);
return nic_data->mcdi_buf.addr + bufid * ALIGN(MCDI_BUF_LEN, 256);
}
static int efx_ef10_get_warm_boot_count(struct efx_nic *efx)
{
efx_dword_t reg;
efx_readd(efx, ®, ER_DZ_BIU_MC_SFT_STATUS);
if (EFX_DWORD_FIELD(reg, EFX_DWORD_0) == 0xffffffff) {
netif_err(efx, hw, efx->net_dev, "Hardware unavailable\n");
efx->state = STATE_DISABLED;
return -ENETDOWN;
} else {
return EFX_DWORD_FIELD(reg, EFX_WORD_1) == 0xb007 ?
EFX_DWORD_FIELD(reg, EFX_WORD_0) : -EIO;
}
}
/* On all EF10s up to and including SFC9220 (Medford1), all PFs use BAR 0 for
* I/O space and BAR 2(&3) for memory. On SFC9250 (Medford2), there is no I/O
* bar; PFs use BAR 0/1 for memory.
*/
static unsigned int efx_ef10_pf_mem_bar(struct efx_nic *efx)
{
switch (efx->pci_dev->device) {
case 0x0b03: /* SFC9250 PF */
return 0;
default:
return 2;
}
}
#if defined(CONFIG_SFC_SRIOV)
/* All VFs use BAR 0/1 for memory */
static unsigned int efx_ef10_vf_mem_bar(struct efx_nic *efx)
{
return 0;
}
#endif
static unsigned int efx_ef10_initial_mem_map_size(struct efx_nic *efx)
{
/* For the initial memory mapping, map only one (minimum-size) VI's-
* worth. This is enough to get the VI-independent registers.
*/
#ifdef EFX_NOT_UPSTREAM
/* ...but is not so much as to interfere with pre-existing mappings of
* portions of the BAR held by Onload.
*/
#endif
return EFX_DEFAULT_VI_STRIDE;
}
#if defined(EFX_NOT_UPSTREAM) && defined(CONFIG_SFC_AOE)
static inline bool aoe_enabled(struct efx_ef10_nic_data *nic)
{
return (nic->caps & (1 << MC_CMD_CAPABILITIES_AOE_LBN));
}
#endif
static unsigned int efx_ef10_bar_size(struct efx_nic *efx)
{
int bar;
bar = efx->type->mem_bar(efx);
return resource_size(&efx->pci_dev->resource[bar]);
}
static bool efx_ef10_is_vf(struct efx_nic *efx)
{
return efx->type->is_vf;
}
static int efx_ef10_init_datapath_caps(struct efx_nic *efx)
{
MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_CAPABILITIES_V4_OUT_LEN);
struct efx_ef10_nic_data *nic_data = efx->nic_data;
size_t outlen;
int rc;
BUILD_BUG_ON(MC_CMD_GET_CAPABILITIES_IN_LEN != 0);
rc = efx_mcdi_rpc(efx, MC_CMD_GET_CAPABILITIES, NULL, 0,
outbuf, sizeof(outbuf), &outlen);
if (rc)
return rc;
if (outlen < MC_CMD_GET_CAPABILITIES_OUT_LEN) {
netif_err(efx, drv, efx->net_dev,
"unable to read datapath firmware capabilities\n");
return -EIO;
}
nic_data->datapath_caps =
MCDI_DWORD(outbuf, GET_CAPABILITIES_OUT_FLAGS1);
if (outlen >= MC_CMD_GET_CAPABILITIES_V2_OUT_LEN) {
nic_data->datapath_caps2 = MCDI_DWORD(outbuf,
GET_CAPABILITIES_V2_OUT_FLAGS2);
nic_data->piobuf_size = MCDI_WORD(outbuf,
GET_CAPABILITIES_V2_OUT_SIZE_PIO_BUFF);
#ifdef EFX_NOT_UPSTREAM
/* Does the largest sw-possible PIO packet fit inside a hw
* PIO buffer?
*/
EFX_WARN_ON_PARANOID(nic_data->piobuf_size < ER_DZ_TX_PIOBUF_SIZE);
#endif
} else {
nic_data->datapath_caps2 = 0;
nic_data->piobuf_size = ER_DZ_TX_PIOBUF_SIZE;
}
if (!efx_ef10_has_cap(nic_data->datapath_caps, RX_PREFIX_LEN_14)) {
netif_err(efx, probe, efx->net_dev,
"current firmware does not support an RX prefix\n");
return -ENODEV;
}
if (outlen >= MC_CMD_GET_CAPABILITIES_V3_OUT_LEN) {
u8 vi_window_mode = MCDI_BYTE(outbuf,
GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE);
rc = efx_mcdi_window_mode_to_stride(efx, vi_window_mode);
if (rc)
return rc;
} else {
/* keep default VI stride */
netif_dbg(efx, probe, efx->net_dev,
"firmware did not report VI window mode, assuming vi_stride = %u\n",
efx->vi_stride);
}
if (outlen >= MC_CMD_GET_CAPABILITIES_V4_OUT_LEN) {
efx->num_mac_stats = MCDI_WORD(outbuf,
GET_CAPABILITIES_V4_OUT_MAC_STATS_NUM_STATS);
netif_dbg(efx, probe, efx->net_dev,
"firmware reports num_mac_stats = %u\n",
efx->num_mac_stats);
} else {
/* leave num_mac_stats as the default value, MC_CMD_MAC_NSTATS */
netif_dbg(efx, probe, efx->net_dev,
"firmware did not report num_mac_stats, assuming %u\n",
efx->num_mac_stats);
}
return 0;
}
static void efx_ef10_read_licensed_features(struct efx_nic *efx)
{
MCDI_DECLARE_BUF(inbuf, MC_CMD_LICENSING_V3_IN_LEN);
MCDI_DECLARE_BUF(outbuf, MC_CMD_LICENSING_V3_OUT_LEN);
struct efx_ef10_nic_data *nic_data = efx->nic_data;
size_t outlen;
int rc, try;
MCDI_SET_DWORD(inbuf, LICENSING_V3_IN_OP,
MC_CMD_LICENSING_V3_IN_OP_REPORT_LICENSE);
for (try=0; try < 15; try++) {
rc = efx_mcdi_rpc_quiet(efx, MC_CMD_LICENSING_V3, inbuf,
sizeof(inbuf), outbuf, sizeof(outbuf),
&outlen);
if (rc != -EAGAIN)
break;
/* It takes a long time to verify the license on an 8xxx
* series.
*/
msleep(200);
}
if (!rc && (outlen >= MC_CMD_LICENSING_V3_OUT_LEN)) {
nic_data->licensed_features = MCDI_QWORD(outbuf,
LICENSING_V3_OUT_LICENSED_FEATURES);
return;
}
if (rc != -MC_CMD_ERR_ENOSYS)
efx_mcdi_display_error(efx, MC_CMD_LICENSING_V3,
MC_CMD_LICENSING_V3_IN_LEN, outbuf,
outlen, rc);
/* LICENSING_V3 will fail on older firmwares, so fall back to
* LICENSED_APP_STATE.
*/
BUILD_BUG_ON(MC_CMD_GET_LICENSED_APP_STATE_IN_LEN >
MC_CMD_LICENSING_V3_IN_LEN);
BUILD_BUG_ON(MC_CMD_GET_LICENSED_APP_STATE_OUT_LEN >
MC_CMD_LICENSING_V3_OUT_LEN);
MCDI_SET_DWORD(inbuf, GET_LICENSED_APP_STATE_IN_APP_ID,
LICENSED_APP_ID_PTP);
rc = efx_mcdi_rpc(efx, MC_CMD_GET_LICENSED_APP_STATE, inbuf,
MC_CMD_GET_LICENSED_APP_STATE_IN_LEN,
outbuf, MC_CMD_GET_LICENSED_APP_STATE_OUT_LEN,
&outlen);
if (rc || (outlen < MC_CMD_GET_LICENSED_APP_STATE_OUT_LEN))
return;
if (MCDI_QWORD(outbuf, GET_LICENSED_APP_STATE_OUT_STATE) ==
MC_CMD_GET_LICENSED_APP_STATE_OUT_LICENSED)
nic_data->licensed_features |=
(1 << LICENSED_V3_FEATURES_TX_TIMESTAMPS_LBN);
}
static int efx_ef10_get_sysclk_freq(struct efx_nic *efx)
{
MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_CLOCK_OUT_LEN);
int rc;
rc = efx_mcdi_rpc(efx, MC_CMD_GET_CLOCK, NULL, 0,
outbuf, sizeof(outbuf), NULL);
if (rc)
return rc;
rc = MCDI_DWORD(outbuf, GET_CLOCK_OUT_SYS_FREQ);
return rc > 0 ? rc : -ERANGE;
}
static int efx_ef10_get_timer_workarounds(struct efx_nic *efx)
{
struct efx_ef10_nic_data *nic_data = efx->nic_data;
unsigned int implemented;
unsigned int enabled;
int rc;
nic_data->workaround_35388 = false;
nic_data->workaround_61265 = false;
rc = efx_mcdi_get_workarounds(efx, &implemented, &enabled);
if (rc == -ENOSYS) {
/* Firmware without GET_WORKAROUNDS - not a problem. */
rc = 0;
} else if (rc == 0) {
/* Bug61265 workaround is always enabled if implemented. */
if (enabled & MC_CMD_GET_WORKAROUNDS_OUT_BUG61265)
nic_data->workaround_61265 = true;
if (enabled & MC_CMD_GET_WORKAROUNDS_OUT_BUG35388) {
nic_data->workaround_35388 = true;
} else if (implemented & MC_CMD_GET_WORKAROUNDS_OUT_BUG35388) {
/* Workaround is implemented but not enabled.
* Try to enable it.
*/
rc = efx_mcdi_set_workaround(efx,
MC_CMD_WORKAROUND_BUG35388,
true, NULL);
if (rc == 0)
nic_data->workaround_35388 = true;
/* If we failed to set the workaround just carry on. */
rc = 0;
}
}
netif_dbg(efx, probe, efx->net_dev,
"workaround for bug 35388 is %sabled\n",
nic_data->workaround_35388 ? "en" : "dis");
netif_dbg(efx, probe, efx->net_dev,
"workaround for bug 61265 is %sabled\n",
nic_data->workaround_61265 ? "en" : "dis");
return rc;
}
static void efx_ef10_process_timer_config(struct efx_nic *efx,
const efx_dword_t *data)
{
unsigned int max_count;
if (EFX_EF10_WORKAROUND_61265(efx)) {
efx->timer_quantum_ns = MCDI_DWORD(data,
GET_EVQ_TMR_PROPERTIES_OUT_MCDI_TMR_STEP_NS);
efx->timer_max_ns = MCDI_DWORD(data,
GET_EVQ_TMR_PROPERTIES_OUT_MCDI_TMR_MAX_NS);
} else if (EFX_EF10_WORKAROUND_35388(efx)) {
efx->timer_quantum_ns = MCDI_DWORD(data,
GET_EVQ_TMR_PROPERTIES_OUT_BUG35388_TMR_NS_PER_COUNT);
max_count = MCDI_DWORD(data,
GET_EVQ_TMR_PROPERTIES_OUT_BUG35388_TMR_MAX_COUNT);
efx->timer_max_ns = max_count * efx->timer_quantum_ns;
} else {
efx->timer_quantum_ns = MCDI_DWORD(data,
GET_EVQ_TMR_PROPERTIES_OUT_TMR_REG_NS_PER_COUNT);
max_count = MCDI_DWORD(data,
GET_EVQ_TMR_PROPERTIES_OUT_TMR_REG_MAX_COUNT);
efx->timer_max_ns = max_count * efx->timer_quantum_ns;
}
netif_dbg(efx, probe, efx->net_dev,
"got timer properties from MC: quantum %u ns; max %u ns\n",
efx->timer_quantum_ns, efx->timer_max_ns);
}
static int efx_ef10_get_timer_config(struct efx_nic *efx)
{
MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_LEN);
int rc;
rc = efx_ef10_get_timer_workarounds(efx);
if (rc)
return rc;
rc = efx_mcdi_rpc_quiet(efx, MC_CMD_GET_EVQ_TMR_PROPERTIES, NULL, 0,
outbuf, sizeof(outbuf), NULL);
if (rc == 0) {
efx_ef10_process_timer_config(efx, outbuf);
} else if (rc == -ENOSYS || rc == -EPERM) {
/* Not available - fall back to Huntington defaults. */
unsigned int quantum;
rc = efx_ef10_get_sysclk_freq(efx);
if (rc < 0)
return rc;
quantum = 1536000 / rc; /* 1536 cycles */
efx->timer_quantum_ns = quantum;
efx->timer_max_ns = efx->type->timer_period_max * quantum;
rc = 0;
} else {
efx_mcdi_display_error(efx, MC_CMD_GET_EVQ_TMR_PROPERTIES,
MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_LEN,
NULL, 0, rc);
}
return rc;
}
static int efx_ef10_get_mac_address_pf(struct efx_nic *efx, u8 *mac_address)
{
MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_MAC_ADDRESSES_OUT_LEN);
size_t outlen;
int rc;
BUILD_BUG_ON(MC_CMD_GET_MAC_ADDRESSES_IN_LEN != 0);
rc = efx_mcdi_rpc(efx, MC_CMD_GET_MAC_ADDRESSES, NULL, 0,
outbuf, sizeof(outbuf), &outlen);
#ifdef EFX_NOT_UPSTREAM
/* XXX remove fallback in 2013-10
* efx_mcdi_get_board_cfg() should also be made static in siena.c then
*/
if (rc == -ENOSYS && efx_port_num(efx) < 2) {
netif_warn(efx, probe, efx->net_dev,
"current firmware does not support GET_MAC_ADDRESSES; falling back to GET_BOARD_CFG\n");
return efx_mcdi_get_board_cfg(efx, efx_port_num(efx),
mac_address, NULL, NULL);
}
#endif
if (rc)
return rc;
if (outlen < MC_CMD_GET_MAC_ADDRESSES_OUT_LEN)
return -EIO;
ether_addr_copy(mac_address,
MCDI_PTR(outbuf, GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE));
#ifdef EFX_NOT_UPSTREAM
if (mac_address[0] & 2)
netif_warn(efx, probe, efx->net_dev,
"static config does not include a global MAC address pool; using local address\n");
#endif
return 0;
}
#if defined(CONFIG_SFC_SRIOV)
static int efx_ef10_get_mac_address_vf(struct efx_nic *efx, u8 *mac_address)
{
MCDI_DECLARE_BUF(inbuf, MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_LEN);
MCDI_DECLARE_BUF(outbuf, MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMAX);
size_t outlen;
int num_addrs, rc;
MCDI_SET_DWORD(inbuf, VPORT_GET_MAC_ADDRESSES_IN_VPORT_ID,
EVB_PORT_ID_ASSIGNED);
rc = efx_mcdi_rpc(efx, MC_CMD_VPORT_GET_MAC_ADDRESSES, inbuf,
sizeof(inbuf), outbuf, sizeof(outbuf), &outlen);
if (rc)
return rc;
if (outlen < MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMIN)
return -EIO;
num_addrs = MCDI_DWORD(outbuf,
VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_COUNT);
WARN_ON(num_addrs != 1);
ether_addr_copy(mac_address,
MCDI_PTR(outbuf, VPORT_GET_MAC_ADDRESSES_OUT_MACADDR));
return 0;
}
#endif
#ifdef CONFIG_SFC_SRIOV
static int efx_vf_parent(struct efx_nic *efx, struct efx_nic **efx_pf)
{
#if !defined(EFX_USE_KCOMPAT) || defined(EFX_HAVE_PHYSFN)
struct pci_dev *pci_dev_pf = pci_physfn(efx->pci_dev);
#endif
int rc = 0;
/* By default succeed without a parent PF */
*efx_pf = NULL;
#if !defined(EFX_USE_KCOMPAT) || defined(EFX_HAVE_PHYSFN)
/* Suceed if this is a PF already, or if there is noparent PF.
* Fail if the parent is not an sfc device.
*/
if (!pci_dev_pf || (efx->pci_dev == pci_dev_pf))
rc = 0;
else if (!pci_dev_pf->dev.driver ||
(pci_dev_pf->dev.driver->owner != THIS_MODULE))
rc = -EBUSY;
else
*efx_pf = pci_get_drvdata(pci_dev_pf);
#endif
return rc;
}
#endif
int efx_ef10_vswitch_alloc(struct efx_nic *efx, unsigned int port_id,
unsigned int vswitch_type)
{
MCDI_DECLARE_BUF(inbuf, MC_CMD_VSWITCH_ALLOC_IN_LEN);
int rc;
MCDI_SET_DWORD(inbuf, VSWITCH_ALLOC_IN_UPSTREAM_PORT_ID, port_id);
MCDI_SET_DWORD(inbuf, VSWITCH_ALLOC_IN_TYPE, vswitch_type);
MCDI_SET_DWORD(inbuf, VSWITCH_ALLOC_IN_NUM_VLAN_TAGS, 2);
MCDI_POPULATE_DWORD_1(inbuf, VSWITCH_ALLOC_IN_FLAGS,
VSWITCH_ALLOC_IN_FLAG_AUTO_PORT, 0);
/* Quietly try to allocate 2 VLAN tags */
rc = efx_mcdi_rpc_quiet(efx, MC_CMD_VSWITCH_ALLOC, inbuf, sizeof(inbuf),
NULL, 0, NULL);
/* If 2 VLAN tags is too many, revert to trying with 1 VLAN tags */
if (rc == -EPROTO) {
MCDI_SET_DWORD(inbuf, VSWITCH_ALLOC_IN_NUM_VLAN_TAGS, 1);
rc = efx_mcdi_rpc(efx, MC_CMD_VSWITCH_ALLOC, inbuf,
sizeof(inbuf), NULL, 0, NULL);
} else if (rc) {
efx_mcdi_display_error(efx, MC_CMD_VSWITCH_ALLOC,
MC_CMD_VSWITCH_ALLOC_IN_LEN, NULL, 0,
rc);
}
return rc;
}
int efx_ef10_vswitch_free(struct efx_nic *efx, unsigned int port_id)
{
MCDI_DECLARE_BUF(inbuf, MC_CMD_VSWITCH_FREE_IN_LEN);
MCDI_SET_DWORD(inbuf, VSWITCH_FREE_IN_UPSTREAM_PORT_ID, port_id);
return efx_mcdi_rpc(efx, MC_CMD_VSWITCH_FREE, inbuf, sizeof(inbuf),
NULL, 0, NULL);
}
int efx_ef10_vport_alloc(struct efx_nic *efx, u16 vlan, bool vlan_restrict,
unsigned int *port_id_out)
{
MCDI_DECLARE_BUF(inbuf, MC_CMD_VPORT_ALLOC_IN_LEN);
MCDI_DECLARE_BUF(outbuf, MC_CMD_VPORT_ALLOC_OUT_LEN);
size_t outlen;
int rc;
EFX_WARN_ON_PARANOID(!port_id_out);
/* we only ever want a single level of vports, so parent is ASSIGNED */
MCDI_SET_DWORD(inbuf, VPORT_ALLOC_IN_UPSTREAM_PORT_ID,
EVB_PORT_ID_ASSIGNED);
/* we also only ever want NORMAL type, the others are obsolete */
MCDI_SET_DWORD(inbuf, VPORT_ALLOC_IN_TYPE,
MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_NORMAL);
MCDI_SET_DWORD(inbuf, VPORT_ALLOC_IN_NUM_VLAN_TAGS,
(vlan != EFX_FILTER_VID_UNSPEC));
MCDI_POPULATE_DWORD_2(inbuf, VPORT_ALLOC_IN_FLAGS,
VPORT_ALLOC_IN_FLAG_AUTO_PORT, 0,
VPORT_ALLOC_IN_FLAG_VLAN_RESTRICT, vlan_restrict);
if (vlan != EFX_FILTER_VID_UNSPEC)
MCDI_POPULATE_DWORD_1(inbuf, VPORT_ALLOC_IN_VLAN_TAGS,
VPORT_ALLOC_IN_VLAN_TAG_0, vlan);
rc = efx_mcdi_rpc(efx, MC_CMD_VPORT_ALLOC, inbuf, sizeof(inbuf),
outbuf, sizeof(outbuf), &outlen);
if (rc)
return rc;
if (outlen < MC_CMD_VPORT_ALLOC_OUT_LEN)
return -EIO;
*port_id_out = MCDI_DWORD(outbuf, VPORT_ALLOC_OUT_VPORT_ID);
return 0;
}
int efx_ef10_vport_free(struct efx_nic *efx, unsigned int port_id)
{
MCDI_DECLARE_BUF(inbuf, MC_CMD_VPORT_FREE_IN_LEN);
MCDI_SET_DWORD(inbuf, VPORT_FREE_IN_VPORT_ID, port_id);
return efx_mcdi_rpc(efx, MC_CMD_VPORT_FREE, inbuf, sizeof(inbuf),
NULL, 0, NULL);
}
int efx_ef10_vadaptor_query(struct efx_nic *efx, unsigned int port_id,
u32 *port_flags, u32 *vadaptor_flags,
unsigned int *vlan_tags)
{
struct efx_ef10_nic_data *nic_data = efx->nic_data;
MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_QUERY_IN_LEN);
MCDI_DECLARE_BUF(outbuf, MC_CMD_VADAPTOR_QUERY_OUT_LEN);
size_t outlen;
int rc;
if (efx_ef10_has_cap(nic_data->datapath_caps, VADAPTOR_QUERY)) {
MCDI_SET_DWORD(inbuf, VADAPTOR_QUERY_IN_UPSTREAM_PORT_ID,
port_id);
rc = efx_mcdi_rpc(efx, MC_CMD_VADAPTOR_QUERY,
inbuf, sizeof(inbuf),
outbuf, sizeof(outbuf), &outlen);
if (rc)
return rc;
if (outlen < sizeof(outbuf)) {
rc = -EIO;
return rc;
}
}
if (port_flags)
*port_flags = MCDI_DWORD(outbuf, VADAPTOR_QUERY_OUT_PORT_FLAGS);
if (vadaptor_flags)
*vadaptor_flags =
MCDI_DWORD(outbuf, VADAPTOR_QUERY_OUT_VADAPTOR_FLAGS);
if (vlan_tags)
*vlan_tags =
MCDI_DWORD(outbuf,
VADAPTOR_QUERY_OUT_NUM_AVAILABLE_VLAN_TAGS);
return 0;
}
int efx_ef10_vadaptor_alloc(struct efx_nic *efx, unsigned int port_id)
{
MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_ALLOC_IN_LEN);
MCDI_SET_DWORD(inbuf, VADAPTOR_ALLOC_IN_UPSTREAM_PORT_ID, port_id);
MCDI_POPULATE_DWORD_1(inbuf, VADAPTOR_ALLOC_IN_FLAGS,
VADAPTOR_ALLOC_IN_FLAG_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED,
1);
return efx_mcdi_rpc(efx, MC_CMD_VADAPTOR_ALLOC, inbuf, sizeof(inbuf),
NULL, 0, NULL);
}
int efx_ef10_vadaptor_free(struct efx_nic *efx, unsigned int port_id)
{
MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_FREE_IN_LEN);
MCDI_SET_DWORD(inbuf, VADAPTOR_FREE_IN_UPSTREAM_PORT_ID, port_id);
return efx_mcdi_rpc(efx, MC_CMD_VADAPTOR_FREE, inbuf, sizeof(inbuf),
NULL, 0, NULL);
}
int efx_ef10_evb_port_assign(struct efx_nic *efx, unsigned int port_id,
unsigned int vf_fn)
{
MCDI_DECLARE_BUF(inbuf, MC_CMD_EVB_PORT_ASSIGN_IN_LEN);
struct efx_ef10_nic_data *nic_data = efx->nic_data;
MCDI_SET_DWORD(inbuf, EVB_PORT_ASSIGN_IN_PORT_ID, port_id);
MCDI_POPULATE_DWORD_2(inbuf, EVB_PORT_ASSIGN_IN_FUNCTION,
EVB_PORT_ASSIGN_IN_PF, nic_data->pf_index,
EVB_PORT_ASSIGN_IN_VF, vf_fn);
return efx_mcdi_rpc(efx, MC_CMD_EVB_PORT_ASSIGN, inbuf, sizeof(inbuf),
NULL, 0, NULL);
}
int efx_ef10_vport_add_mac(struct efx_nic *efx, unsigned int port_id, u8 *mac)
{
MCDI_DECLARE_BUF(inbuf, MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_LEN);
MCDI_SET_DWORD(inbuf, VPORT_ADD_MAC_ADDRESS_IN_VPORT_ID, port_id);
ether_addr_copy(MCDI_PTR(inbuf, VPORT_ADD_MAC_ADDRESS_IN_MACADDR), mac);
return efx_mcdi_rpc(efx, MC_CMD_VPORT_ADD_MAC_ADDRESS, inbuf,
sizeof(inbuf), NULL, 0, NULL);
}
int efx_ef10_vport_del_mac(struct efx_nic *efx, unsigned int port_id, u8 *mac)
{
MCDI_DECLARE_BUF(inbuf, MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_LEN);
MCDI_SET_DWORD(inbuf, VPORT_DEL_MAC_ADDRESS_IN_VPORT_ID, port_id);
ether_addr_copy(MCDI_PTR(inbuf, VPORT_DEL_MAC_ADDRESS_IN_MACADDR), mac);
return efx_mcdi_rpc(efx, MC_CMD_VPORT_DEL_MAC_ADDRESS, inbuf,
sizeof(inbuf), NULL, 0, NULL);
}
#ifdef EFX_USE_PIO
static void efx_ef10_free_piobufs(struct efx_nic *efx)
{
struct efx_ef10_nic_data *nic_data = efx->nic_data;
MCDI_DECLARE_BUF(inbuf, MC_CMD_FREE_PIOBUF_IN_LEN);
unsigned int i;
int rc;
BUILD_BUG_ON(MC_CMD_FREE_PIOBUF_OUT_LEN != 0);
for (i = 0; i < nic_data->n_piobufs; i++) {
MCDI_SET_DWORD(inbuf, FREE_PIOBUF_IN_PIOBUF_HANDLE,
nic_data->piobuf_handle[i]);
rc = efx_mcdi_rpc(efx, MC_CMD_FREE_PIOBUF, inbuf, sizeof(inbuf),
NULL, 0, NULL);
if (unlikely(rc && rc != -ENETDOWN &&
!efx_ef10_hw_unavailable(efx)))
netif_warn(efx, probe, efx->net_dev,
"Failed to free PIO buffers: %d\n", rc);
}
nic_data->n_piobufs = 0;
}
static int efx_ef10_alloc_piobufs(struct efx_nic *efx, unsigned int n)
{
struct efx_ef10_nic_data *nic_data = efx->nic_data;
MCDI_DECLARE_BUF(outbuf, MC_CMD_ALLOC_PIOBUF_OUT_LEN);
unsigned int i;
size_t outlen;
int rc = 0;
BUILD_BUG_ON(MC_CMD_ALLOC_PIOBUF_IN_LEN != 0);
for (i = 0; i < n; i++) {
rc = efx_mcdi_rpc_quiet(efx, MC_CMD_ALLOC_PIOBUF, NULL, 0,
outbuf, sizeof(outbuf), &outlen);
if (rc == -EPERM) {
netif_info(efx, probe, efx->net_dev, "no PIO support\n");
break;
} else if (rc) {
/* Don't display the MC error if we didn't have space
* for a VF.
*/
if (!(efx_ef10_is_vf(efx) && rc == -ENOSPC))
efx_mcdi_display_error(efx, MC_CMD_ALLOC_PIOBUF,
0, outbuf, outlen, rc);
break;
}
if (outlen < MC_CMD_ALLOC_PIOBUF_OUT_LEN) {
rc = -EIO;
break;
}
nic_data->piobuf_handle[i] =
MCDI_DWORD(outbuf, ALLOC_PIOBUF_OUT_PIOBUF_HANDLE);
netif_dbg(efx, probe, efx->net_dev,
"allocated PIO buffer %u handle %x\n", i,
nic_data->piobuf_handle[i]);
}
nic_data->n_piobufs = i;
if (rc)
efx_ef10_free_piobufs(efx);
return rc;
}
static int efx_ef10_link_piobufs(struct efx_nic *efx)
{
struct efx_ef10_nic_data *nic_data = efx->nic_data;
MCDI_DECLARE_BUF(inbuf, MC_CMD_LINK_PIOBUF_IN_LEN);
struct efx_channel *channel;
struct efx_tx_queue *tx_queue;
unsigned int offset, index;
int rc;
BUILD_BUG_ON(MC_CMD_LINK_PIOBUF_OUT_LEN != 0);
BUILD_BUG_ON(MC_CMD_UNLINK_PIOBUF_OUT_LEN != 0);
/* Link a buffer to each VI in the write-combining mapping */
for (index = 0; index < nic_data->n_piobufs; ++index) {
MCDI_SET_DWORD(inbuf, LINK_PIOBUF_IN_PIOBUF_HANDLE,
nic_data->piobuf_handle[index]);
MCDI_SET_DWORD(inbuf, LINK_PIOBUF_IN_TXQ_INSTANCE,
nic_data->pio_write_vi_base + index);
rc = efx_mcdi_rpc(efx, MC_CMD_LINK_PIOBUF,
inbuf, MC_CMD_LINK_PIOBUF_IN_LEN,
NULL, 0, NULL);
if (rc) {
netif_err(efx, drv, efx->net_dev,
"failed to link VI %u to PIO buffer %u (%d)\n",
nic_data->pio_write_vi_base + index, index,
rc);
goto fail;
}
netif_dbg(efx, probe, efx->net_dev,
"linked VI %u to PIO buffer %u\n",
nic_data->pio_write_vi_base + index, index);
}
/* Link a buffer to each TX queue */
efx_for_each_channel(channel, efx) {
if (!efx_channel_has_tx_queues(channel))
continue;
efx_for_each_channel_tx_queue(tx_queue, channel) {
/* We assign the PIO buffers to queues in
* reverse order to allow for the following
* special case.
*/
offset = ((efx->tx_channel_offset +
efx_tx_channels(efx) -
tx_queue->channel->channel - 1) *
efx_piobuf_size);
index = offset / nic_data->piobuf_size;
offset = offset % nic_data->piobuf_size;
/* When the host page size is 4K, the first
* host page in the WC mapping may be within
* the same VI page as the last TX queue. We
* can only link one buffer to each VI.
*/
if (tx_queue->queue == nic_data->pio_write_vi_base) {
BUG_ON(index != 0);
rc = 0;
} else {
MCDI_SET_DWORD(inbuf,
LINK_PIOBUF_IN_PIOBUF_HANDLE,
nic_data->piobuf_handle[index]);
MCDI_SET_DWORD(inbuf,
LINK_PIOBUF_IN_TXQ_INSTANCE,
tx_queue->queue);
rc = efx_mcdi_rpc(efx, MC_CMD_LINK_PIOBUF,
inbuf, MC_CMD_LINK_PIOBUF_IN_LEN,
NULL, 0, NULL);
}
if (rc) {
/* This is non-fatal; the TX path just
* won't use PIO for this queue
*/
netif_err(efx, drv, efx->net_dev,
"failed to link VI %u to PIO buffer %u (%d)\n",
tx_queue->queue, index, rc);
tx_queue->piobuf = NULL;
if (rc == -ENETDOWN)
goto fail;
} else {
tx_queue->piobuf =
nic_data->pio_write_base +
index * efx->vi_stride + offset;
tx_queue->piobuf_offset = offset;
netif_dbg(efx, probe, efx->net_dev,
"linked VI %u to PIO buffer %u offset %x addr %p\n",
tx_queue->queue, index,
tx_queue->piobuf_offset,
tx_queue->piobuf);
}
}
}
return 0;
fail:
/* inbuf was defined for MC_CMD_LINK_PIOBUF. We can use the same
* buffer for MC_CMD_UNLINK_PIOBUF because it's shorter.
*/
BUILD_BUG_ON(MC_CMD_LINK_PIOBUF_IN_LEN < MC_CMD_UNLINK_PIOBUF_IN_LEN);
while (index--) {
MCDI_SET_DWORD(inbuf, UNLINK_PIOBUF_IN_TXQ_INSTANCE,
nic_data->pio_write_vi_base + index);
efx_mcdi_rpc(efx, MC_CMD_UNLINK_PIOBUF,
inbuf, MC_CMD_UNLINK_PIOBUF_IN_LEN,
NULL, 0, NULL);
}
return rc;
}
static void efx_ef10_forget_old_piobufs(struct efx_nic *efx)
{
struct efx_channel *channel;
struct efx_tx_queue *tx_queue;
/* All our existing PIO buffers went away */
efx_for_each_channel(channel, efx)
efx_for_each_channel_tx_queue(tx_queue, channel)
tx_queue->piobuf = NULL;
}
#else /* !EFX_USE_PIO */
static int efx_ef10_alloc_piobufs(struct efx_nic *efx, unsigned int n)
{
return n == 0 ? 0 : -ENOBUFS;