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xnandps.c
1952 lines (1740 loc) · 51.4 KB
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xnandps.c
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/******************************************************************************
* Copyright (C) 2009 - 2021 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xnandps.c
* @addtogroup nandps_v2_7
* @{
*
* This file contains the implementation of the interface functions for
* XNandPs driver. Refer to the header file xnandps.h for more detailed
* information.
*
* This module supports for NAND flash memory devices that conform to the
* "Open NAND Flash Interface" (ONFI) Specification. This modules implements
* basic flash operations like read, write and erase.
*
* @note None
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- ---------- -----------------------------------------------
* 1.00a nm 12/10/2010 First release
* 1.01a nm 28/02/2012 Fixed 16-bit issue with ONFI commands like
* read, write and read status command. The config
* structure width is updated after ONFI query
* with the parameter page width.
* 1.02a nm 20/09/2012 Removed setting of set_cycles and set_opmode
* register values as it is now done in FSBL using
* the PCW generated files. CR#678949.
* 1.03a nm 10/22/2012 Fixed CR# 673348.
* 1.04a nm 04/15/2013 Fixed CR# 704401. Removed warnings when compiled
* with -Wall and -Wextra option in bsp.
* 04/25/2013 Implemented PR# 699544. Added page cache read
* and program support. Added API's XNandPs_ReadCache
* and XNandPs_WriteCache for page cache support.
* Added ECC handling functions XNandPs_EccSetCfg,
* XNandPs_EccSetMemCmd1...etc, to support better
* usage of ECC block for page cache commands.
* Modified Read/Write API's so that there is common
* code for normal read/write and page cache commands.
* Disabling/Re-enabling ECC block in read/write API's
* of spare bytes since we don't calculate ECC for
* spare bytes.
* 2.01 kpc 07/24/2014 Fixed CR#808770. Update command register twice only
* if flash device requires >= four address cycles.
* 2.2 sb 01/31/2015 Use the address cycles defined in onfi parameter
* page than hardcoding this value to 5 for read and
* write operations.
* </pre>
*
******************************************************************************/
/***************************** Include Files *********************************/
#include "xnandps.h"
#include "xnandps_bbm.h"
#include "xnandps_onfi.h"
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
static int XNandPs_EccHwInit(XNandPs *InstancePtr);
static int XNandPs_EccSwInit(XNandPs *InstancePtr);
static int XNandPs_ReadPage_HwEcc(XNandPs *InstancePtr, u8 *DstPtr);
static int XNandPs_ReadPage(XNandPs *InstancePtr, u8 *DstPtr);
static int XNandPs_WritePage_HwEcc(XNandPs *InstancePtr, u8 *SrcPtr);
static int XNandPs_WritePage(XNandPs *InstancePtr, u8 *SrcPtr);
static int XNandPs_EccCalculate(XNandPs *InstancePtr, u8 *EccData);
static int XNandPs_EccCorrect(u8 *Buf, u8 *EccCalc, u8 *EccCode);
static void XNandPs_ReadBuf(XNandPs *InstancePtr, u8 *Buf, u32 Length);
static void XNandPs_WriteBuf(XNandPs *InstancePtr, u8 *Buf, u32 Length);
static int XNandPs_IsBusy(XNandPs *InstancePtr);
void XNandPs_SendCommand(XNandPs *InstancePtr, XNandPs_CommandFormat
*Command, int Page, int Column);
static void XNandPs_EccSetCfg(XNandPs *InstancePtr, u32 EccConfig);
static void XNandPs_EccSetMemCmd1(XNandPs *InstancePtr, u32 EccCmd);
static void XNandPs_EccSetMemCmd2(XNandPs *InstancePtr, u32 EccCmd);
static void XNandPs_EccDisable(XNandPs *InstancePtr);
/* Bad block management routines */
extern void XNandPs_InitBbtDesc(XNandPs *InstancePtr);
extern int XNandPs_ScanBbt(XNandPs *InstancePtr);
/* ONFI routines */
extern u8 Onfi_CmdReadStatus(XNandPs *InstancePtr);
extern int Onfi_NandInit(XNandPs *InstancePtr);
/************************** Variable Definitions *****************************/
/* ECC data position in the spare data area for different page sizes */
u32 NandOob16[] = {13, 14, 15}; /**< Ecc position for 16 bytes spare area */
u32 NandOob32[] = {26, 27, 28, 29, 30, 31};
/**< Ecc position for 32 bytes spare area */
u32 NandOob64[] = {52, 53, 54, 55, 56, 57,
58, 59, 60, 61, 62, 63};
/**< Ecc position for 64 bytes spare area */
extern XNandPs_CommandFormat OnfiCommands[]; /**< ONFI commands */
/*****************************************************************************/
/**
*
* This function initializes a specific XNandPs device/instance. This function
* must be called prior to using the flash device to read or write any data.
*
* @param InstancePtr is a pointer to the XNandPs instance.
* @param ConfigPtr points to the XNandPs device configuration structure.
* @param SmcBaseAddr is the base address of SMC controller.
* @param FlashBaseAddr is the base address of NAND flash.
*
* @return
* - XST_SUCCESS if successful.
* - XST_FAILURE if fail.
*
* @note The user needs to first call the XNandPs_LookupConfig() API
* which returns the Configuration structure pointer which is
* passed as a parameter to the XNandPs_CfgInitialize() API.
*
******************************************************************************/
int XNandPs_CfgInitialize(XNandPs *InstancePtr, XNandPs_Config *ConfigPtr,
u32 SmcBaseAddr, u32 FlashBaseAddr)
{
u32 PageSize;
int Status;
/*
* Assert the input arguments.
*/
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(ConfigPtr != NULL);
/*
* Set the values read from the device config and the base address.
*/
InstancePtr->Config.DeviceId = ConfigPtr->DeviceId;
InstancePtr->Config.SmcBase = SmcBaseAddr;
InstancePtr->Config.FlashBase = FlashBaseAddr;
InstancePtr->Config.FlashWidth = ConfigPtr->FlashWidth;
XNandPs_WriteReg(InstancePtr->Config.SmcBase +
XNANDPS_MEMC_CLR_CONFIG_OFFSET,
XNANDPS_CLR_CONFIG); /* Disable interrupts */
/*
* ONFI query to get geometry
*/
Status = Onfi_NandInit(InstancePtr);
if (Status != XST_SUCCESS) {
return Status;
}
/*
* Updating Config structure flash width
*/
InstancePtr->Config.FlashWidth = InstancePtr->Geometry.FlashWidth;
/*
* Fill the spare buffer pointer
*/
PageSize = InstancePtr->Geometry.BytesPerPage;
InstancePtr->SpareBufPtr = &InstancePtr->DataBuf[PageSize];
/*
* Initialize ECC Block Parameters
*/
switch (InstancePtr->EccMode)
{
case XNANDPS_ECC_NONE:
/* Fall through */
case XNANDPS_ECC_ONDIE:
/* Bypass the ECC block in the SMC controller */
XNandPs_EccDisable(InstancePtr);
/* Initialize the Read/Write page routines */
InstancePtr->ReadPage = XNandPs_ReadPage;
InstancePtr->WritePage = XNandPs_WritePage;
break;
case XNANDPS_ECC_HW:
/* Use SMC ECC controller ECC block */
Status = XNandPs_EccHwInit(InstancePtr);
if (Status != XST_SUCCESS)
return Status;
/* Initialize ECC SW parameters */
Status = XNandPs_EccSwInit(InstancePtr);
if (Status != XST_SUCCESS)
return Status;
/* Initialize the Read/Write page routines */
InstancePtr->ReadPage = XNandPs_ReadPage_HwEcc;
InstancePtr->WritePage = XNandPs_WritePage_HwEcc;
break;
default:
return XST_FAILURE;
}
/*
* Indicate the instance is now ready to use, initialized without error.
*/
InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
/*
* Scan for the bad block table(bbt) stored in the flash & load it in
* memory(RAM). If bbt is not found, create bbt by scanning factory
* marked bad blocks and store it in last good blocks of flash.
*/
XNandPs_InitBbtDesc(InstancePtr);
Status = XNandPs_ScanBbt(InstancePtr);
if (Status != XST_SUCCESS) {
return Status;
}
return XST_SUCCESS;
}
/*****************************************************************************/
/**
*
* This function initializes the HW ECC block based on flash.
*
* @param InstancePtr is a pointer to the XNandPs instance.
* @param EccConfig is the value of ECC config to update.
*
* @return None
*
* @note None
*
*****************************************************************************/
static void XNandPs_EccSetCfg(XNandPs *InstancePtr, u32 EccConfig)
{
/*
* Check the busy status of the ECC block
*/
while (XNandPs_ReadReg(InstancePtr->Config.SmcBase +
XNANDPS_ECC_STATUS_OFFSET(XNANDPS_IF1_ECC_OFFSET)) &
XNANDPS_ECC_STATUS_MASK);
/*
* Write ECC configuration register
*/
XNandPs_WriteReg(InstancePtr->Config.SmcBase +
(XNANDPS_ECC_MEMCFG_OFFSET(XNANDPS_IF1_ECC_OFFSET)),
EccConfig);
}
/*****************************************************************************/
/**
*
* This function writes ECC MEM CMD1 register with EccCmd value.
*
* @param InstancePtr is a pointer to the XNandPs instance.
* @param EccCmd is register value to write.
*
* @return None
*
* @note None
*
*****************************************************************************/
static void XNandPs_EccSetMemCmd1(XNandPs *InstancePtr, u32 EccCmd)
{
/*
* Set the ECC mem command1 register
*/
XNandPs_WriteReg(InstancePtr->Config.SmcBase +
(XNANDPS_ECC_MEMCMD1_OFFSET(XNANDPS_IF1_ECC_OFFSET)),
EccCmd);
}
/*****************************************************************************/
/**
*
* This function writes ECC MEM CMD2 register with EccCmd value.
*
* @param InstancePtr is a pointer to the XNandPs instance.
* @param EccCmd is register value to write.
*
* @return None
*
* @note None
*
*****************************************************************************/
static void XNandPs_EccSetMemCmd2(XNandPs *InstancePtr, u32 EccCmd)
{
/*
* Set the ECC mem command2 register
*/
XNandPs_WriteReg(InstancePtr->Config.SmcBase +
(XNANDPS_ECC_MEMCMD2_OFFSET(XNANDPS_IF1_ECC_OFFSET)),
EccCmd);
}
/*****************************************************************************/
/**
*
* This function disables ECC block.
*
* @param InstancePtr is a pointer to the XNandPs instance.
*
* @return None
*
* @note None
*
*****************************************************************************/
static void XNandPs_EccDisable(XNandPs *InstancePtr)
{
u32 EccConfig = 0;
/*
* Bypass the ECC block in the SMC controller
*/
EccConfig = XNandPs_ReadReg(InstancePtr->Config.SmcBase +
(XNANDPS_ECC_MEMCFG_OFFSET(XNANDPS_IF1_ECC_OFFSET)));
EccConfig &= ~XNANDPS_ECC_MEMCFG_ECC_MODE_MASK;
XNandPs_EccSetCfg(InstancePtr, EccConfig);
}
/*****************************************************************************/
/**
*
* This function initializes the HW ECC block based on flash.
*
* @param InstancePtr is a pointer to the XNandPs instance.
*
* @return
* - XST_SUCCESS if successful.
* - XST_FAILURE if the flash is not supported.
*
* @note None
*
*****************************************************************************/
static int XNandPs_EccHwInit(XNandPs *InstancePtr)
{
u32 PageSize;
u32 EccConfig = 0;
PageSize = InstancePtr->Geometry.BytesPerPage;
/*
* Set the ECC mem command1 and ECC mem command2 register
*/
XNandPs_EccSetMemCmd1(InstancePtr, XNANDPS_ECC_CMD1);
XNandPs_EccSetMemCmd2(InstancePtr, XNANDPS_ECC_CMD2);
/*
* Configure HW ECC block
*/
switch(PageSize) {
case XNANDPS_PAGE_SIZE_512:
EccConfig = (XNANDPS_ECC_MEMCFG |
XNANDPS_ECC_MEMCFG_PAGE_SIZE_512);
break;
case XNANDPS_PAGE_SIZE_1024:
EccConfig = (XNANDPS_ECC_MEMCFG |
XNANDPS_ECC_MEMCFG_PAGE_SIZE_1024);
break;
case XNANDPS_PAGE_SIZE_2048:
EccConfig = (XNANDPS_ECC_MEMCFG |
XNANDPS_ECC_MEMCFG_PAGE_SIZE_2048);
break;
default:
/*
* Page size 256 bytes & 4096 bytes not supported
* by ECC block
*/
return XST_FAILURE;
}
XNandPs_EccSetCfg(InstancePtr, EccConfig);
return XST_SUCCESS;
}
/*****************************************************************************/
/**
*
* This function initializes the software variables related
* to ECC generation, ECC checking and writing ECC bytes in spare bytes.
*
* @param InstancePtr is a pointer to the XNandPs instance.
*
* @return
* - XST_SUCCESS if successful.
* - XST_FAILURE if the flash is not supported.
*
* @note None
*
*****************************************************************************/
static int XNandPs_EccSwInit(XNandPs *InstancePtr)
{
u32 PageSize;
u32 SpareBytesSize;
u32 Index;
PageSize = InstancePtr->Geometry.BytesPerPage;
SpareBytesSize = InstancePtr->Geometry.SpareBytesPerPage;
/*
* Initialize ECC config structure parameters
*/
InstancePtr->EccConfig.BytesPerBlock = XNANDPS_ECC_BYTES;
InstancePtr->EccConfig.BlockSize = XNANDPS_ECC_BLOCK_SIZE;
InstancePtr->EccConfig.TotalBytes = (PageSize/XNANDPS_ECC_BLOCK_SIZE)
* XNANDPS_ECC_BYTES;
InstancePtr->EccConfig.NumSteps = PageSize/XNANDPS_ECC_BLOCK_SIZE;
/*
* Ecc write position in spare data area as per Linux mtd subsystem
*/
switch(SpareBytesSize) {
case XNANDPS_SPARE_SIZE_16:
for(Index = 0; Index <
InstancePtr->EccConfig.TotalBytes;
Index++) {
InstancePtr->EccConfig.EccPos[Index] =
NandOob16[Index];
}
break;
case XNANDPS_SPARE_SIZE_32:
for(Index = 0; Index <
InstancePtr->EccConfig.TotalBytes;
Index++) {
InstancePtr->EccConfig.EccPos[Index] =
NandOob32[Index];
}
break;
case XNANDPS_SPARE_SIZE_64:
for(Index = 0; Index <
InstancePtr->EccConfig.TotalBytes;
Index++) {
InstancePtr->EccConfig.EccPos[Index] =
NandOob64[Index];
}
break;
default:
return XST_FAILURE;
}
return XST_SUCCESS;
}
/*****************************************************************************/
/**
*
* This function reads the data from the Flash device and copies it into the
* specified user buffer. It doesn't check for the bad blocks while reading
* the flash pages that cross block boundary. User must take care of handling
* bad blocks.
*
* @param InstancePtr is the pointer to the XNandPs instance.
* @param Offset is the flash data address to read from.
* @param Length is number of bytes to read.
* @param DestPtr is the destination address to copy data to.
* @param UserSparePtr is the user buffer to which spare data must be
* copied.
*
* @return
* - XST_SUCCESS if successful.
* - XST_FAILURE if fail.
*
* @note This function reads sequential pages from the Flash device.
*
******************************************************************************/
int XNandPs_Read(XNandPs *InstancePtr, u64 Offset, u32 Length, void *DestPtr,
u8 *UserSparePtr)
{
u32 Page;
u32 Col;
u32 PartialBytes;
u32 NumOfBytes;
int Status;
u32 PartialPageRead = 0;
u32 CopyOffset;
u8 *BufPtr;
u8 *Ptr = (u8 *)DestPtr;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(DestPtr != NULL);
Xil_AssertNonvoid((Offset + Length) < InstancePtr->Geometry.DeviceSize);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Xil_AssertNonvoid(Length != 0);
Page = (u32) (Offset/InstancePtr->Geometry.BytesPerPage);
Col = (u32) (Offset & (InstancePtr->Geometry.BytesPerPage - 1));
PartialBytes = InstancePtr->Geometry.BytesPerPage - Col;
NumOfBytes = (PartialBytes < Length) ? PartialBytes:Length;
CopyOffset = InstancePtr->Geometry.BytesPerPage - PartialBytes;
/*
* Restore the ECC mem command1 and ECC mem command2 register
* if the previous command is read page cache.
*/
XNandPs_EccSetMemCmd1(InstancePtr, XNANDPS_ECC_CMD1);
XNandPs_EccSetMemCmd2(InstancePtr, XNANDPS_ECC_CMD2);
while (Length) {
/*
* Check if partial read
*/
if (NumOfBytes < InstancePtr->Geometry.BytesPerPage) {
BufPtr = &InstancePtr->DataBuf[0];
PartialPageRead = 1;
} else {
BufPtr = (u8 *)Ptr;
PartialPageRead = 0;
}
/*
* Send the ONFI Read command
*/
XNandPs_SendCommand(InstancePtr, &OnfiCommands[READ], Page, 0);
/*
* Poll the Memory controller status register
*/
while (XNandPs_IsBusy(InstancePtr) == TRUE) {
}
/*
* Clear the interrupt condition
*/
XNandPs_WriteReg((InstancePtr->Config.SmcBase +
XNANDPS_MEMC_CLR_CONFIG_OFFSET),
XNANDPS_MEMC_CLR_CONFIG_INT_CLR1_MASK);
/*
* Read the page data
*/
Status = InstancePtr->ReadPage(InstancePtr, BufPtr);
if (Status != XST_SUCCESS) {
return Status;
}
/*
* Fill the partial data in the buffer
*/
if (PartialPageRead) {
memcpy(Ptr, BufPtr + CopyOffset, NumOfBytes);
}
Ptr += NumOfBytes;
Length -= NumOfBytes;
Page++;
NumOfBytes = (Length > InstancePtr->Geometry.BytesPerPage) ?
InstancePtr->Geometry.BytesPerPage:Length;
CopyOffset = 0;
}
/*
* Copy the spare data to user spare buffer
*/
if (UserSparePtr) {
memcpy(UserSparePtr, InstancePtr->SpareBufPtr,
InstancePtr->Geometry.SpareBytesPerPage);
}
return XST_SUCCESS;
}
/*****************************************************************************/
/**
*
* This function reads the data from the Flash device using read page cache
* command and copies it into the specified user buffer.
* It doesn't check for the bad blocks while reading the flash pages that
* cross block boundary. User must take care of handling bad blocks.
*
* @param InstancePtr is the pointer to the XNandPs instance.
* @param Offset is the flash data address to read from.
* @param Length is number of bytes to read.
* @param DestPtr is the destination address to copy data to.
* @param UserSparePtr is the user buffer to which spare data must be
* copied.
*
* @return
* - XST_SUCCESS if successful.
* - XST_FAILURE if fail.
*
* @note This function reads sequential pages from the Flash device.
*
******************************************************************************/
int XNandPs_ReadCache(XNandPs *InstancePtr, u64 Offset, u32 Length,
void *DestPtr, u8 *UserSparePtr)
{
u32 Page;
u32 Col;
u32 PartialBytes;
u32 NumOfBytes;
int Status;
u32 PartialPageRead = 0;
u32 CopyOffset;
u8 *BufPtr;
u8 *Ptr = (u8 *)DestPtr;
u32 NumPages;
u32 EccConfig = 0;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(DestPtr != NULL);
Xil_AssertNonvoid((Offset + Length) < InstancePtr->Geometry.DeviceSize);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Xil_AssertNonvoid(Length != 0);
/*
* Check if the flash supports read cache
*/
if (!InstancePtr->Features.ReadCache) {
return XNandPs_Read(InstancePtr, Offset, Length, DestPtr,
UserSparePtr);
}
Page = (u32) (Offset/InstancePtr->Geometry.BytesPerPage);
Col = (u32) (Offset & (InstancePtr->Geometry.BytesPerPage - 1));
PartialBytes = InstancePtr->Geometry.BytesPerPage - Col;
NumOfBytes = (PartialBytes < Length) ? PartialBytes:Length;
CopyOffset = InstancePtr->Geometry.BytesPerPage - PartialBytes;
/*
* Calculate number of pages to read
*/
NumPages = Length/InstancePtr->Geometry.BytesPerPage;
NumPages += (Length % InstancePtr->Geometry.BytesPerPage) ? 1:0;
/*
* Read, Read Cache start, Read Cache end
*/
if (NumPages <= 1) {
return XNandPs_Read(InstancePtr, Offset, Length, DestPtr,
UserSparePtr);
}
/*
* Change ECC commands in ECC registers for page cache support
*/
EccConfig |= ONFI_CMD_PAGE_CACHE_PROGRAM1;
EccConfig |= ONFI_CMD_READ_CACHE_ENHANCED1 << 8;
EccConfig |= ONFI_CMD_READ_CACHE_ENHANCED2 << 16;
EccConfig |= (XNANDPS_ECC_MEMCOMMAND1_RD_CMD_END_VALID_MASK);
XNandPs_EccSetMemCmd1(InstancePtr, EccConfig);
/*
* Send the ONFI Read command
*/
XNandPs_SendCommand(InstancePtr, &OnfiCommands[READ], Page, 0);
/*
* Poll the Memory controller status register
*/
while (XNandPs_IsBusy(InstancePtr) == TRUE) {
}
/*
* Clear the interrupt condition
*/
XNandPs_WriteReg((InstancePtr->Config.SmcBase +
XNANDPS_MEMC_CLR_CONFIG_OFFSET),
XNANDPS_MEMC_CLR_CONFIG_INT_CLR1_MASK);
/*
* Check ONFI Status Register
*/
Status = Onfi_CmdReadStatus(InstancePtr);
if (Status & ONFI_STATUS_FAIL) {
return XST_FAILURE;
}
while (Length && (NumPages > 0)) {
/*
* Check if partial read
*/
if (NumOfBytes < InstancePtr->Geometry.BytesPerPage) {
BufPtr = &InstancePtr->DataBuf[0];
PartialPageRead = 1;
} else {
BufPtr = (u8 *)Ptr;
PartialPageRead = 0;
}
/* Increment the page */
Page++;
if (NumPages <= 1) {
/*
* Change ECC commands in ECC registers to check
* change read column for ECC calculation
*/
EccConfig = 0;
EccConfig |= ONFI_CMD_PAGE_CACHE_PROGRAM1;
EccConfig |= ONFI_CMD_CHANGE_READ_COLUMN1 << 8;
EccConfig |= ONFI_CMD_CHANGE_READ_COLUMN2 << 16;
EccConfig |=
XNANDPS_ECC_MEMCOMMAND1_RD_CMD_END_VALID_MASK;
XNandPs_EccSetMemCmd1(InstancePtr, EccConfig);
/*
* Send NAND page cache end command 0x3F
*/
XNandPs_SendCommand(InstancePtr,
&OnfiCommands[READ_CACHE_END_SEQ],
XNANDPS_PAGE_NOT_VALID,
XNANDPS_COLUMN_NOT_VALID);
} else {
XNandPs_SendCommand(InstancePtr,
&OnfiCommands[READ_CACHE_RANDOM],
Page, 0);
}
/*
* Poll the Memory controller status register
*/
while (XNandPs_IsBusy(InstancePtr) == TRUE) {
}
/*
* Clear the interrupt condition
*/
XNandPs_WriteReg((InstancePtr->Config.SmcBase +
XNANDPS_MEMC_CLR_CONFIG_OFFSET),
XNANDPS_MEMC_CLR_CONFIG_INT_CLR1_MASK);
if (NumPages <= 1) {
XNandPs_SendCommand(InstancePtr,
&OnfiCommands[CHANGE_READ_COLUMN],
XNANDPS_PAGE_NOT_VALID,
0);
}
/*
* Read the page data
*/
Status = InstancePtr->ReadPage(InstancePtr, BufPtr);
if (Status != XST_SUCCESS) {
return Status;
}
/*
* Fill the partial data in the buffer
*/
if (PartialPageRead) {
memcpy(Ptr, BufPtr + CopyOffset, NumOfBytes);
}
Ptr += NumOfBytes;
Length -= NumOfBytes;
NumPages--;
NumOfBytes = (Length > InstancePtr->Geometry.BytesPerPage) ?
InstancePtr->Geometry.BytesPerPage:Length;
CopyOffset = 0;
}
/*
* Copy the spare data to user spare buffer
*/
if (UserSparePtr) {
memcpy(UserSparePtr, InstancePtr->SpareBufPtr,
InstancePtr->Geometry.SpareBytesPerPage);
}
return XST_SUCCESS;
}
/*****************************************************************************/
/**
*
* This function programs the flash device(s) with data specified in the user
* buffer. The source and destination address must be aligned to the width of the
* flash's data bus. It doesn't check for the bad blocks while writing to
* the flash pages that cross block boundary. User must take care of handling
* bad blocks.
*
* @param InstancePtr is the pointer to the XNandPs instance.
* @param Offset is the flash data address to write to.
* @param Length is number of bytes to write.
* @param SrcPtr is the source address to write the data from.
* @param UserSparePtr is the user buffer which contains buffer to write
* into spare data area.
*
* @return
* - XST_SUCCESS if successful.
* - XST_FAILURE if fail.
* - XST_NAND_WRITE_PROTECTED if the flash is write protected.
*
* @note This function writes number of sequential pages into the
* Flash device.
*
******************************************************************************/
int XNandPs_Write(XNandPs *InstancePtr, u64 Offset, u32 Length, void *SrcPtr,
u8 *UserSparePtr)
{
u32 Page;
u32 Col;
u32 PartialBytes;
u32 NumOfBytes;
u32 CopyOffset;
u32 Status;
u8 *BufPtr;
u8 OnfiStatus;
u8 *Ptr = (u8 *)SrcPtr;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(SrcPtr != NULL);
Xil_AssertNonvoid((Offset + Length) < InstancePtr->Geometry.DeviceSize);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Xil_AssertNonvoid(Length != 0);
/*
* Check if the flash is write protected
*/
OnfiStatus = Onfi_CmdReadStatus(InstancePtr);
if (!(OnfiStatus & ONFI_STATUS_WP)) {
return XST_NAND_WRITE_PROTECTED;
}
/*
* Copy the user spare data buffer
*/
if (UserSparePtr == NULL) {
memset(InstancePtr->SpareBufPtr, 0xff,
InstancePtr->Geometry.SpareBytesPerPage);
} else {
memcpy(InstancePtr->SpareBufPtr, UserSparePtr,
InstancePtr->Geometry.SpareBytesPerPage);
}
Page = (u32) (Offset/InstancePtr->Geometry.BytesPerPage);
Col = (u32) (Offset & (InstancePtr->Geometry.BytesPerPage - 1));
PartialBytes = InstancePtr->Geometry.BytesPerPage - Col;
NumOfBytes = (PartialBytes < Length) ? PartialBytes:Length;
CopyOffset = InstancePtr->Geometry.BytesPerPage - PartialBytes;
while (Length)
{
/*
* Partial write, fill the remaining buffer with 0xff
*/
if (NumOfBytes < InstancePtr->Geometry.BytesPerPage) {
BufPtr = &InstancePtr->DataBuf[0];
memset(BufPtr, 0xff,
InstancePtr->Geometry.BytesPerPage);
memcpy(BufPtr + CopyOffset, Ptr, NumOfBytes);
} else {
BufPtr = (u8 *)Ptr;
}
/*
* Send ONFI Program command
*/
XNandPs_SendCommand(InstancePtr, &OnfiCommands[PAGE_PROGRAM],
Page, 0);
/*
* Write the page data
*/
Status = InstancePtr->WritePage(InstancePtr, BufPtr);
if (Status != XST_SUCCESS) {
return Status;
}
Ptr += NumOfBytes;
Length -= NumOfBytes;
Page++;
NumOfBytes = (Length > InstancePtr->Geometry.BytesPerPage) ?
InstancePtr->Geometry.BytesPerPage:Length;
CopyOffset = 0;
}
return XST_SUCCESS;
}
/*****************************************************************************/
/**
*
* This function programs the flash device(s) with data specified in the user
* buffer using program cache command.
* The source and destination address must be aligned to the width of the
* flash's data bus. It doesn't check for the bad blocks while writing to
* the flash pages that cross block boundary. User must take care of handling
* bad blocks.
*
* @param InstancePtr is the pointer to the XNandPs instance.
* @param Offset is the flash data address to write to.
* @param Length is number of bytes to write.
* @param SrcPtr is the source address to write the data from.
* @param UserSparePtr is the user buffer which contains buffer to write
* into spare data area.
*
* @return
* - XST_SUCCESS if successful.
* - XST_FAILURE if fail.
* - XST_NAND_WRITE_PROTECTED if the flash is write protected.
*
* @note This function writes number of sequential pages into the
* Flash device.
*
******************************************************************************/
int XNandPs_WriteCache(XNandPs *InstancePtr, u64 Offset, u32 Length,
void *SrcPtr, u8 *UserSparePtr)
{
u32 Page;
u32 Col;
u32 PartialBytes;
u32 NumOfBytes;
u32 CopyOffset;
u32 Status;
u8 *BufPtr;
u8 OnfiStatus;
u8 *Ptr = (u8 *)SrcPtr;
u32 NumPages;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(SrcPtr != NULL);
Xil_AssertNonvoid((Offset + Length) < InstancePtr->Geometry.DeviceSize);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Xil_AssertNonvoid(Length != 0);
/*
* Check if the flash is write protected
*/
OnfiStatus = Onfi_CmdReadStatus(InstancePtr);
if (!(OnfiStatus & ONFI_STATUS_WP)) {
return XST_NAND_WRITE_PROTECTED;
}
/*
* Copy the user spare data buffer
*/
if (UserSparePtr == NULL) {
memset(InstancePtr->SpareBufPtr, 0xff,
InstancePtr->Geometry.SpareBytesPerPage);
} else {
memcpy(InstancePtr->SpareBufPtr, UserSparePtr,
InstancePtr->Geometry.SpareBytesPerPage);
}
Page = (u32) (Offset/InstancePtr->Geometry.BytesPerPage);
Col = (u32) (Offset & (InstancePtr->Geometry.BytesPerPage - 1));
PartialBytes = InstancePtr->Geometry.BytesPerPage - Col;
NumOfBytes = (PartialBytes < Length) ? PartialBytes:Length;
CopyOffset = InstancePtr->Geometry.BytesPerPage - PartialBytes;
/*
* Calculate number of pages to write
*/
NumPages = Length/InstancePtr->Geometry.BytesPerPage;
NumPages += (Length % InstancePtr->Geometry.BytesPerPage) ? 1:0;
/*
* Check for enough pages for cache programming
*/
if (NumPages <= 1) {
return XNandPs_Write(InstancePtr, Offset, Length, SrcPtr,
UserSparePtr);
}
while (Length && (NumPages > 0))
{
/*
* Partial write, fill the remaining buffer with 0xff
*/
if (NumOfBytes < InstancePtr->Geometry.BytesPerPage) {
BufPtr = &InstancePtr->DataBuf[0];
memset(BufPtr, 0xff,
InstancePtr->Geometry.BytesPerPage);
memcpy(BufPtr + CopyOffset, Ptr, NumOfBytes);
} else {
BufPtr = (u8 *)Ptr;
}
if (NumPages > 1) {
/*
* Send ONFI Program cache command
*/
XNandPs_SendCommand(InstancePtr,
&OnfiCommands[PAGE_CACHE_PROGRAM],
Page, 0);
/*
* Write the page data
*/
Status = InstancePtr->WritePage(InstancePtr, BufPtr);
if (Status != XST_SUCCESS) {
return Status;
}
} else {
/*
* Send ONFI Program command