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xilinx-hdmirx.c
2294 lines (1971 loc) · 76 KB
/
xilinx-hdmirx.c
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/*
* Xilinx Video HDMI RX Subsystem driver implementing a V4L2 subdevice
*
* Copyright (C) 2016-2017 Leon Woestenberg <leon@sidebranch.com>
* Copyright (C) 2016-2017 Xilinx, Inc.
*
* Authors: Leon Woestenberg <leon@sidebranch.com>
* Rohit Consul <rohitco@xilinx.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/device.h>
#include <linux/gpio/consumer.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/phy/phy.h>
#include <linux/interrupt.h>
#include <linux/platform_device.h>
#include <linux/xilinx-v4l2-controls.h>
#include <linux/v4l2-dv-timings.h>
#include <linux/firmware.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include <media/v4l2-async.h>
#include <media/v4l2-ctrls.h>
#include <media/v4l2-event.h>
#include <media/v4l2-subdev.h>
#include <media/v4l2-dv-timings.h>
#include "linux/phy/phy-vphy.h"
/* baseline driver includes */
#include "xilinx-hdmi-rx/xv_hdmirxss.h"
/* for the HMAC, using password to decrypt HDCP keys */
#include "phy-xilinx-vphy/xhdcp22_common.h"
#include "phy-xilinx-vphy/aes256.h"
#include "xlnx_hdmirx_audio.h"
#define hdmi_mutex_lock(x) mutex_lock(x)
#define hdmi_mutex_unlock(x) mutex_unlock(x)
#define HDMI_MAX_LANES 4
#define EDID_BLOCKS_MAX 10
#define EDID_BLOCK_SIZE 128
/* RX Subsystem Sub-core offsets */
#define RXSS_RX_OFFSET 0x00000u
#define RXSS_HDCP14_OFFSET 0x10000u
#define RXSS_HDCP14_TIMER_OFFSET 0x20000u
#define RXSS_HDCP22_OFFSET 0x40000u
/* HDCP22 sub-core offsets */
#define RX_HDCP22_CIPHER_OFFSET 0x00000u
#define RX_HDCP2_MMULT_OFFSET 0x10000u
#define RX_HDCP22_TIMER_OFFSET 0x20000u
#define RX_HDCP22_RNG_OFFSET 0x30000u
struct xhdmi_device {
struct device *dev;
void __iomem *iomem;
void __iomem *hdcp1x_keymngmt_iomem;
/* clocks */
struct clk *clk;
struct clk *axi_lite_clk;
/* HDMI RXSS interrupt number */
int irq;
/* HDCP interrupt numbers */
int hdcp1x_irq;
int hdcp1x_timer_irq;
int hdcp22_irq;
int hdcp22_timer_irq;
/* status */
bool hdcp_authenticated;
bool hdcp_encrypted;
bool hdcp_password_accepted;
/* delayed work to drive HDCP poll */
struct delayed_work delayed_work_hdcp_poll;
bool teardown;
struct phy *phy[HDMI_MAX_LANES];
/* mutex to prevent concurrent access to this structure */
struct mutex xhdmi_mutex;
/* protects concurrent access from interrupt context */
spinlock_t irq_lock;
/* schedule (future) work */
struct workqueue_struct *work_queue;
struct delayed_work delayed_work_enable_hotplug;
struct v4l2_subdev subdev;
/* V4L media output pad to construct the video pipeline */
struct media_pad pad;
struct v4l2_mbus_framefmt detected_format;
struct v4l2_dv_timings detected_timings;
const struct xvip_video_format *vip_format;
struct v4l2_ctrl_handler ctrl_handler;
bool cable_is_connected;
bool hdmi_stream_is_up;
/* copy of user specified EDID block, if any */
u8 edid_user[EDID_BLOCKS_MAX * EDID_BLOCK_SIZE];
/* number of actual blocks valid in edid_user */
int edid_user_blocks;
/* number of EDID blocks supported by IP */
int edid_blocks_max;
/* configuration for the baseline subsystem driver instance */
XV_HdmiRxSs_Config config;
/* bookkeeping for the baseline subsystem driver instance */
XV_HdmiRxSs xv_hdmirxss;
/* sub core interrupt status registers */
u32 IntrStatus[7];
/* pointer to xvphy */
XVphy *xvphy;
/* HDCP keys */
u8 hdcp_password[32];
u8 Hdcp22Lc128[16];
u8 Hdcp22PrivateKey[902];
u8 Hdcp14KeyA[328];
u8 Hdcp14KeyB[328];
/* flag to indicate audio is enabled in device tree */
bool audio_enabled;
/* flag to indicate audio is initialized */
bool audio_init;
/* audio data to be shared with audio module */
struct xlnx_hdmirx_audio_data *rx_audio_data;
};
// Xilinx EDID
static const u8 xilinx_edid[] = {
0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x61, 0x98, 0x34, 0x12, 0x78, 0x56, 0x34, 0x12,
0x0E, 0x1C, 0x01, 0x03, 0x80, 0xA0, 0x5A, 0x78, 0x0A, 0xEE, 0x91, 0xA3, 0x54, 0x4C, 0x99, 0x26,
0x0F, 0x50, 0x54, 0x21, 0x08, 0x00, 0x71, 0x4F, 0x81, 0xC0, 0x81, 0x00, 0x81, 0x80, 0x95, 0x00,
0xA9, 0xC0, 0xB3, 0x00, 0x01, 0x01, 0x08, 0xE8, 0x00, 0x30, 0xF2, 0x70, 0x5A, 0x80, 0xB0, 0x58,
0x8A, 0x00, 0x40, 0x84, 0x63, 0x00, 0x00, 0x1E, 0x02, 0x3A, 0x80, 0x18, 0x71, 0x38, 0x2D, 0x40,
0x58, 0x2C, 0x45, 0x00, 0x40, 0x84, 0x63, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0xFD, 0x00, 0x18,
0x4B, 0x0F, 0x8C, 0x3C, 0x00, 0x0A, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x00, 0x00, 0x00, 0xFC,
0x00, 0x58, 0x49, 0x4C, 0x49, 0x4E, 0x58, 0x20, 0x48, 0x44, 0x4D, 0x49, 0x0A, 0x20, 0x01, 0x85,
0x02, 0x03, 0x3B, 0xF1, 0x57, 0x61, 0x10, 0x1F, 0x04, 0x13, 0x05, 0x14, 0x20, 0x21, 0x22, 0x5D,
0x5E, 0x5F, 0x60, 0x65, 0x66, 0x62, 0x63, 0x64, 0x07, 0x16, 0x03, 0x12, 0x23, 0x09, 0x07, 0x07,
0x6B, 0x03, 0x0C, 0x00, 0x10, 0x00, 0x78, 0x3C, 0x20, 0x00, 0x20, 0x03, 0x67, 0xD8, 0x5D, 0xC4,
0x01, 0x78, 0x80, 0x07, 0xE3, 0x0F, 0x01, 0xE0, 0xE2, 0x00, 0xCF, 0x02, 0x3A, 0x80, 0x18, 0x71,
0x38, 0x2D, 0x40, 0x58, 0x2C, 0x45, 0x00, 0x20, 0xC2, 0x31, 0x00, 0x00, 0x1E, 0x08, 0xE8, 0x00,
0x30, 0xF2, 0x70, 0x5A, 0x80, 0xB0, 0x58, 0x8A, 0x00, 0x20, 0xC2, 0x31, 0x00, 0x00, 0x1E, 0x04,
0x74, 0x00, 0x30, 0xF2, 0x70, 0x5A, 0x80, 0xB0, 0x58, 0x8A, 0x00, 0x20, 0x52, 0x31, 0x00, 0x00,
0x1E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xDC
};
static inline struct xhdmi_device *to_xhdmi(struct v4l2_subdev *subdev)
{
return container_of(subdev, struct xhdmi_device, subdev);
}
/* -----------------------------------------------------------------------------
* V4L2 Subdevice Core Operations
*/
static const struct v4l2_event xhdmi_ev_fmt = {
.type = V4L2_EVENT_SOURCE_CHANGE,
.u.src_change.changes = V4L2_EVENT_SRC_CH_RESOLUTION,
};
static int xhdmi_subscribe_event(struct v4l2_subdev *sd, struct v4l2_fh *fh, struct v4l2_event_subscription *sub)
{
struct xhdmi_device *xhdmi = to_xhdmi(sd);
switch (sub->type) {
case V4L2_EVENT_SOURCE_CHANGE:
{
int rc;
rc = v4l2_src_change_event_subdev_subscribe(sd, fh, sub);
dev_dbg(xhdmi->dev, "xhdmi_subscribe_event(V4L2_EVENT_SOURCE_CHANGE) = %d\n", rc);
return rc;
}
#if 0
case V4L2_EVENT_CTRL:
return v4l2_ctrl_subdev_subscribe_event(sd, fh, sub);
#endif
default:
{
dev_dbg(xhdmi->dev, "xhdmi_subscribe_event() default: -EINVAL\n");
return -EINVAL;
}
}
}
/* -----------------------------------------------------------------------------
* V4L2 Subdevice Video Operations
*/
static int xhdmi_s_stream(struct v4l2_subdev *subdev, int enable)
{
struct xhdmi_device *xhdmi = to_xhdmi(subdev);
/* HDMI does not need to be enabled when we start streaming */
dev_dbg(xhdmi->dev, "xhdmi_s_stream enable = %d\n", enable);
return 0;
}
/* -----------------------------------------------------------------------------
* V4L2 Subdevice Pad Operations
*/
/* https://linuxtv.org/downloads/v4l-dvb-apis/vidioc-dv-timings-cap.html */
/* https://linuxtv.org/downloads/v4l-dvb-apis/vidioc-subdev-g-fmt.html */
static struct v4l2_mbus_framefmt *
__xhdmi_get_pad_format_ptr(struct xhdmi_device *xhdmi,
struct v4l2_subdev_pad_config *cfg,
unsigned int pad, u32 which)
{
switch (which) {
case V4L2_SUBDEV_FORMAT_TRY:
dev_dbg(xhdmi->dev, "__xhdmi_get_pad_format(): V4L2_SUBDEV_FORMAT_TRY\n");
return v4l2_subdev_get_try_format(&xhdmi->subdev, cfg, pad);
case V4L2_SUBDEV_FORMAT_ACTIVE:
dev_dbg(xhdmi->dev, "__xhdmi_get_pad_format(): V4L2_SUBDEV_FORMAT_ACTIVE\n");
dev_dbg(xhdmi->dev, "detected_format->width = %u\n", xhdmi->detected_format.width);
return &xhdmi->detected_format;
default:
return NULL;
}
}
static int xhdmi_get_format(struct v4l2_subdev *subdev,
struct v4l2_subdev_pad_config *cfg,
struct v4l2_subdev_format *fmt)
{
struct xhdmi_device *xhdmi = to_xhdmi(subdev);
dev_dbg(xhdmi->dev, "xhdmi_get_format\n");
if (fmt->pad > 0)
return -EINVAL;
/* copy either try or currently-active (i.e. detected) format to caller */
fmt->format = *__xhdmi_get_pad_format_ptr(xhdmi, cfg, fmt->pad, fmt->which);
dev_dbg(xhdmi->dev, "xhdmi_get_format, height = %u\n", fmt->format.height);
return 0;
}
/* we must modify the requested format to match what the hardware can provide */
static int xhdmi_set_format(struct v4l2_subdev *subdev,
struct v4l2_subdev_pad_config *cfg,
struct v4l2_subdev_format *fmt)
{
struct xhdmi_device *xhdmi = to_xhdmi(subdev);
dev_dbg(xhdmi->dev,"xhdmi_set_format\n");
if (fmt->pad > 0)
return -EINVAL;
hdmi_mutex_lock(&xhdmi->xhdmi_mutex);
/* there is nothing we can take from the format requested by the caller,
* by convention we must return the active (i.e. detected) format */
fmt->format = xhdmi->detected_format;
hdmi_mutex_unlock(&xhdmi->xhdmi_mutex);
return 0;
}
/* https://linuxtv.org/downloads/v4l-dvb-apis-new/media/kapi/v4l2-subdev.html#v4l2-sub-device-functions-and-data-structures
* https://linuxtv.org/downloads/v4l-dvb-apis/vidioc-g-edid.html
*/
static int xhdmi_get_edid(struct v4l2_subdev *subdev, struct v4l2_edid *edid) {
struct xhdmi_device *xhdmi = to_xhdmi(subdev);
int do_copy = 1;
if (edid->pad > 0)
return -EINVAL;
if (edid->start_block != 0)
return -EINVAL;
/* caller is only interested in the size of the EDID? */
if ((edid->start_block == 0) && (edid->blocks == 0)) do_copy = 0;
hdmi_mutex_lock(&xhdmi->xhdmi_mutex);
/* user EDID active? */
if (xhdmi->edid_user_blocks) {
if (do_copy)
memcpy(edid->edid, xhdmi->edid_user, 128 * xhdmi->edid_user_blocks);
edid->blocks = xhdmi->edid_user_blocks;
} else {
if (do_copy)
memcpy(edid->edid, &xilinx_edid[0], sizeof(xilinx_edid));
edid->blocks = sizeof(xilinx_edid) / 128;
}
hdmi_mutex_unlock(&xhdmi->xhdmi_mutex);
return 0;
}
static void xhdmi_set_hpd(struct xhdmi_device *xhdmi, int enable)
{
XV_HdmiRxSs *HdmiRxSsPtr;
HdmiRxSsPtr = &xhdmi->xv_hdmirxss;
XV_HdmiRx_SetHpd(HdmiRxSsPtr->HdmiRxPtr, enable);
}
static void xhdmi_delayed_work_enable_hotplug(struct work_struct *work)
{
struct delayed_work *dwork = to_delayed_work(work);
struct xhdmi_device *xhdmi = container_of(dwork, struct xhdmi_device,
delayed_work_enable_hotplug);
XV_HdmiRxSs *HdmiRxSsPtr;
HdmiRxSsPtr = &xhdmi->xv_hdmirxss;
XV_HdmiRx_SetHpd(HdmiRxSsPtr->HdmiRxPtr, 1);
}
static int xhdmi_set_edid(struct v4l2_subdev *subdev, struct v4l2_edid *edid) {
struct xhdmi_device *xhdmi = to_xhdmi(subdev);
XV_HdmiRxSs *HdmiRxSsPtr = &xhdmi->xv_hdmirxss;
if (edid->pad > 0)
return -EINVAL;
if (edid->start_block != 0)
return -EINVAL;
if (edid->blocks > xhdmi->edid_blocks_max) {
/* notify caller of how many EDID blocks this driver supports */
edid->blocks = xhdmi->edid_blocks_max;
return -E2BIG;
}
hdmi_mutex_lock(&xhdmi->xhdmi_mutex);
xhdmi->edid_user_blocks = edid->blocks;
/* Disable hotplug and I2C access to EDID RAM from DDC port */
cancel_delayed_work_sync(&xhdmi->delayed_work_enable_hotplug);
xhdmi_set_hpd(xhdmi, 0);
if (edid->blocks) {
memcpy(xhdmi->edid_user, edid->edid, 128 * edid->blocks);
XV_HdmiRxSs_LoadEdid(HdmiRxSsPtr, (u8 *)&xhdmi->edid_user, 128 * xhdmi->edid_user_blocks);
/* enable hotplug after 100 ms */
queue_delayed_work(xhdmi->work_queue,
&xhdmi->delayed_work_enable_hotplug, HZ / 10);
}
hdmi_mutex_unlock(&xhdmi->xhdmi_mutex);
return 0;
}
/* -----------------------------------------------------------------------------
* V4L2 Subdevice Operations
*/
static int xhdmi_enum_frame_size(struct v4l2_subdev *subdev,
struct v4l2_subdev_pad_config *cfg,
struct v4l2_subdev_frame_size_enum *fse)
{
if (fse->pad > 0)
return -EINVAL;
/* we support a non-discrete set, i.e. contiguous range of frame sizes,
* do not return a discrete set */
return 0;
}
/**
* xhdmi_enum_mbus_code - Enumerate the media format code
* @subdev: V4L2 subdevice
* @cfg: V4L2 subdev pad configuration
* @code: returning media bus code
*
* Enumerate the media bus code of the subdevice. Return the corresponding
* pad format code. This function only works for subdevices with fixed format
* on all pads. Subdevices with multiple format should have their own
* function to enumerate mbus codes.
*
* Return: 0 if the media bus code is found, or -EINVAL if the format index
* is not valid.
*/
int xhdmi_enum_mbus_code(struct v4l2_subdev *subdev,
struct v4l2_subdev_pad_config *cfg,
struct v4l2_subdev_mbus_code_enum *code)
{
struct v4l2_mbus_framefmt *format;
/* Enumerating frame sizes based on the active configuration isn't
* supported yet.
*/
if (code->which == V4L2_SUBDEV_FORMAT_ACTIVE)
return -EINVAL;
if (code->index)
return -EINVAL;
format = v4l2_subdev_get_try_format(subdev, cfg, code->pad);
code->code = format->code;
return 0;
}
static int xhdmi_dv_timings_cap(struct v4l2_subdev *subdev,
struct v4l2_dv_timings_cap *cap)
{
if (cap->pad != 0)
return -EINVAL;
cap->type = V4L2_DV_BT_656_1120;
cap->bt.max_width = 4096;
cap->bt.max_height = 2160;
cap->bt.min_pixelclock = 25000000;
cap->bt.max_pixelclock = 297000000;
cap->bt.standards = V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT;
cap->bt.capabilities = V4L2_DV_BT_CAP_PROGRESSIVE |
V4L2_DV_BT_CAP_REDUCED_BLANKING | V4L2_DV_BT_CAP_CUSTOM;
return 0;
}
static int xhdmi_query_dv_timings(struct v4l2_subdev *subdev,
struct v4l2_dv_timings *timings)
{
struct xhdmi_device *xhdmi = to_xhdmi(subdev);
if (!timings)
return -EINVAL;
hdmi_mutex_lock(&xhdmi->xhdmi_mutex);
if (!xhdmi->hdmi_stream_is_up) {
hdmi_mutex_unlock(&xhdmi->xhdmi_mutex);
return -ENOLINK;
}
/* copy detected timings into destination */
*timings = xhdmi->detected_timings;
hdmi_mutex_unlock(&xhdmi->xhdmi_mutex);
return 0;
}
/* struct v4l2_subdev_internal_ops.open */
static int xhdmi_open(struct v4l2_subdev *subdev, struct v4l2_subdev_fh *fh)
{
struct xhdmi_device *xhdmi = to_xhdmi(subdev);
dev_dbg(xhdmi->dev,"xhdmi_open\n");
return 0;
}
/* struct v4l2_subdev_internal_ops.close */
static int xhdmi_close(struct v4l2_subdev *subdev, struct v4l2_subdev_fh *fh)
{
struct xhdmi_device *xhdmi = to_xhdmi(subdev);
dev_dbg(xhdmi->dev,"xhdmi_close\n");
return 0;
}
static int xhdmi_s_ctrl(struct v4l2_ctrl *ctrl)
{
return 0;
}
static const struct v4l2_ctrl_ops xhdmi_ctrl_ops = {
.s_ctrl = xhdmi_s_ctrl,
};
static struct v4l2_subdev_core_ops xhdmi_core_ops = {
.subscribe_event = xhdmi_subscribe_event,
.unsubscribe_event = v4l2_event_subdev_unsubscribe,
};
static struct v4l2_subdev_video_ops xhdmi_video_ops = {
.s_stream = xhdmi_s_stream,
.query_dv_timings = xhdmi_query_dv_timings,
};
/* If the subdev driver intends to process video and integrate with the media framework,
* it must implement format related functionality using v4l2_subdev_pad_ops instead of
* v4l2_subdev_video_ops. */
static struct v4l2_subdev_pad_ops xhdmi_pad_ops = {
.enum_mbus_code = xhdmi_enum_mbus_code,
.enum_frame_size = xhdmi_enum_frame_size,
.get_fmt = xhdmi_get_format,
.set_fmt = xhdmi_set_format,
.get_edid = xhdmi_get_edid,
.set_edid = xhdmi_set_edid,
.dv_timings_cap = xhdmi_dv_timings_cap,
};
static struct v4l2_subdev_ops xhdmi_ops = {
.core = &xhdmi_core_ops,
.video = &xhdmi_video_ops,
.pad = &xhdmi_pad_ops,
};
static const struct v4l2_subdev_internal_ops xhdmi_internal_ops = {
.open = xhdmi_open,
.close = xhdmi_close,
};
/* -----------------------------------------------------------------------------
* Media Operations
*/
static const struct media_entity_operations xhdmi_media_ops = {
.link_validate = v4l2_subdev_link_validate,
};
/* -----------------------------------------------------------------------------
* Power Management
*/
void HdmiRx_PioIntrHandler(XV_HdmiRx *InstancePtr);
void HdmiRx_TmrIntrHandler(XV_HdmiRx *InstancePtr);
void HdmiRx_VtdIntrHandler(XV_HdmiRx *InstancePtr);
void HdmiRx_DdcIntrHandler(XV_HdmiRx *InstancePtr);
void HdmiRx_AuxIntrHandler(XV_HdmiRx *InstancePtr);
void HdmiRx_AudIntrHandler(XV_HdmiRx *InstancePtr);
void HdmiRx_LinkStatusIntrHandler(XV_HdmiRx *InstancePtr);
static void XV_HdmiRxSs_IntrEnable(XV_HdmiRxSs *HdmiRxSsPtr)
{
XV_HdmiRx_PioIntrEnable(HdmiRxSsPtr->HdmiRxPtr);
XV_HdmiRx_TmrIntrEnable(HdmiRxSsPtr->HdmiRxPtr);
XV_HdmiRx_VtdIntrEnable(HdmiRxSsPtr->HdmiRxPtr);
XV_HdmiRx_DdcIntrEnable(HdmiRxSsPtr->HdmiRxPtr);
XV_HdmiRx_AuxIntrEnable(HdmiRxSsPtr->HdmiRxPtr);
XV_HdmiRx_AudioIntrEnable(HdmiRxSsPtr->HdmiRxPtr);
}
static void XV_HdmiRxSs_IntrDisable(XV_HdmiRxSs *HdmiRxSsPtr)
{
XV_HdmiRx_PioIntrDisable(HdmiRxSsPtr->HdmiRxPtr);
XV_HdmiRx_TmrIntrDisable(HdmiRxSsPtr->HdmiRxPtr);
XV_HdmiRx_VtdIntrDisable(HdmiRxSsPtr->HdmiRxPtr);
XV_HdmiRx_DdcIntrDisable(HdmiRxSsPtr->HdmiRxPtr);
XV_HdmiRx_AuxIntrDisable(HdmiRxSsPtr->HdmiRxPtr);
XV_HdmiRx_AudioIntrDisable(HdmiRxSsPtr->HdmiRxPtr);
XV_HdmiRx_LinkIntrDisable(HdmiRxSsPtr->HdmiRxPtr);
}
static int __maybe_unused hdmirx_pm_suspend(struct device *dev)
{
unsigned long flags;
struct xhdmi_device *xhdmi = dev_get_drvdata(dev);
XV_HdmiRxSs *HdmiRxSsPtr = (XV_HdmiRxSs *)&xhdmi->xv_hdmirxss;
dev_dbg(xhdmi->dev,"HDMI RX suspend function called\n");
spin_lock_irqsave(&xhdmi->irq_lock, flags);
XV_HdmiRxSs_IntrDisable(HdmiRxSsPtr);
spin_unlock_irqrestore(&xhdmi->irq_lock, flags);
return 0;
}
static int __maybe_unused hdmirx_pm_resume(struct device *dev)
{
unsigned long flags;
struct xhdmi_device *xhdmi = dev_get_drvdata(dev);
XV_HdmiRxSs *HdmiRxSsPtr = (XV_HdmiRxSs *)&xhdmi->xv_hdmirxss;
dev_dbg(xhdmi->dev,"HDMI RX resume function called\n");
spin_lock_irqsave(&xhdmi->irq_lock, flags);
XV_HdmiRxSs_IntrEnable(HdmiRxSsPtr);
spin_unlock_irqrestore(&xhdmi->irq_lock, flags);
return 0;
}
static irqreturn_t hdmirx_irq_handler(int irq, void *dev_id)
{
struct xhdmi_device *xhdmi;
XV_HdmiRxSs *HdmiRxSsPtr;
unsigned long flags;
xhdmi = (struct xhdmi_device *)dev_id;
HdmiRxSsPtr = (XV_HdmiRxSs *)&xhdmi->xv_hdmirxss;
if (HdmiRxSsPtr->IsReady != XIL_COMPONENT_IS_READY) {
printk(KERN_INFO "hdmirx_irq_handler(): HDMI RX SS is not initialized?!\n");
}
/* read status registers */
xhdmi->IntrStatus[0] = XV_HdmiRx_ReadReg(HdmiRxSsPtr->HdmiRxPtr->Config.BaseAddress, (XV_HDMIRX_PIO_STA_OFFSET)) & (XV_HDMIRX_PIO_STA_IRQ_MASK);
xhdmi->IntrStatus[1] = XV_HdmiRx_ReadReg(HdmiRxSsPtr->HdmiRxPtr->Config.BaseAddress, (XV_HDMIRX_TMR_STA_OFFSET)) & (XV_HDMIRX_TMR_STA_IRQ_MASK);
xhdmi->IntrStatus[2] = XV_HdmiRx_ReadReg(HdmiRxSsPtr->HdmiRxPtr->Config.BaseAddress, (XV_HDMIRX_VTD_STA_OFFSET)) & (XV_HDMIRX_VTD_STA_IRQ_MASK);
xhdmi->IntrStatus[3] = XV_HdmiRx_ReadReg(HdmiRxSsPtr->HdmiRxPtr->Config.BaseAddress, (XV_HDMIRX_DDC_STA_OFFSET)) & (XV_HDMIRX_DDC_STA_IRQ_MASK);
xhdmi->IntrStatus[4] = XV_HdmiRx_ReadReg(HdmiRxSsPtr->HdmiRxPtr->Config.BaseAddress, (XV_HDMIRX_AUX_STA_OFFSET)) & (XV_HDMIRX_AUX_STA_IRQ_MASK);
xhdmi->IntrStatus[5] = XV_HdmiRx_ReadReg(HdmiRxSsPtr->HdmiRxPtr->Config.BaseAddress, (XV_HDMIRX_AUD_STA_OFFSET)) & (XV_HDMIRX_AUD_STA_IRQ_MASK);
xhdmi->IntrStatus[6] = XV_HdmiRx_ReadReg(HdmiRxSsPtr->HdmiRxPtr->Config.BaseAddress, (XV_HDMIRX_LNKSTA_STA_OFFSET)) & (XV_HDMIRX_LNKSTA_STA_IRQ_MASK);
spin_lock_irqsave(&xhdmi->irq_lock, flags);
/* mask interrupt request */
XV_HdmiRxSs_IntrDisable(HdmiRxSsPtr);
spin_unlock_irqrestore(&xhdmi->irq_lock, flags);
/* call bottom-half */
return IRQ_WAKE_THREAD;
}
static irqreturn_t hdmirx_irq_thread(int irq, void *dev_id)
{
struct xhdmi_device *xhdmi;
XV_HdmiRxSs *HdmiRxSsPtr;
unsigned long flags;
xhdmi = (struct xhdmi_device *)dev_id;
if (xhdmi->teardown) {
printk(KERN_INFO "irq_thread: teardown\n");
return IRQ_HANDLED;
}
HdmiRxSsPtr = (XV_HdmiRxSs *)&xhdmi->xv_hdmirxss;
hdmi_mutex_lock(&xhdmi->xhdmi_mutex);
/* call baremetal interrupt handler, this in turn will
* call the registed callbacks functions */
if (xhdmi->IntrStatus[0]) HdmiRx_PioIntrHandler(HdmiRxSsPtr->HdmiRxPtr);
if (xhdmi->IntrStatus[1]) HdmiRx_TmrIntrHandler(HdmiRxSsPtr->HdmiRxPtr);
if (xhdmi->IntrStatus[2]) HdmiRx_VtdIntrHandler(HdmiRxSsPtr->HdmiRxPtr);
if (xhdmi->IntrStatus[3]) HdmiRx_DdcIntrHandler(HdmiRxSsPtr->HdmiRxPtr);
if (xhdmi->IntrStatus[4]) HdmiRx_AuxIntrHandler(HdmiRxSsPtr->HdmiRxPtr);
if (xhdmi->IntrStatus[5]) HdmiRx_AudIntrHandler(HdmiRxSsPtr->HdmiRxPtr);
if (xhdmi->IntrStatus[6]) HdmiRx_LinkStatusIntrHandler(HdmiRxSsPtr->HdmiRxPtr);
hdmi_mutex_unlock(&xhdmi->xhdmi_mutex);
spin_lock_irqsave(&xhdmi->irq_lock, flags);
/* unmask interrupt request */
XV_HdmiRxSs_IntrEnable(HdmiRxSsPtr);
spin_unlock_irqrestore(&xhdmi->irq_lock, flags);
return IRQ_HANDLED;
}
/* top-half interrupt handler for HDMI RX HDCP */
static irqreturn_t hdmirx_hdcp_irq_handler(int irq, void *dev_id)
{
struct xhdmi_device *xhdmi;
XV_HdmiRxSs *HdmiRxSsPtr;
unsigned long flags;
xhdmi = (struct xhdmi_device *)dev_id;
HdmiRxSsPtr = (XV_HdmiRxSs *)&xhdmi->xv_hdmirxss;
spin_lock_irqsave(&xhdmi->irq_lock, flags);
/* mask/disable interrupt requests */
if (irq == xhdmi->hdcp1x_irq) {
XHdcp1x_WriteReg(HdmiRxSsPtr->Hdcp14Ptr->Config.BaseAddress,
XHDCP1X_CIPHER_REG_INTERRUPT_MASK, (u32)0xFFFFFFFFu);
} else if (irq == xhdmi->hdcp1x_timer_irq) {
XTmrCtr_DisableIntr(HdmiRxSsPtr->HdcpTimerPtr->BaseAddress, 0);
} else if (irq == xhdmi->hdcp22_timer_irq) {
XTmrCtr_DisableIntr(HdmiRxSsPtr->Hdcp22Ptr->TimerInst.BaseAddress, 0);
XTmrCtr_DisableIntr(HdmiRxSsPtr->Hdcp22Ptr->TimerInst.BaseAddress, 1);
}
spin_unlock_irqrestore(&xhdmi->irq_lock, flags);
/* call bottom-half */
return IRQ_WAKE_THREAD;
}
/* HDCP service routine, runs outside of interrupt context and can sleep and takes mutexes */
static irqreturn_t hdmirx_hdcp_irq_thread(int irq, void *dev_id)
{
struct xhdmi_device *xhdmi;
XV_HdmiRxSs *HdmiRxSsPtr;
unsigned long flags;
xhdmi = (struct xhdmi_device *)dev_id;
HdmiRxSsPtr = (XV_HdmiRxSs *)&xhdmi->xv_hdmirxss;
/* driver is being torn down, do not process further interrupts */
if (xhdmi->teardown) {
printk(KERN_INFO "irq_thread: teardown\n");
return IRQ_HANDLED;
}
/* invoke the bare-metal interrupt handler under mutex lock */
hdmi_mutex_lock(&xhdmi->xhdmi_mutex);
if (irq == xhdmi->hdcp1x_irq) {
XV_HdmiRxSS_HdcpIntrHandler(HdmiRxSsPtr);
} else if (irq == xhdmi->hdcp1x_timer_irq) {
XV_HdmiRxSS_HdcpTimerIntrHandler(HdmiRxSsPtr);
} else if (irq == xhdmi->hdcp22_timer_irq) {
XV_HdmiRxSS_Hdcp22TimerIntrHandler(HdmiRxSsPtr);
}
hdmi_mutex_unlock(&xhdmi->xhdmi_mutex);
/* re-enable interrupt requests */
spin_lock_irqsave(&xhdmi->irq_lock, flags);
if (irq == xhdmi->hdcp1x_irq) {
XHdcp1x_WriteReg(HdmiRxSsPtr->Hdcp14Ptr->Config.BaseAddress,
XHDCP1X_CIPHER_REG_INTERRUPT_MASK, (u32)0xFFFFFFFDu);
} else if (irq == xhdmi->hdcp1x_timer_irq) {
XTmrCtr_EnableIntr(HdmiRxSsPtr->HdcpTimerPtr->BaseAddress, 0);
} else if (irq == xhdmi->hdcp22_timer_irq) {
XTmrCtr_EnableIntr(HdmiRxSsPtr->Hdcp22Ptr->TimerInst.BaseAddress, 0);
XTmrCtr_EnableIntr(HdmiRxSsPtr->Hdcp22Ptr->TimerInst.BaseAddress, 1);
}
spin_unlock_irqrestore(&xhdmi->irq_lock, flags);
return IRQ_HANDLED;
}
/* callbacks from HDMI RX SS interrupt handler
* these are called with the xhdmi->mutex locked and the xvphy_mutex non-locked
* to prevent mutex deadlock, always lock the xhdmi first, then the xvphy mutex */
static void RxConnectCallback(void *CallbackRef)
{
struct xhdmi_device *xhdmi = (struct xhdmi_device *)CallbackRef;
XV_HdmiRxSs *HdmiRxSsPtr = &xhdmi->xv_hdmirxss;
XVphy *VphyPtr = xhdmi->xvphy;
if (!xhdmi || !HdmiRxSsPtr || !VphyPtr) return;
xhdmi->cable_is_connected = !!HdmiRxSsPtr->IsStreamConnected;
dev_dbg(xhdmi->dev,"RxConnectCallback(): cable is %sconnected.\n",
xhdmi->cable_is_connected? "": "dis");
xvphy_mutex_lock(xhdmi->phy[0]);
/* RX cable is connected? */
if (HdmiRxSsPtr->IsStreamConnected) {
XVphy_IBufDsEnable(VphyPtr, 0, XVPHY_DIR_RX, (TRUE));
} else {
/* clear GT RX TMDS clock ratio */
VphyPtr->HdmiRxTmdsClockRatio = 0;
XVphy_IBufDsEnable(VphyPtr, 0, XVPHY_DIR_RX, (FALSE));
}
xvphy_mutex_unlock(xhdmi->phy[0]);
}
static void RxStreamDownCallback(void *CallbackRef)
{
struct xhdmi_device *xhdmi = (struct xhdmi_device *)CallbackRef;
XV_HdmiRxSs *HdmiRxSsPtr = &xhdmi->xv_hdmirxss;
if (!xhdmi || !HdmiRxSsPtr) return;
(void)HdmiRxSsPtr;
dev_dbg(xhdmi->dev,"RxStreamDownCallback()\n");
xhdmi->hdmi_stream_is_up = 0;
xhdmi->hdcp_authenticated = 0;
}
static void RxStreamInitCallback(void *CallbackRef)
{
struct xhdmi_device *xhdmi = (struct xhdmi_device *)CallbackRef;
XV_HdmiRxSs *HdmiRxSsPtr = &xhdmi->xv_hdmirxss;
XVphy *VphyPtr = xhdmi->xvphy;
XVidC_VideoStream *HdmiRxSsVidStreamPtr;
u32 Status;
if (!xhdmi || !HdmiRxSsPtr || !VphyPtr) return;
dev_dbg(xhdmi->dev,"RxStreamInitCallback\r\n");
// Calculate RX MMCM parameters
// In the application the YUV422 colordepth is 12 bits
// However the HDMI transports YUV422 in 8 bits.
// Therefore force the colordepth to 8 bits when the colorspace is YUV422
HdmiRxSsVidStreamPtr = XV_HdmiRxSs_GetVideoStream(HdmiRxSsPtr);
xvphy_mutex_lock(xhdmi->phy[0]);
if (HdmiRxSsVidStreamPtr->ColorFormatId == XVIDC_CSF_YCRCB_422) {
Status = XVphy_HdmiCfgCalcMmcmParam(VphyPtr, 0, XVPHY_CHANNEL_ID_CH1,
XVPHY_DIR_RX,
HdmiRxSsVidStreamPtr->PixPerClk,
XVIDC_BPC_8);
// Other colorspaces
} else {
Status = XVphy_HdmiCfgCalcMmcmParam(VphyPtr, 0, XVPHY_CHANNEL_ID_CH1,
XVPHY_DIR_RX,
HdmiRxSsVidStreamPtr->PixPerClk,
HdmiRxSsVidStreamPtr->ColorDepth);
}
if (Status == XST_FAILURE) {
xvphy_mutex_unlock(xhdmi->phy[0]);
return;
}
// Enable and configure RX MMCM
XVphy_MmcmStart(VphyPtr, 0, XVPHY_DIR_RX);
//wait 10ms for PLL to stabilize
usleep_range(10000, 11000);
xvphy_mutex_unlock(xhdmi->phy[0]);
}
/* @TODO Once this upstream V4L2 patch lands, consider VIC support: https://patchwork.linuxtv.org/patch/37137/ */
static void RxStreamUpCallback(void *CallbackRef)
{
struct xhdmi_device *xhdmi = (struct xhdmi_device *)CallbackRef;
XV_HdmiRxSs *HdmiRxSsPtr = &xhdmi->xv_hdmirxss;
XVidC_VideoStream *Stream;
if (!xhdmi || !HdmiRxSsPtr || !HdmiRxSsPtr->HdmiRxPtr) return;
dev_dbg(xhdmi->dev,"RxStreamUpCallback() - stream is up.\n");
Stream = XV_HdmiRxSs_GetVideoStream(HdmiRxSsPtr);
#ifdef DEBUG
XV_HdmiRx_DebugInfo(HdmiRxSsPtr->HdmiRxPtr);
#endif
/* http://lxr.free-electrons.com/source/include/uapi/linux/videodev2.h#L1229 */
xhdmi->detected_format.width = Stream->Timing.HActive;
xhdmi->detected_format.height = Stream->Timing.VActive;
/* Check for the NTSC and PAL resolutions. RX will detect the resolution as 1440x240 (NTSC resolution)
* for field 0 and field 1.
* Upon detecting this RX should drop the extra pixel and send only 720x240 per field to Frame buffer write IP.
* Therefore in the end of this function, we will have to call API to configure bridge for pixel drop.
*/
if((((Stream->Timing.HActive == 1440) && (Stream->Timing.VActive == 240) && (Stream->FrameRate == 60)) ||
((Stream->Timing.HActive == 1440) && (Stream->Timing.VActive == 288) && (Stream->FrameRate == 50)))
&& (!!Stream->IsInterlaced))
{
xhdmi->detected_format.width /= 2;
dev_dbg(xhdmi->dev, "NTSC/PAL detected_format.width after divide by 2 = %d\n", xhdmi->detected_format.width);
}
/* There is no point in setting feild V4L2_FIELD_INTERLACED as it is not getting used */
//xhdmi->detected_format.field = Stream->IsInterlaced? V4L2_FIELD_INTERLACED: V4L2_FIELD_NONE;
xhdmi->detected_format.field = V4L2_FIELD_NONE;
/* https://linuxtv.org/downloads/v4l-dvb-apis/ch02s05.html#v4l2-colorspace */
if (Stream->ColorFormatId == XVIDC_CSF_RGB) {
dev_dbg(xhdmi->dev,"xhdmi->detected_format.colorspace = V4L2_COLORSPACE_SRGB\n");
xhdmi->detected_format.colorspace = V4L2_COLORSPACE_SRGB;
} else {
dev_dbg(xhdmi->dev,"xhdmi->detected_format.colorspace = V4L2_COLORSPACE_REC709\n");
xhdmi->detected_format.colorspace = V4L2_COLORSPACE_REC709;
}
/* https://linuxtv.org/downloads/v4l-dvb-apis/subdev.html#v4l2-mbus-framefmt */
/* see UG934 page 8 */
/* the V4L2 media bus fmt codes match the AXI S format, and match those from TPG */
if (Stream->ColorFormatId == XVIDC_CSF_RGB) {
if (HdmiRxSsPtr->Config.MaxBitsPerPixel == 10) {
if(Stream->ColorDepth == XVIDC_BPC_8) {
xhdmi->detected_format.code = MEDIA_BUS_FMT_RBG888_1X24;
dev_dbg(xhdmi->dev,"XVIDC_CSF_RGB -> MEDIA_BUS_FMT_RBG888_1X24\n");
} else {
xhdmi->detected_format.code = MEDIA_BUS_FMT_RBG101010_1X30;
dev_dbg(xhdmi->dev,"XVIDC_CSF_RGB -> MEDIA_BUS_FMT_RBG101010_1X30\n");
}
/* Default will always be 8 */
} else {
xhdmi->detected_format.code = MEDIA_BUS_FMT_RBG888_1X24;
dev_dbg(xhdmi->dev,"XVIDC_CSF_RGB -> MEDIA_BUS_FMT_RBG888_1X24\n");
}
/* YUV444 */
} else if (Stream->ColorFormatId == XVIDC_CSF_YCRCB_444) {
if (HdmiRxSsPtr->Config.MaxBitsPerPixel == 10) {
if(Stream->ColorDepth == XVIDC_BPC_8) {
xhdmi->detected_format.code = MEDIA_BUS_FMT_VUY8_1X24;
dev_dbg(xhdmi->dev,"XVIDC_CSF_YCRCB_444 -> MEDIA_BUS_FMT_VUY8_1X24\n");
} else {
xhdmi->detected_format.code = MEDIA_BUS_FMT_VUY10_1X30;
dev_dbg(xhdmi->dev,"XVIDC_CSF_YCRCB_444 -> MEDIA_BUS_FMT_VUY10_1X30\n");
}
/* Default will always be 8 */
} else {
xhdmi->detected_format.code = MEDIA_BUS_FMT_VUY8_1X24;
dev_dbg(xhdmi->dev,"XVIDC_CSF_YCRCB_444 -> MEDIA_BUS_FMT_VUY8_1X24\n");
}
/* Since 422 is always detected as 12 BPC, set the 8bit media bus format */
} else if (Stream->ColorFormatId == XVIDC_CSF_YCRCB_422) {
if (HdmiRxSsPtr->Config.MaxBitsPerPixel == 10) {
xhdmi->detected_format.code = MEDIA_BUS_FMT_UYVY10_1X20;
dev_dbg(xhdmi->dev,"XVIDC_CSF_YCRCB_422 -> MEDIA_BUS_FMT_UYVY10_1X20\n");
/* Default will always be 8 */
} else {
xhdmi->detected_format.code = MEDIA_BUS_FMT_UYVY8_1X16;
dev_dbg(xhdmi->dev,"XVIDC_CSF_YCRCB_422 -> MEDIA_BUS_FMT_UYVY8_1X16\n");
}
/* YUV420 */
} else if (Stream->ColorFormatId == XVIDC_CSF_YCRCB_420) {
if (HdmiRxSsPtr->Config.MaxBitsPerPixel == 10) {
if(Stream->ColorDepth == XVIDC_BPC_8) {
xhdmi->detected_format.code = MEDIA_BUS_FMT_VYYUYY8_1X24;
dev_dbg(xhdmi->dev,"XVIDC_CSF_YCRCB_420 -> MEDIA_BUS_FMT_VYYUYY8_1X24\n");
} else {
xhdmi->detected_format.code = MEDIA_BUS_FMT_VYYUYY10_4X20;
dev_dbg(xhdmi->dev,"XVIDC_CSF_YCRCB_420 -> MEDIA_BUS_FMT_VYYUYY10_1X24\n");
}
} else {
xhdmi->detected_format.code = MEDIA_BUS_FMT_VYYUYY8_1X24;
dev_dbg(xhdmi->dev,"XVIDC_CSF_YCRCB_420 -> MEDIA_BUS_FMT_VYYUYY8_1X24\n");
}
}
xhdmi->detected_format.xfer_func = V4L2_XFER_FUNC_DEFAULT;
xhdmi->detected_format.ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT;
xhdmi->detected_format.quantization = V4L2_QUANTIZATION_DEFAULT;
/* map to v4l2_dv_timings */
xhdmi->detected_timings.type = V4L2_DV_BT_656_1120;
/* Read Active Pixels */
xhdmi->detected_timings.bt.width = Stream->Timing.HActive;
/* Active lines field 1 */
xhdmi->detected_timings.bt.height = Stream->Timing.VActive;
/* Interlaced */
xhdmi->detected_timings.bt.interlaced = !!Stream->IsInterlaced;
xhdmi->detected_timings.bt.polarities =
/* Vsync polarity, Positive == 1 */
(Stream->Timing.VSyncPolarity? V4L2_DV_VSYNC_POS_POL: 0) |
/* Hsync polarity, Positive == 1 */
(Stream->Timing.HSyncPolarity? V4L2_DV_HSYNC_POS_POL: 0);
/* from xvid.c:XVidC_GetPixelClockHzByVmId() but without VmId */
if (Stream->IsInterlaced) {
xhdmi->detected_timings.bt.pixelclock =
(Stream->Timing.F0PVTotal + Stream->Timing.F1VTotal) *
Stream->FrameRate / 2;
} else {
xhdmi->detected_timings.bt.pixelclock =
Stream->Timing.F0PVTotal * Stream->FrameRate;
}
xhdmi->detected_timings.bt.pixelclock *= Stream->Timing.HTotal;
/* Check for the NTSC and PAL resolutions. RX will detect the resolution as 1440x240 (NTSC resolution)
* for field 0 and field 1.
* Upon detecting this RX should drop the extra pixel and send only 720x240 per field to Frame buffer write IP.
* Therefore in the end of this function, we will have to call API to configure bridge for pixel drop.
*/
if((((Stream->Timing.HActive == 1440) && (Stream->Timing.VActive == 240) && (Stream->FrameRate == 60)) ||
((Stream->Timing.HActive == 1440) && (Stream->Timing.VActive == 288) && (Stream->FrameRate == 50)))
&& (!!Stream->IsInterlaced))
{
xhdmi->detected_timings.bt.width /= 2;
dev_dbg(xhdmi->dev, "NTSC/PAL detected_timings.bt.width after divide by 2 = %d\n", xhdmi->detected_format.width);
dev_dbg(xhdmi->dev,"Programming RX bridge for dropping pixels\n");
XV_HdmiRxSs_BridgeYuv420(HdmiRxSsPtr, FALSE);
XV_HdmiRxSs_BridgePixelDrop(HdmiRxSsPtr, TRUE);
}
dev_dbg(xhdmi->dev,"HdmiRxSsPtr->HdmiRxPtr->Stream.PixelClk = %d\n", HdmiRxSsPtr->HdmiRxPtr->Stream.PixelClk);
/* Read HFront Porch */
xhdmi->detected_timings.bt.hfrontporch = Stream->Timing.HFrontPorch;
/* Read Hsync Width */
xhdmi->detected_timings.bt.hsync = Stream->Timing.HSyncWidth;
/* Read HBack Porch */
xhdmi->detected_timings.bt.hbackporch = Stream->Timing.HBackPorch;
/* Read VFront Porch field 1*/
xhdmi->detected_timings.bt.vfrontporch = Stream->Timing.F0PVFrontPorch;
/* Read VSync Width field 1*/
xhdmi->detected_timings.bt.vsync = Stream->Timing.F0PVSyncWidth;
/* Read VBack Porch field 1 */
xhdmi->detected_timings.bt.vbackporch = Stream->Timing.F0PVBackPorch;
/* Read VFront Porch field 2*/
xhdmi->detected_timings.bt.il_vfrontporch = Stream->Timing.F1VFrontPorch;
/* Read VSync Width field 2*/
xhdmi->detected_timings.bt.il_vsync = Stream->Timing.F1VSyncWidth;
/* Read VBack Porch field 2 */
xhdmi->detected_timings.bt.il_vbackporch = Stream->Timing.F1VBackPorch;
xhdmi->detected_timings.bt.standards = V4L2_DV_BT_STD_CEA861;
xhdmi->detected_timings.bt.flags = V4L2_DV_FL_IS_CE_VIDEO;
(void)Stream->VmId;
xhdmi->hdmi_stream_is_up = 1;
/* notify source format change event */
v4l2_subdev_notify_event(&xhdmi->subdev, &xhdmi_ev_fmt);
/* TODO: As subsystem API XV_HdmiRxSs_AudioEnable is not available,
* core API is used currently.
*/
if (xhdmi->audio_init)
XV_HdmiRx_AudioEnable(HdmiRxSsPtr->HdmiRxPtr);
#ifdef DEBUG
v4l2_print_dv_timings("xilinx-hdmi-rx", "", & xhdmi->detected_timings, 1);
#endif
}
static void RxBrdgOverflowCallback(void *CallbackRef)
{
struct xhdmi_device *xhdmi = (struct xhdmi_device *)CallbackRef;
XV_HdmiRxSs *HdmiRxSsPtr = &xhdmi->xv_hdmirxss;
//dev_dbg(xhdmi->dev,"RxBrdgOverflowCallback()\n");
}
static void RxAudCallback(void *CallbackRef)
{
struct xhdmi_device *xhdmi = (struct xhdmi_device *)CallbackRef;
XV_HdmiRxSs *HdmiRxSsPtr = &xhdmi->xv_hdmirxss;
struct xlnx_hdmirx_audio_data *adata = xhdmi->rx_audio_data;
dev_dbg(xhdmi->dev,"%s()\n", __func__);
adata->format = XV_HdmiRxSs_GetAudioFormat(HdmiRxSsPtr);
adata->num_channels = XV_HdmiRxSs_GetAudioChannels(HdmiRxSsPtr);
//ToDo: Insert registered ALSA driver call-back
if (xhdmi->audio_init && adata->num_channels >= 2) {
adata->audio_detected = true;
wake_up_interruptible(&adata->audio_update_q);
}
dev_dbg(xhdmi->dev, "Channels = %d\n", adata->num_channels);
dev_dbg(xhdmi->dev, "Format = %d\n", adata->format);
}
static void RxAuxCallback(void *CallbackRef)
{
struct xhdmi_device *xhdmi = (struct xhdmi_device *)CallbackRef;
XV_HdmiRxSs *HdmiRxSsPtr = &xhdmi->xv_hdmirxss;
XHdmiC_Aux *AuxPtr;
XHdmiC_Aux AuxFifo;
AuxPtr = XV_HdmiRxSs_GetAuxiliary(HdmiRxSsPtr);
//dev_dbg(xhdmi->dev,"%s()\n", __func__);
/* read out the aux packet to a local buffer
* currently only 1 Aux packet (last recvd) is stored
*/
if (AuxPtr->Header.Byte[0] != AUX_GENERAL_CONTROL_PACKET_TYPE) {