versal.dtsi

// SPDX-License-Identifier: GPL-2.0
/*
 * dts file for Xilinx Versal
 *
 * (C) Copyright 2017 - 2021, Xilinx, Inc.
 *
 * Michal Simek <michal.simek@amd.com>
 */

/dts-v1/;

/ {
	compatible = "xlnx,versal";
	#address-cells = <2>;
	#size-cells = <2>;
	model = "Xilinx Versal";

	options {
		u-boot {
			compatible = "u-boot,config";
			bootscr-address = /bits/ 64 <0x20000000>;
		};
	};

	cpus: cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			compatible = "arm,cortex-a72";
			device_type = "cpu";
			enable-method = "psci";
			operating-points-v2 = <&cpu_opp_table>;
			reg = <0>;
			cpu-idle-states = <&CPU_SLEEP_0>;
		};

		cpu1: cpu@1 {
			compatible = "arm,cortex-a72";
			device_type = "cpu";
			enable-method = "psci";
			operating-points-v2 = <&cpu_opp_table>;
			reg = <1>;
			cpu-idle-states = <&CPU_SLEEP_0>;
		};

		idle-states {
			entry-method = "psci";

			CPU_SLEEP_0: cpu-sleep-0 {
				compatible = "arm,idle-state";
				arm,psci-suspend-param = <0x40000000>;
				local-timer-stop;
				entry-latency-us = <300>;
				exit-latency-us = <600>;
				min-residency-us = <10000>;
			};
		};
	};

	cpu_opp_table: opp-table-cpu {
		compatible = "operating-points-v2";
		opp-shared;
		opp00 {
			opp-hz = /bits/ 64 <1199999988>;
			opp-microvolt = <1000000>;
			clock-latency-ns = <500000>;
		};
		opp01 {
			opp-hz = /bits/ 64 <599999994>;
			opp-microvolt = <1000000>;
			clock-latency-ns = <500000>;
		};
		opp02 {
			opp-hz = /bits/ 64 <399999996>;
			opp-microvolt = <1000000>;
			clock-latency-ns = <500000>;
		};
		opp03 {
			opp-hz = /bits/ 64 <299999997>;
			opp-microvolt = <1000000>;
			clock-latency-ns = <500000>;
		};
	};

	dcc: dcc {
		compatible = "arm,dcc";
		status = "disabled";
		bootph-all;
	};

	fpga: fpga {
		compatible = "fpga-region";
		fpga-mgr = <&versal_fpga>;
		#address-cells = <2>;
		#size-cells = <2>;
	};

	psci: psci {
		compatible = "arm,psci-0.2";
		method = "smc";
	};

	pmu {
		compatible = "arm,armv8-pmuv3";
		interrupt-parent = <&gic>;
		interrupts = <1 7 0x304>;
	};

	timer: timer {
		compatible = "arm,armv8-timer";
		interrupt-parent = <&gic>;
		interrupts = <1 13 4>,
			     <1 14 4>,
			     <1 11 4>,
			     <1 10 4>;
	};

	versal_fpga: versal-fpga {
		compatible = "xlnx,versal-fpga";
	};

	amba: axi {
		compatible = "simple-bus";
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;
		interrupt-parent = <&gic>;
		bootph-all;

		gic: interrupt-controller@f9000000 {
			compatible = "arm,gic-v3";
			#interrupt-cells = <3>;
			#address-cells = <2>;
			#size-cells = <2>;
			ranges;
			reg = <0 0xf9000000 0 0x80000>, /* GICD */
			      <0 0xf9080000 0 0x80000>; /* GICR */
			interrupt-controller;
			interrupts = <1 9 4>;

			gic_its: msi-controller@f9020000 {
				compatible = "arm,gic-v3-its";
				status = "disabled";
				msi-controller;
				#msi-cells = <1>;
				reg = <0 0xf9020000 0 0x20000>;
			};
		};

		can0: can@ff060000 {
			compatible = "xlnx,canfd-2.0";
			status = "disabled";
			reg = <0 0xff060000 0 0x6000>;
			interrupts = <0 20 4>;
			clock-names = "can_clk", "s_axi_aclk";
			rx-fifo-depth = <0x40>;
			tx-mailbox-count = <0x20>;
		};

		can1: can@ff070000 {
			compatible = "xlnx,canfd-2.0";
			status = "disabled";
			reg = <0 0xff070000 0 0x6000>;
			interrupts = <0 21 4>;
			clock-names = "can_clk", "s_axi_aclk";
			rx-fifo-depth = <0x40>;
			tx-mailbox-count = <0x20>;
		};

		cci: cci@fd000000 {
			compatible = "arm,cci-500";
			status = "disabled";
			reg = <0 0xfd000000 0 0x10000>;
			ranges = <0 0 0xfd000000 0xa0000>;
			#address-cells = <1>;
			#size-cells = <1>;
			cci_pmu: pmu@10000 {
				compatible = "arm,cci-500-pmu,r0";
				reg = <0x10000 0x90000>;
				interrupts = <0 106 4>,
					     <0 106 4>,
					     <0 106 4>,
					     <0 106 4>,
					     <0 106 4>,
					     <0 106 4>,
					     <0 106 4>,
					     <0 106 4>;
			};
		};

		lpd_dma_chan0: dma-controller@ffa80000 {
			compatible = "xlnx,zynqmp-dma-1.0";
			status = "disabled";
			reg = <0 0xffa80000 0 0x1000>;
			interrupts = <0 60 4>;
			clock-names = "clk_main", "clk_apb";
			/* iommus = <&smmu 0x210>; */
			#dma-cells = <1>;
			xlnx,bus-width = <64>;
			/* dma-coherent; */
		};

		lpd_dma_chan1: dma-controller@ffa90000 {
			compatible = "xlnx,zynqmp-dma-1.0";
			status = "disabled";
			reg = <0 0xffa90000 0 0x1000>;
			interrupts = <0 61 4>;
			clock-names = "clk_main", "clk_apb";
			/* iommus = <&smmu 0x212>; */
			#dma-cells = <1>;
			xlnx,bus-width = <64>;
			/* dma-coherent; */
		};

		lpd_dma_chan2: dma-controller@ffaa0000 {
			compatible = "xlnx,zynqmp-dma-1.0";
			status = "disabled";
			reg = <0 0xffaa0000 0 0x1000>;
			interrupts = <0 62 4>;
			clock-names = "clk_main", "clk_apb";
			/* iommus = <&smmu 0x214>; */
			#dma-cells = <1>;
			xlnx,bus-width = <64>;
			/* dma-coherent; */
		};

		lpd_dma_chan3: dma-controller@ffab0000 {
			compatible = "xlnx,zynqmp-dma-1.0";
			status = "disabled";
			reg = <0 0xffab0000 0 0x1000>;
			interrupts = <0 63 4>;
			clock-names = "clk_main", "clk_apb";
			/* iommus = <&smmu 0x216>; */
			#dma-cells = <1>;
			xlnx,bus-width = <64>;
			/* dma-coherent; */
		};

		lpd_dma_chan4: dma-controller@ffac0000 {
			compatible = "xlnx,zynqmp-dma-1.0";
			status = "disabled";
			reg = <0 0xffac0000 0 0x1000>;
			interrupts = <0 64 4>;
			clock-names = "clk_main", "clk_apb";
			/* iommus = <&smmu 0x218>; */
			#dma-cells = <1>;
			xlnx,bus-width = <64>;
			/* dma-coherent; */
		};

		lpd_dma_chan5: dma-controller@ffad0000 {
			compatible = "xlnx,zynqmp-dma-1.0";
			status = "disabled";
			reg = <0 0xffad0000 0 0x1000>;
			interrupts = <0 65 4>;
			clock-names = "clk_main", "clk_apb";
			/* iommus = <&smmu 0x21a>; */
			#dma-cells = <1>;
			xlnx,bus-width = <64>;
			/* dma-coherent; */
		};

		lpd_dma_chan6: dma-controller@ffae0000 {
			compatible = "xlnx,zynqmp-dma-1.0";
			status = "disabled";
			reg = <0 0xffae0000 0 0x1000>;
			interrupts = <0 66 4>;
			clock-names = "clk_main", "clk_apb";
			/* iommus = <&smmu 0x21c>; */
			#dma-cells = <1>;
			xlnx,bus-width = <64>;
			/* dma-coherent; */
		};

		lpd_dma_chan7: dma-controller@ffaf0000 {
			compatible = "xlnx,zynqmp-dma-1.0";
			status = "disabled";
			reg = <0 0xffaf0000 0 0x1000>;
			interrupts = <0 67 4>;
			clock-names = "clk_main", "clk_apb";
			/* iommus = <&smmu 0x21e>; */
			#dma-cells = <1>;
			xlnx,bus-width = <64>;
			/* dma-coherent; */
		};

		gem0: ethernet@ff0c0000 {
			compatible = "xlnx,versal-gem", "cdns,gem";
			status = "disabled";
			reg = <0 0xff0c0000 0 0x1000>;
			interrupts = <0 56 4>, <0 56 4>;
			clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
			/* iommus = <&smmu 0x234>; */
			/* dma-coherent; */
			#address-cells = <1>;
			#size-cells = <0>;
		};

		gem1: ethernet@ff0d0000 {
			compatible = "xlnx,versal-gem", "cdns,gem";
			status = "disabled";
			reg = <0 0xff0d0000 0 0x1000>;
			interrupts = <0 58 4>, <0 58 4>;
			clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
			/* iommus = <&smmu 0x235>; */
			/* dma-coherent; */
			#address-cells = <1>;
			#size-cells = <0>;
		};

		gpio0: gpio@ff0b0000 {
			compatible = "xlnx,versal-gpio-1.0";
			status = "disabled";
			reg = <0 0xff0b0000 0 0x1000>;
			interrupts = <0 13 4>;
			#gpio-cells = <2>;
			gpio-controller;
			#interrupt-cells = <2>;
			interrupt-controller;
		};

		gpio1: gpio@f1020000 {
			compatible = "xlnx,pmc-gpio-1.0";
			status = "disabled";
			reg = <0 0xf1020000 0 0x1000>;
			interrupts = <0 122 4>;
			#gpio-cells = <2>;
			gpio-controller;
			#interrupt-cells = <2>;
			interrupt-controller;
		};

		i2c0: i2c@ff020000 {
			compatible = "cdns,i2c-r1p14";
			status = "disabled";
			reg = <0 0xff020000 0 0x1000>;
			interrupts = <0 14 4>;
			clock-frequency = <100000>;
			#address-cells = <1>;
			#size-cells = <0>;
		};

		i2c1: i2c@ff030000 {
			compatible = "cdns,i2c-r1p14";
			status = "disabled";
			reg = <0 0xff030000 0 0x1000>;
			interrupts = <0 15 4>;
			clock-frequency = <100000>;
			#address-cells = <1>;
			#size-cells = <0>;
		};

		i2c2: i2c@f1000000 {
			compatible = "cdns,i2c-r1p14";
			status = "disabled";
			reg = <0 0xf1000000 0 0x1000>;
			interrupts = <0 123 4>;
			clock-frequency = <100000>;
			#address-cells = <1>;
			#size-cells = <0>;
		};

		mc0: memory-controller@f6150000	{
			compatible = "xlnx,versal-ddrmc";
			status = "disabled";
			reg = <0x0 0xf6150000 0x0 0x2000>, <0x0 0xf6070000 0x0 0x20000>;
			reg-names = "base", "noc";
			interrupts = <0 147 4>;
		};

		mc1: memory-controller@f62c0000 {
			compatible = "xlnx,versal-ddrmc";
			status = "disabled";
			reg = <0x0 0xf62c0000 0x0 0x2000>, <0x0 0xf6210000 0x0 0x20000>;
			reg-names = "base", "noc";
			interrupts = <0 147 4>;
		};

		mc2: memory-controller@f6430000 {
			compatible = "xlnx,versal-ddrmc";
			status = "disabled";
			reg = <0x0 0xf6430000 0x0 0x2000>, <0x0 0xf6380000 0x0 0x20000>;
			reg-names = "base", "noc";
			interrupts = <0 147 4>;
		};

		mc3: memory-controller@f65a0000 {
			compatible = "xlnx,versal-ddrmc";
			status = "disabled";
			reg = <0x0 0xf65a0000 0x0 0x2000>, <0x0 0xf64f0000 0x0 0x20000>;
			reg-names = "base", "noc";
			interrupts = <0 147 4>;
		};

		ocm: memory-controller@ff960000 {
			compatible = "xlnx,zynqmp-ocmc-1.0";
			reg = <0x0 0xff960000 0x0 0x1000>;
			interrupts = <0 10 4>;
		};

		rtc: rtc@f12a0000 {
			compatible = "xlnx,zynqmp-rtc";
			status = "disabled";
			reg = <0 0xf12a0000 0 0x100>;
			interrupt-names = "alarm", "sec";
			interrupts = <0 142 4>, <0 143 4>;
			calibration = <0x7FFF>;
		};

		sdhci0: mmc@f1040000 {
			compatible = "xlnx,versal-8.9a", "arasan,sdhci-8.9a";
			status = "disabled";
			reg = <0 0xf1040000 0 0x10000>;
			interrupts = <0 126 4>;
			clock-names = "clk_xin", "clk_ahb", "gate";
			#clock-cells = <1>;
			clock-output-names = "clk_out_sd0", "clk_in_sd0";
			/* iommus = <&smmu 0x242>; */
			/* dma-coherent; */
		};

		sdhci1: mmc@f1050000 {
			compatible = "xlnx,versal-8.9a", "arasan,sdhci-8.9a";
			status = "disabled";
			reg = <0 0xf1050000 0 0x10000>;
			interrupts = <0 128 4>;
			clock-names = "clk_xin", "clk_ahb", "gate";
			#clock-cells = <1>;
			clock-output-names = "clk_out_sd1", "clk_in_sd1";
			/* iommus = <&smmu 0x243>; */
			/* dma-coherent; */
		};

		serial0: serial@ff000000 {
			compatible = "arm,pl011", "arm,primecell";
			status = "disabled";
			reg = <0 0xff000000 0 0x1000>;
			interrupts = <0 18 4>;
			reg-io-width = <4>;
			clock-names = "uartclk", "apb_pclk";
			current-speed = <115200>;
			bootph-all;
		};

		serial1: serial@ff010000 {
			compatible = "arm,pl011", "arm,primecell";
			status = "disabled";
			reg = <0 0xff010000 0 0x1000>;
			interrupts = <0 19 4>;
			reg-io-width = <4>;
			clock-names = "uartclk", "apb_pclk";
			current-speed = <115200>;
			bootph-all;
		};

		smmu: iommu@fd800000 {
			compatible = "arm,mmu-500";
			status = "disabled";
			reg = <0 0xfd800000 0 0x40000>;
			stream-match-mask = <0x7c00>;
			#iommu-cells = <1>;
			#global-interrupts = <1>;
			interrupts = <0 107 4>,
				     <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,
				     <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,
				     <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,
				     <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,
				     <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,
				     <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,
				     <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,
				     <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>;
		};

		ospi: spi@f1010000 {
			compatible = "xlnx,versal-ospi-1.0", "cadence,qspi", "cdns,qspi-nor";
			status = "disabled";
			reg = <0 0xf1010000 0 0x10000 0 0xc0000000 0 0x20000000>;
			interrupts = <0 124 4>;
			cdns,fifo-depth = <256>;
			cdns,fifo-width = <4>;
			cdns,is-dma = <1>;
			cdns,trigger-address = <0xC0000000>;
			#address-cells = <1>;
			#size-cells = <0>;
		};

		qspi: spi@f1030000 {
			compatible = "xlnx,versal-qspi-1.0";
			status = "disabled";
			reg = <0 0xf1030000 0 0x1000>;
			interrupts = <0 125 4>;
			clock-names = "ref_clk", "pclk";
			/* iommus = <&smmu 0x244>; */
			/* dma-coherent; */
			#address-cells = <1>;
			#size-cells = <0>;
		};

		spi0: spi@ff040000 {
			compatible = "cdns,spi-r1p6";
			status = "disabled";
			reg = <0 0xff040000 0 0x1000>;
			interrupts = <0 16 4>;
			clock-names = "ref_clk", "pclk";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		spi1: spi@ff050000 {
			compatible = "cdns,spi-r1p6";
			status = "disabled";
			reg = <0 0xff050000 0 0x1000>;
			interrupts = <0 17 4>;
			clock-names = "ref_clk", "pclk";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		sysmon0: sysmon@f1270000 {
			compatible = "xlnx,versal-sysmon";
			reg = <0x0 0xf1270000 0x0 0x4000>;
			interrupts = <0 144 4>;
			xlnx,numchannels = /bits/8 <0>;
		};

		sysmon1: sysmon@109270000 {
			compatible = "xlnx,versal-sysmon";
			#address-cells = <2>;
			#size-cells = <2>;
			status = "disabled";
			reg = <0x1 0x09270000 0x0 0x4000>;
			xlnx,numchannels = /bits/8 <0>;
		};

		sysmon2: sysmon@111270000 {
			compatible = "xlnx,versal-sysmon";
			status = "disabled";
			#address-cells = <2>;
			#size-cells = <2>;
			reg = <0x1 0x11270000 0x0 0x4000>;
			xlnx,numchannels = /bits/8 <0>;
		};

		sysmon3: sysmon@119270000 {
			compatible = "xlnx,versal-sysmon";
			status = "disabled";
			#address-cells = <2>;
			#size-cells = <2>;
			reg = <0x1 0x19270000 0x0 0x4000>;
			xlnx,numchannels = /bits/8 <0>;
		};

		ttc0: timer@ff0e0000 {
			compatible = "cdns,ttc";
			status = "disabled";
			interrupts = <0 37 4>, <0 38 4>, <0 39 4>;
			reg = <0x0 0xff0e0000 0x0 0x1000>;
			timer-width = <32>;
		};

		ttc1: timer@ff0f0000 {
			compatible = "cdns,ttc";
			status = "disabled";
			interrupts = <0 40 4>, <0 41 4>, <0 42 4>;
			reg = <0x0 0xff0f0000 0x0 0x1000>;
			timer-width = <32>;
		};

		ttc2: timer@ff100000 {
			compatible = "cdns,ttc";
			status = "disabled";
			interrupts = <0 43 4>, <0 44 4>, <0 45 4>;
			reg = <0x0 0xff100000 0x0 0x1000>;
			timer-width = <32>;
		};

		ttc3: timer@ff110000 {
			compatible = "cdns,ttc";
			status = "disabled";
			interrupts = <0 46 4>, <0 47 4>, <0 48 4>;
			reg = <0x0 0xff110000 0x0 0x1000>;
			timer-width = <32>;
		};

		usb0: usb@ff9d0000 {
			compatible = "xlnx,versal-dwc3";
			status = "disabled";
			reg = <0 0xff9d0000 0 0x100>;
			clock-names = "bus_clk", "ref_clk";
			ranges;
			#address-cells = <2>;
			#size-cells = <2>;

			dwc3_0: usb@fe200000 {
				compatible = "snps,dwc3";
				status = "disabled";
				reg = <0 0xfe200000 0 0x10000>;
				interrupt-names = "host", "peripheral", "otg", "wakeup";
				interrupts = <0 0x16 4>, <0 0x16 4>, <0 0x1a 4>, <0x0 0x4a 0x4>;
				/* iommus = <&smmu 0x230>; */
				snps,dis_u2_susphy_quirk;
				snps,dis_u3_susphy_quirk;
				snps,quirk-frame-length-adjustment = <0x20>;
				clock-names = "ref";
				/* dma-coherent; */
			};
		};

		cpm_pciea: pci@fca10000 {
			device_type = "pci";
			#address-cells = <3>;
			#interrupt-cells = <1>;
			#size-cells = <2>;
			compatible = "xlnx,versal-cpm-host-1.00";
			status = "disabled";
			interrupt-map = <0 0 0 1 &pcie_intc_0 0>,
					<0 0 0 2 &pcie_intc_0 1>,
					<0 0 0 3 &pcie_intc_0 2>,
					<0 0 0 4 &pcie_intc_0 3>;
			interrupt-map-mask = <0 0 0 7>;
			interrupt-names = "misc";
			interrupts = <0 72 4>;
			interrupt-parent = <&gic>;
			bus-range = <0x00 0xff>;
			ranges = <0x02000000 0x00000000 0xe0000000 0x0 0xe0000000 0x00000000 0x10000000>,
				 <0x43000000 0x00000080 0x00000000 0x00000080 0x00000000 0x00000000 0x80000000>;
			msi-map = <0x0 &gic_its 0x0 0x10000>;
			reg = <0x0 0xfca10000 0x0 0x1000>,
			      <0x6 0x00000000 0x0 0x1000000>;
			reg-names = "cpm_slcr", "cfg";
			pcie_intc_0: interrupt-controller {
				#address-cells = <0>;
				#interrupt-cells = <1>;
				interrupt-controller ;
			};
		};

		cpm5_pcie: pcie@fcdd0000 {
			device_type = "pci";
			#address-cells = <3>;
			#interrupt-cells = <1>;
			#size-cells = <2>;
			compatible = "xlnx,versal-cpm5-host";
			status = "disabled";
			interrupt-map = <0 0 0 1 &pcie_intc_1 0>,
					<0 0 0 2 &pcie_intc_1 1>,
					<0 0 0 3 &pcie_intc_1 2>,
					<0 0 0 4 &pcie_intc_1 3>;
			interrupt-map-mask = <0 0 0 7>;
			interrupt-names = "misc";
			interrupts = <0 72 4>;
			interrupt-parent = <&gic>;
			bus-range = <0x00 0xff>;
			ranges = <0x02000000 0x0 0xe0000000 0x0 0xe0000000 0x0 0x10000000>,
				 <0x43000000 0x80 0x00000000 0x80 0x00000000 0x0 0x80000000>;
			msi-map = <0x0 &gic_its 0x0 0x10000>;
			reg = <0x00 0xfcdd0000 0x00 0x1000>,
			      <0x06 0x00000000 0x00 0x1000000>,
			      <0x00 0xfce20000 0x00 0x1000000>;
			reg-names = "cpm_slcr", "cfg", "cpm_csr";
			pcie_intc_1: interrupt-controller {
				#address-cells = <0>;
				#interrupt-cells = <1>;
				interrupt-controller;
			};
		};

		watchdog: watchdog@fd4d0000 {
			compatible = "xlnx,versal-wwdt";
			status = "disabled";
			reg = <0 0xfd4d0000 0 0x10000>;
			timeout-sec = <30>;
		};

		watchdog1: watchdog@ff120000 {
			compatible = "xlnx,versal-wwdt";
			status = "disabled";
			reg = <0 0xff120000 0 0x10000>;
			timeout-sec = <30>;
		};

		xilsem_edac: edac@f2014050 {
			compatible = "xlnx,versal-xilsem-edac";
			status = "disabled";
			reg = <0x0 0xf2014050 0x0 0xc4>;
		};
	};
};