/
xlnx,dp-tx.yaml
225 lines (187 loc) · 5.79 KB
/
xlnx,dp-tx.yaml
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/xlnx/xlnx,dp-tx.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Xilinx DisplayPort Transmitter Subsystem
maintainers:
- Rajesh Gugulothu <gugulothu.rajesh@xilinx.com>
description: |
The Xilinx DisplayPort Tx Subsystem contains several subcores to implement
a DisplayPort Transmitter and outputs video data using DisplayPort protocol.
For more details, please refer to PG199 at
https://www.xilinx.com/support/documentation/ip_documentation/dp_tx_subsystem/v2_1/pg199-displayport-tx-subsystem.pdf
properties:
compatible:
enum:
- xlnx,v-dp-txss-3.0
- xlnx,v-dp-txss-3.1
reg:
maxItems: 2
description: DisplayPort Transmitter Subsystem registers
reg-names:
items:
- const: dp_base
- const: gt_quad_base
interrupts:
minItems: 1
maxItems: 4
interrupt-names:
description: Only dptxss_dp_irq is mandatory. Others are optional.
dptxss_timer_irq will be present when HDCP 1x or 2x is selected.
dptxss_hdcp_irq will be present when HDCP 1x is selected.
dptxss_hdcp22_cipher_irq will be present when HDCP 2x is selected.
items:
- const: dptxss_dp_irq
- const: dptxss_timer_irq
- const: dptxss_hdcp_irq
- const: dptxss_hdcp22_cipher_irq
clocks:
description: List of clock specifiers
items:
- description: AXI Lite clock
- description: Video clock
clock-names:
items:
- const: s_axi_aclk
- const: tx_vid_clk
phys:
description: This denotes phandles for phy lanes registered
for DP protocol.DisplayPort always require 4 lanes
phy-names:
items:
- const: dp-phy0
- const: dp-phy1
- const: dp-phy2
- const: dp-phy3
xlnx,vtc-offset:
description: This denotes register offset address of VTC sub-core of
DisplayPort Transmitter Subsystem.
allOf:
- $ref: /schemas/types.yaml#/definitions/uint32
xlnx,max-lanes:
description: Max number of lanes that IP configured with.
Possible values are 1, 2, 4.
allOf:
- $ref: /schemas/types.yaml#/definitions/uint32
- enum: [1, 2, 4]
xlnx,max-link-rate:
description: |
Max link rate that IP configured with.Possible values are as below -
162000 - 1.6 Gb/s
270000 - 2.7 Gb/s
540000 - 5.4 Gb/s
810000 - 8.1 Gb/s
allOf:
- $ref: /schemas/types.yaml#/definitions/uint32
- enum: [162000, 270000, 540000, 810000]
xlnx,bpc:
description: |
Max BPC value that IP configured with. For example if IP is configured
with 10 BPC means it supports (6, 8, 10) up to 10bpc.
Possible values are 6, 8, 10, 12, 16.
allOf:
- $ref: /schemas/types.yaml#/definitions/uint32
- enum: [6, 8, 10, 12, 16]
xlnx,audio-channels:
description: |
This denotes number of audio channels enabled in the IP
configuration. Possible values are 2, 3, 4, 5, 6, 7, 8.
allOf:
- $ref: /schemas/types.yaml#/definitions/uint32
- enum: [2, 3, 4, 5, 6, 7, 8]
xlnx,hdcp22-enable:
type: boolean
description: |
Present when HDCP2.2 is present in design.
xlnx,hdcp-enable:
type: boolean
description: |
Present when HDCP1.4 is present in design.
xlnx,versal-gt:
type: boolean
description: |
Boolean property present when versal GT is present in design.
xlnx,xilinx-vfmc:
description: phandle of xilinx video FMC node
$ref: /schemas/types.yaml#/definitions/phandle
ports:
type: object
properties:
port@0:
type: object
description: |
Output / source port node, endpoint describing modules
connected the DisplayPort transmitter
properties:
reg:
const: 0
endpoint:
type: object
properties:
remote-endpoint: true
required:
- remote-endpoint
additionalProperties: false
additionalProperties: false
required:
- compatible
- reg
- reg-names
- interrupts
- clocks
- clock-names
- xlnx,max-link-rate
- xlnx,bpc
- xlnx,max-lanes
- phy-names
- phys
- ports
additionalProperties: false
if:
properties:
compatible:
contains:
const: xlnx,v-dp-txss-3.1
then:
required:
- xlnx,vtc-offset
examples:
- |
bus {
#address-cells = <2>;
#size-cells = <2>;
v_dp_txss1@a0100000 {
compatible = "xlnx,v-dp-txss-3.1";
reg = <0x0 0xa0100000 0x0 0x40000>, <0x0 0xa4080000 0x0 0x10000>;
reg-names = "dp_base", "gt_quad_base";
clock-names = "s_axi_aclk", "tx_vid_clk";
clocks = <&zynqmp_clk 71>, <&si570_1>;
interrupt-names = "dptxss_dp_irq", "dptxss_timer_irq", "dptxss_hdcp_irq",
"dptxss_hdcp22_cipher_irq";
interrupts = <0 92 4>, <0 108 4>, <0 111 4>, <0 109 4>;
xlnx,vtc-offset = <0x8000>;
xlnx,max-lanes = <4>;
xlnx,max-link-rate = <810000>;
xlnx,bpc = <8>;
xlnx,audio-channels = <2>;
xlnx,hdcp22-enable;
xlnx,hdcp-enable;
xlnx,versal-gt;
xlnx,xilinx-vfmc = <&xfmc>;
phy-names = "dp-phy0", "dp-phy1", "dp-phy2", "dp-phy3";
phys = <&vphy_lane0 0 1 1 0>, <&vphy_lane1 0 1 1 0>,
<&vphy_lane2 0 1 1 0>, <&vphy_lane3 0 1 1 0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
dp_transmitter: endpoint {
remote-endpoint = <&display_controller>;
};
};
};
};
};
...