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xilinx-ams: Fix UBSan Warning
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The issue was that a 64 bit datatype was being left shifted by
more than 63 bits due to the scan index of the AMS control
channels.

There is no functional need for these control channels to be
included in the scan_mask. This leads to the fix being a
range check on the scan index before shifting.

Addresses-UBSAN: shift-out-of-bounds
Signed-off-by: Conall O'Griofa <conall.o'griofa@xilinx.com>
State: pending
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Conall O'Griofa authored and michalsimek committed May 17, 2022
1 parent 9ef3be1 commit 6084269
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Showing 2 changed files with 4 additions and 1 deletion.
3 changes: 2 additions & 1 deletion drivers/iio/adc/xilinx-ams.c
Expand Up @@ -178,7 +178,8 @@ static void ams_enable_channel_sequence(struct ams *ams)
/* Run calibration of PS & PL as part of the sequence */
scan_mask = 1 | (1 << PS_SEQ_MAX);
for (i = 0; i < indio_dev->num_channels; i++)
scan_mask |= BIT(indio_dev->channels[i].scan_index);
if (indio_dev->channels[i].scan_index < PL_SEQ_MAX)
scan_mask |= BIT(indio_dev->channels[i].scan_index);

if (ams->ps_base) {
/* put sysmon in a soft reset to change the sequence */
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2 changes: 2 additions & 0 deletions drivers/iio/adc/xilinx-ams.h
Expand Up @@ -193,6 +193,8 @@ enum ams_ps_pl_seq {
#define PS_SEQ(x) (x)
#define PL_SEQ(x) (PS_SEQ_MAX + x)

#define PL_SEQ_MAX ((AMS_SEQ_MAX * 2) + 16U) /* PS Slot + PL Slot + 16 VAUX Channels */

#define AMS_CHAN_TEMP(_scan_index, _addr, _ext) { \
.type = IIO_TEMP, \
.indexed = 1, \
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