target/arm: Add freq property to ARMCPU

Add a property to hold the generic timer frequency. Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Xilinx · Sep 11, 2018 · 9e939b5 · 9e939b5
1 parent d6de234
commit 9e939b5
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Showing 3 changed files with 7 additions and 1 deletion.
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
@@ -161,6 +161,9 @@ static void arm_cpu_reset(CPUState *s)
                            PSCI_OFF : PSCI_ON;
     s->halted = cpu->start_powered_off || s->halt_pin || s->arch_halt_pin;
 
+    if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) {
+        cpu->env.cp15.c14_cntfrq = cpu->gt_freq;
+    }
     /* Reset value of SCTLR_V is controlled by input signal VINITHI.  */
     env->cp15.sctlr_ns &= ~SCTLR_V;
     env->cp15.sctlr_s &= ~SCTLR_V;
@@ -1932,6 +1935,7 @@ static Property arm_cpu_properties[] = {
                         mp_affinity, ARM64_AFFINITY_INVALID),
     DEFINE_PROP_INT32("node-id", ARMCPU, node_id, CPU_UNSET_NUMA_NODE_ID),
     DEFINE_PROP_INT32("core-count", ARMCPU, core_count, -1),
+    DEFINE_PROP_UINT64("generic-timer-frequency", ARMCPU, gt_freq, 62500000),
     DEFINE_PROP_END_OF_LIST()
 };
 

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
@@ -658,6 +658,8 @@ struct ARMCPU {
     uint64_t *cpreg_vmstate_values;
     int32_t cpreg_vmstate_array_len;
 
+    /* Generic Timer freqency*/
+    uint64_t gt_freq;
     /* Timers used by the generic (architected) timer */
     QEMUTimer *gt_timer[NUM_GTIMERS];
     /* GPIO outputs for generic timer */

diff --git a/target/arm/helper.c b/target/arm/helper.c
@@ -2056,11 +2056,11 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
       .access = PL1_RW | PL0_R, .accessfn = gt_cntfrq_access,
       .fieldoffset = offsetoflow32(CPUARMState, cp15.c14_cntfrq),
     },
+    /* timer frequency is set by arm_cpu_reset() */
     { .name = "CNTFRQ_EL0", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 0,
       .access = PL1_RW | PL0_R, .accessfn = gt_cntfrq_access,
       .fieldoffset = offsetof(CPUARMState, cp15.c14_cntfrq),
-      .resetvalue = (1000 * 1000 * 1000) / GTIMER_SCALE,
     },
     /* overall control: mostly access permissions */
     { .name = "CNTKCTL", .state = ARM_CP_STATE_BOTH,