/
pack.cc
3119 lines (2938 loc) · 156 KB
/
pack.cc
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/*
* nextpnr -- Next Generation Place and Route
*
* Copyright (C) 2018 David Shah <david@symbioticeda.com>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
#include <algorithm>
#include <boost/optional.hpp>
#include <iterator>
#include <queue>
#include <unordered_set>
#include "cells.h"
#include "chain_utils.h"
#include "design_utils.h"
#include "globals.h"
#include "log.h"
#include "timing.h"
#include "util.h"
NEXTPNR_NAMESPACE_BEGIN
static bool is_nextpnr_iob(Context *ctx, CellInfo *cell)
{
return cell->type == ctx->id("$nextpnr_ibuf") || cell->type == ctx->id("$nextpnr_obuf") ||
cell->type == ctx->id("$nextpnr_iobuf");
}
class Ecp5Packer
{
public:
Ecp5Packer(Context *ctx) : ctx(ctx){};
private:
// Process the contents of packed_cells and new_cells
void flush_cells()
{
for (auto pcell : packed_cells) {
ctx->cells.erase(pcell);
}
for (auto &ncell : new_cells) {
ctx->cells[ncell->name] = std::move(ncell);
}
packed_cells.clear();
new_cells.clear();
}
// Print logic usgage
int available_slices = 0;
void print_logic_usage()
{
int total_luts = 0, total_ffs = 0;
int total_ramluts = 0, total_ramwluts = 0;
for (auto bel : ctx->getBels()) {
if (ctx->getBelType(bel) == id_TRELLIS_SLICE) {
available_slices += 1;
total_luts += 2;
total_ffs += 2;
Loc l = ctx->getBelLocation(bel);
if (l.z == 0 || l.z == 1)
total_ramluts += 2;
if (l.z == 2)
total_ramwluts += 2;
}
}
int used_lgluts = 0, used_cyluts = 0, used_ramluts = 0, used_ramwluts = 0, used_ffs = 0;
for (auto &cell : ctx->cells) {
CellInfo *ci = cell.second.get();
if (is_lut(ctx, ci))
++used_lgluts;
if (is_carry(ctx, ci))
used_cyluts += 2;
if (is_dpram(ctx, ci)) {
used_ramluts += 4;
used_ramwluts += 2;
}
if (is_ff(ctx, ci))
used_ffs += 2;
}
log_info("Logic utilisation before packing:\n");
auto pc = [](int used, int total) { return 100 * used / total; };
int used_luts = used_lgluts + used_cyluts + used_ramluts + used_ramwluts;
log_info(" Total LUT4s: %5d/%5d %5d%%\n", used_luts, total_luts, pc(used_luts, total_luts));
log_info(" logic LUTs: %5d/%5d %5d%%\n", used_lgluts, total_luts, pc(used_lgluts, total_luts));
log_info(" carry LUTs: %5d/%5d %5d%%\n", used_cyluts, total_luts, pc(used_cyluts, total_luts));
log_info(" RAM LUTs: %5d/%5d %5d%%\n", used_ramluts, total_ramluts, pc(used_ramluts, total_ramluts));
log_info(" RAMW LUTs: %5d/%5d %5d%%\n", used_ramwluts, total_ramwluts,
pc(used_ramwluts, total_ramwluts));
log_break();
log_info(" Total DFFs: %5d/%5d %5d%%\n", used_ffs, total_ffs, pc(used_ffs, total_ffs));
log_break();
}
// Find FFs associated with LUTs, or LUT expansion muxes
void find_lutff_pairs()
{
log_info("Finding LUTFF pairs...\n");
for (auto cell : sorted(ctx->cells)) {
CellInfo *ci = cell.second;
if (is_lut(ctx, ci) || is_pfumx(ctx, ci) || is_l6mux(ctx, ci)) {
NetInfo *znet = ci->ports.at(ctx->id("Z")).net;
if (znet != nullptr) {
CellInfo *ff = net_only_drives(ctx, znet, is_ff, ctx->id("DI"), false);
// Can't combine preload FF with LUT due to conflict on M
if (ff != nullptr && get_net_or_empty(ff, ctx->id("M")) == nullptr) {
lutffPairs[ci->name] = ff->name;
fflutPairs[ff->name] = ci->name;
}
}
}
}
}
// Check if a flipflop is available in a slice
bool is_ff_available(CellInfo *slice, int ff)
{
if (get_net_or_empty(slice, (ff == 1) ? id_Q1 : id_Q0) != nullptr)
return false;
if (get_net_or_empty(slice, (ff == 1) ? id_M1 : id_M0) != nullptr)
return false;
return true;
}
// Check if a flipflop can be added to a slice
bool can_add_ff_to_slice(CellInfo *slice, CellInfo *ff)
{
std::string clkmux = str_or_default(ff->params, ctx->id("CLKMUX"), "CLK");
std::string lsrmux = str_or_default(ff->params, ctx->id("LSRMUX"), "LSR");
bool has_dpram = str_or_default(slice->params, ctx->id("MODE"), "LOGIC") == "DPRAM";
if (has_dpram) {
std::string wckmux = str_or_default(slice->params, ctx->id("WCKMUX"), "WCK");
std::string wremux = str_or_default(slice->params, ctx->id("WREMUX"), "WRE");
if (wckmux != clkmux && !(wckmux == "WCK" && clkmux == "CLK"))
return false;
if (wremux != lsrmux && !(wremux == "WRE" && lsrmux == "LSR"))
return false;
}
bool has_ff0 = get_net_or_empty(slice, id_Q0) != nullptr;
bool has_ff1 = get_net_or_empty(slice, id_Q1) != nullptr;
if (!has_ff0 && !has_ff1)
return true;
if (str_or_default(ff->params, ctx->id("GSR"), "DISABLED") !=
str_or_default(slice->params, ctx->id("GSR"), "DISABLED"))
return false;
if (str_or_default(ff->params, ctx->id("SRMODE"), "LSR_OVER_CE") !=
str_or_default(slice->params, ctx->id("SRMODE"), "LSR_OVER_CE"))
return false;
if (str_or_default(ff->params, ctx->id("CEMUX"), "1") != str_or_default(slice->params, ctx->id("CEMUX"), "1"))
return false;
if (str_or_default(ff->params, ctx->id("LSRMUX"), "LSR") !=
str_or_default(slice->params, ctx->id("LSRMUX"), "LSR"))
return false;
if (str_or_default(ff->params, ctx->id("CLKMUX"), "CLK") !=
str_or_default(slice->params, ctx->id("CLKMUX"), "CLK"))
return false;
if (net_or_nullptr(ff, ctx->id("CLK")) != net_or_nullptr(slice, ctx->id("CLK")))
return false;
if (net_or_nullptr(ff, ctx->id("CE")) != net_or_nullptr(slice, ctx->id("CE")))
return false;
if (net_or_nullptr(ff, ctx->id("LSR")) != net_or_nullptr(slice, ctx->id("LSR")))
return false;
return true;
}
const NetInfo *net_or_nullptr(CellInfo *cell, IdString port)
{
auto fnd = cell->ports.find(port);
if (fnd == cell->ports.end())
return nullptr;
else
return fnd->second.net;
}
// Return whether two FFs can be packed together in the same slice
bool can_pack_ffs(CellInfo *ff0, CellInfo *ff1)
{
if (str_or_default(ff0->params, ctx->id("GSR"), "DISABLED") !=
str_or_default(ff1->params, ctx->id("GSR"), "DISABLED"))
return false;
if (str_or_default(ff0->params, ctx->id("SRMODE"), "LSR_OVER_CE") !=
str_or_default(ff1->params, ctx->id("SRMODE"), "LSR_OVER_CE"))
return false;
if (str_or_default(ff0->params, ctx->id("CEMUX"), "1") != str_or_default(ff1->params, ctx->id("CEMUX"), "1"))
return false;
if (str_or_default(ff0->params, ctx->id("LSRMUX"), "LSR") !=
str_or_default(ff1->params, ctx->id("LSRMUX"), "LSR"))
return false;
if (str_or_default(ff0->params, ctx->id("CLKMUX"), "CLK") !=
str_or_default(ff1->params, ctx->id("CLKMUX"), "CLK"))
return false;
if (net_or_nullptr(ff0, ctx->id("CLK")) != net_or_nullptr(ff1, ctx->id("CLK")))
return false;
if (net_or_nullptr(ff0, ctx->id("CE")) != net_or_nullptr(ff1, ctx->id("CE")))
return false;
if (net_or_nullptr(ff0, ctx->id("LSR")) != net_or_nullptr(ff1, ctx->id("LSR")))
return false;
return true;
}
// Return whether or not an FF can be added to a tile (pairing checks must also be done using the fn above)
bool can_add_ff_to_tile(const std::vector<CellInfo *> &tile_ffs, CellInfo *ff0)
{
for (const auto &existing : tile_ffs) {
if (net_or_nullptr(existing, ctx->id("CLK")) != net_or_nullptr(ff0, ctx->id("CLK")))
return false;
if (net_or_nullptr(existing, ctx->id("LSR")) != net_or_nullptr(ff0, ctx->id("LSR")))
return false;
if (str_or_default(existing->params, ctx->id("CLKMUX"), "CLK") !=
str_or_default(ff0->params, ctx->id("CLKMUX"), "CLK"))
return false;
if (str_or_default(existing->params, ctx->id("LSRMUX"), "LSR") !=
str_or_default(ff0->params, ctx->id("LSRMUX"), "LSR"))
return false;
if (str_or_default(existing->params, ctx->id("SRMODE"), "LSR_OVER_CE") !=
str_or_default(ff0->params, ctx->id("SRMODE"), "LSR_OVER_CE"))
return false;
}
return true;
}
// Return true if a FF can be added to a DPRAM slice
bool can_pack_ff_dram(CellInfo *dpram, CellInfo *ff)
{
if (get_net_or_empty(ff, ctx->id("M")) != nullptr)
return false; // skip PRLD FFs due to M/DI conflict
std::string wckmux = str_or_default(dpram->params, ctx->id("WCKMUX"), "WCK");
std::string clkmux = str_or_default(ff->params, ctx->id("CLKMUX"), "CLK");
if (wckmux != clkmux && !(wckmux == "WCK" && clkmux == "CLK"))
return false;
std::string wremux = str_or_default(dpram->params, ctx->id("WREMUX"), "WRE");
std::string lsrmux = str_or_default(ff->params, ctx->id("LSRMUX"), "LSR");
if (wremux != lsrmux && !(wremux == "WRE" && lsrmux == "LSR"))
return false;
return true;
}
// Return true if two LUTs can be paired considering FF compatibility
bool can_pack_lutff(IdString lut0, IdString lut1)
{
auto ff0 = lutffPairs.find(lut0), ff1 = lutffPairs.find(lut1);
if (ff0 != lutffPairs.end() && ff1 != lutffPairs.end()) {
return can_pack_ffs(ctx->cells.at(ff0->second).get(), ctx->cells.at(ff1->second).get());
} else {
return true;
}
}
// Find "closely connected" LUTs and pair them together
void pair_luts()
{
log_info("Finding LUT-LUT pairs...\n");
std::unordered_set<IdString> procdLuts;
for (auto cell : sorted(ctx->cells)) {
CellInfo *ci = cell.second;
if (is_lut(ctx, ci) && procdLuts.find(cell.first) == procdLuts.end()) {
NetInfo *znet = ci->ports.at(ctx->id("Z")).net;
std::vector<NetInfo *> inpnets;
if (znet != nullptr) {
for (auto user : znet->users) {
if (is_lut(ctx, user.cell) && user.cell != ci &&
procdLuts.find(user.cell->name) == procdLuts.end()) {
if (can_pack_lutff(ci->name, user.cell->name)) {
procdLuts.insert(ci->name);
procdLuts.insert(user.cell->name);
lutPairs[ci->name] = user.cell->name;
goto paired;
}
}
}
if (false) {
paired:
continue;
}
}
if (lutffPairs.find(ci->name) != lutffPairs.end()) {
NetInfo *qnet = ctx->cells.at(lutffPairs[ci->name])->ports.at(ctx->id("Q")).net;
if (qnet != nullptr) {
for (auto user : qnet->users) {
if (is_lut(ctx, user.cell) && user.cell != ci &&
procdLuts.find(user.cell->name) == procdLuts.end()) {
if (can_pack_lutff(ci->name, user.cell->name)) {
procdLuts.insert(ci->name);
procdLuts.insert(user.cell->name);
lutPairs[ci->name] = user.cell->name;
goto paired_ff;
}
}
}
if (false) {
paired_ff:
continue;
}
}
}
for (const char *inp : {"A", "B", "C", "D"}) {
if (!ci->ports.count(ctx->id(inp)))
continue;
NetInfo *innet = ci->ports.at(ctx->id(inp)).net;
if (innet != nullptr && innet->driver.cell != nullptr) {
CellInfo *drv = innet->driver.cell;
if (is_lut(ctx, drv) && drv != ci && innet->driver.port == ctx->id("Z")) {
if (procdLuts.find(drv->name) == procdLuts.end()) {
if (can_pack_lutff(ci->name, drv->name)) {
procdLuts.insert(ci->name);
procdLuts.insert(drv->name);
lutPairs[ci->name] = drv->name;
goto paired_inlut;
}
}
} else if (is_ff(ctx, drv) && innet->driver.port == ctx->id("Q")) {
auto fflut = fflutPairs.find(drv->name);
if (fflut != fflutPairs.end() && fflut->second != ci->name &&
procdLuts.find(fflut->second) == procdLuts.end()) {
if (can_pack_lutff(ci->name, fflut->second)) {
procdLuts.insert(ci->name);
procdLuts.insert(fflut->second);
lutPairs[ci->name] = fflut->second;
goto paired_inlut;
}
}
}
}
}
// Pack LUTs feeding the same CCU2, RAM or DFF into a SLICE
if (znet != nullptr && znet->users.size() < 10) {
for (auto user : znet->users) {
if (is_lc(ctx, user.cell) || user.cell->type == ctx->id("DP16KD") || is_ff(ctx, user.cell)) {
for (auto port : user.cell->ports) {
if (port.second.type != PORT_IN || port.second.net == nullptr ||
port.second.net == znet)
continue;
if (port.second.net->users.size() > 10)
continue;
CellInfo *drv = port.second.net->driver.cell;
if (drv == nullptr)
continue;
if (is_lut(ctx, drv) && !procdLuts.count(drv->name) &&
can_pack_lutff(ci->name, drv->name)) {
procdLuts.insert(ci->name);
procdLuts.insert(drv->name);
lutPairs[ci->name] = drv->name;
goto paired_inlut;
}
}
}
}
}
// Pack LUTs sharing an input with a simple fanout-based heuristic
for (const char *inp : {"A", "B", "C", "D"}) {
if (!ci->ports.count(ctx->id(inp)))
continue;
NetInfo *innet = ci->ports.at(ctx->id(inp)).net;
if (innet != nullptr && innet->users.size() < 5 && innet->users.size() > 1)
inpnets.push_back(innet);
}
std::sort(inpnets.begin(), inpnets.end(),
[&](const NetInfo *a, const NetInfo *b) { return a->users.size() < b->users.size(); });
for (auto inet : inpnets) {
for (auto &user : inet->users) {
if (user.cell == nullptr || user.cell == ci || !is_lut(ctx, user.cell))
continue;
if (procdLuts.count(user.cell->name))
continue;
if (can_pack_lutff(ci->name, user.cell->name)) {
procdLuts.insert(ci->name);
procdLuts.insert(user.cell->name);
lutPairs[ci->name] = user.cell->name;
goto paired_inlut;
}
}
}
if (false) {
paired_inlut:
continue;
}
}
}
if (ctx->debug) {
log_info("Singleton LUTs (packer QoR debug): \n");
for (auto cell : sorted(ctx->cells))
if (is_lut(ctx, cell.second) && !procdLuts.count(cell.first))
log_info(" %s\n", cell.first.c_str(ctx));
}
}
// Return true if an port is a top level port that provides its own IOBUF
bool is_top_port(PortRef &port)
{
if (port.cell == nullptr)
return false;
if (port.cell->type == id_DCUA) {
return port.port == id_CH0_HDINP || port.port == id_CH0_HDINN || port.port == id_CH0_HDOUTP ||
port.port == id_CH0_HDOUTN || port.port == id_CH1_HDINP || port.port == id_CH1_HDINN ||
port.port == id_CH1_HDOUTP || port.port == id_CH1_HDOUTN;
} else if (port.cell->type == id_EXTREFB) {
return port.port == id_REFCLKP || port.port == id_REFCLKN;
} else {
return false;
}
}
// Return true if a net only drives a top port
bool drives_top_port(NetInfo *net, PortRef &tp)
{
if (net == nullptr)
return false;
for (auto user : net->users) {
if (is_top_port(user)) {
if (net->users.size() > 1)
log_error(" port %s.%s must be connected to (and only to) a top level pin\n",
user.cell->name.c_str(ctx), user.port.c_str(ctx));
tp = user;
return true;
}
}
if (net->driver.cell != nullptr && is_top_port(net->driver)) {
if (net->users.size() > 1)
log_error(" port %s.%s must be connected to (and only to) a top level pin\n",
net->driver.cell->name.c_str(ctx), net->driver.port.c_str(ctx));
tp = net->driver;
return true;
}
return false;
}
// Simple "packer" to remove nextpnr IOBUFs, this assumes IOBUFs are manually instantiated
void pack_io()
{
log_info("Packing IOs..\n");
for (auto cell : sorted(ctx->cells)) {
CellInfo *ci = cell.second;
if (is_nextpnr_iob(ctx, ci)) {
CellInfo *trio = nullptr;
NetInfo *ionet = nullptr;
PortRef tp;
if (ci->type == ctx->id("$nextpnr_ibuf") || ci->type == ctx->id("$nextpnr_iobuf")) {
ionet = ci->ports.at(ctx->id("O")).net;
trio = net_only_drives(ctx, ionet, is_trellis_io, ctx->id("B"), true, ci);
} else if (ci->type == ctx->id("$nextpnr_obuf")) {
ionet = ci->ports.at(ctx->id("I")).net;
trio = net_only_drives(ctx, ci->ports.at(ctx->id("I")).net, is_trellis_io, ctx->id("B"), true, ci);
}
if (bool_or_default(ctx->settings, ctx->id("arch.ooc"))) {
// No IO buffer insertion in out-of-context mode, just remove the nextpnr buffer
// and leave the top level port
for (auto &port : ci->ports)
disconnect_port(ctx, ci, port.first);
} else if (trio != nullptr) {
// Trivial case, TRELLIS_IO used. Just remove the IOBUF
log_info("%s feeds TRELLIS_IO %s, removing %s %s.\n", ci->name.c_str(ctx), trio->name.c_str(ctx),
ci->type.c_str(ctx), ci->name.c_str(ctx));
NetInfo *net = trio->ports.at(ctx->id("B")).net;
if (((ci->type == ctx->id("$nextpnr_ibuf") || ci->type == ctx->id("$nextpnr_iobuf")) &&
net->users.size() > 1) ||
(ci->type == ctx->id("$nextpnr_obuf") &&
(net->users.size() > 2 || net->driver.cell != nullptr)) ||
(ci->type == ctx->id("$nextpnr_iobuf") && ci->ports.at(ctx->id("I")).net != nullptr &&
ci->ports.at(ctx->id("I")).net->driver.cell != nullptr))
log_error("Pin B of %s '%s' connected to more than a single top level IO.\n",
trio->type.c_str(ctx), trio->name.c_str(ctx));
if (net != nullptr) {
if (net->clkconstr != nullptr && trio->ports.count(ctx->id("O"))) {
NetInfo *onet = trio->ports.at(ctx->id("O")).net;
if (onet != nullptr && !onet->clkconstr) {
// Move clock constraint from IO pad to input buffer output
std::swap(net->clkconstr, onet->clkconstr);
}
}
}
} else if (drives_top_port(ionet, tp)) {
log_info("%s feeds %s %s.%s, removing %s %s.\n", ci->name.c_str(ctx), tp.cell->type.c_str(ctx),
tp.cell->name.c_str(ctx), tp.port.c_str(ctx), ci->type.c_str(ctx), ci->name.c_str(ctx));
if (ionet != nullptr) {
ctx->nets.erase(ionet->name);
tp.cell->ports.at(tp.port).net = nullptr;
}
if (ci->type == ctx->id("$nextpnr_iobuf")) {
NetInfo *net2 = ci->ports.at(ctx->id("I")).net;
if (net2 != nullptr) {
ctx->nets.erase(net2->name);
}
}
} else {
// Create a TRELLIS_IO buffer
std::unique_ptr<CellInfo> tr_cell =
create_ecp5_cell(ctx, ctx->id("TRELLIS_IO"), ci->name.str(ctx) + "$tr_io");
nxio_to_tr(ctx, ci, tr_cell.get(), new_cells, packed_cells);
new_cells.push_back(std::move(tr_cell));
trio = new_cells.back().get();
}
for (auto port : ci->ports)
disconnect_port(ctx, ci, port.first);
packed_cells.insert(ci->name);
if (trio != nullptr) {
for (const auto &attr : ci->attrs)
trio->attrs[attr.first] = attr.second;
auto loc_attr = trio->attrs.find(ctx->id("LOC"));
if (loc_attr != trio->attrs.end()) {
std::string pin = loc_attr->second.as_string();
BelId pinBel = ctx->getPackagePinBel(pin);
if (pinBel == BelId()) {
log_error("IO pin '%s' constrained to pin '%s', which does not exist for package '%s'.\n",
trio->name.c_str(ctx), pin.c_str(), ctx->args.package.c_str());
} else {
log_info("pin '%s' constrained to Bel '%s'.\n", trio->name.c_str(ctx),
ctx->getBelName(pinBel).c_str(ctx));
}
trio->attrs[ctx->id("BEL")] = ctx->getBelName(pinBel).str(ctx);
}
}
}
}
flush_cells();
}
// Pass to pack LUT5s into a newly created slice
void pack_lut5xs()
{
log_info("Packing LUT5-7s...\n");
for (auto cell : sorted(ctx->cells)) {
CellInfo *ci = cell.second;
if (is_pfumx(ctx, ci)) {
std::unique_ptr<CellInfo> packed =
create_ecp5_cell(ctx, ctx->id("TRELLIS_SLICE"), ci->name.str(ctx) + "_SLICE");
NetInfo *f0 = ci->ports.at(ctx->id("BLUT")).net;
if (f0 == nullptr)
log_error("PFUMX '%s' has disconnected port 'BLUT'\n", ci->name.c_str(ctx));
NetInfo *f1 = ci->ports.at(ctx->id("ALUT")).net;
if (f1 == nullptr)
log_error("PFUMX '%s' has disconnected port 'ALUT'\n", ci->name.c_str(ctx));
CellInfo *lut0 = net_driven_by(ctx, f0, is_lut, ctx->id("Z"));
CellInfo *lut1 = net_driven_by(ctx, f1, is_lut, ctx->id("Z"));
if (lut0 == nullptr)
log_error("PFUMX '%s' has BLUT driven by cell other than a LUT\n", ci->name.c_str(ctx));
if (lut1 == nullptr)
log_error("PFUMX '%s' has ALUT driven by cell other than a LUT\n", ci->name.c_str(ctx));
if (ctx->verbose)
log_info(" mux '%s' forms part of a LUT5\n", cell.first.c_str(ctx));
replace_port(lut0, ctx->id("A"), packed.get(), ctx->id("A0"));
replace_port(lut0, ctx->id("B"), packed.get(), ctx->id("B0"));
replace_port(lut0, ctx->id("C"), packed.get(), ctx->id("C0"));
replace_port(lut0, ctx->id("D"), packed.get(), ctx->id("D0"));
replace_port(lut1, ctx->id("A"), packed.get(), ctx->id("A1"));
replace_port(lut1, ctx->id("B"), packed.get(), ctx->id("B1"));
replace_port(lut1, ctx->id("C"), packed.get(), ctx->id("C1"));
replace_port(lut1, ctx->id("D"), packed.get(), ctx->id("D1"));
replace_port(ci, ctx->id("C0"), packed.get(), ctx->id("M0"));
replace_port(ci, ctx->id("Z"), packed.get(), ctx->id("OFX0"));
packed->params[ctx->id("LUT0_INITVAL")] =
get_or_default(lut0->params, ctx->id("INIT"), Property(0, 16));
packed->params[ctx->id("LUT1_INITVAL")] =
get_or_default(lut1->params, ctx->id("INIT"), Property(0, 16));
ctx->nets.erase(f0->name);
ctx->nets.erase(f1->name);
sliceUsage[packed->name].lut0_used = true;
sliceUsage[packed->name].lut1_used = true;
sliceUsage[packed->name].mux5_used = true;
if (lutffPairs.find(ci->name) != lutffPairs.end()) {
CellInfo *ff = ctx->cells.at(lutffPairs[ci->name]).get();
ff_to_slice(ctx, ff, packed.get(), 0, true);
packed_cells.insert(ff->name);
sliceUsage[packed->name].ff0_used = true;
lutffPairs.erase(ci->name);
fflutPairs.erase(ff->name);
}
new_cells.push_back(std::move(packed));
packed_cells.insert(lut0->name);
packed_cells.insert(lut1->name);
packed_cells.insert(ci->name);
}
}
flush_cells();
// Pack LUT6s
for (auto cell : sorted(ctx->cells)) {
CellInfo *ci = cell.second;
if (is_l6mux(ctx, ci)) {
NetInfo *ofx0_0 = ci->ports.at(ctx->id("D0")).net;
if (ofx0_0 == nullptr)
log_error("L6MUX21 '%s' has disconnected port 'D0'\n", ci->name.c_str(ctx));
NetInfo *ofx0_1 = ci->ports.at(ctx->id("D1")).net;
if (ofx0_1 == nullptr)
log_error("L6MUX21 '%s' has disconnected port 'D1'\n", ci->name.c_str(ctx));
CellInfo *slice0 = net_driven_by(ctx, ofx0_0, is_lc, ctx->id("OFX0"));
CellInfo *slice1 = net_driven_by(ctx, ofx0_1, is_lc, ctx->id("OFX0"));
if (slice0 == nullptr) {
if (!net_driven_by(ctx, ofx0_0, is_l6mux, ctx->id("Z")) &&
!net_driven_by(ctx, ofx0_0, is_lc, ctx->id("OFX1")))
log_error("L6MUX21 '%s' has D0 driven by cell other than a SLICE OFX0 but not a LUT7 mux "
"('%s.%s')\n",
ci->name.c_str(ctx), ofx0_0->driver.cell->name.c_str(ctx),
ofx0_0->driver.port.c_str(ctx));
continue;
}
if (slice1 == nullptr) {
if (!net_driven_by(ctx, ofx0_1, is_l6mux, ctx->id("Z")) &&
!net_driven_by(ctx, ofx0_1, is_lc, ctx->id("OFX1")))
log_error("L6MUX21 '%s' has D1 driven by cell other than a SLICE OFX0 but not a LUT7 mux "
"('%s.%s')\n",
ci->name.c_str(ctx), ofx0_0->driver.cell->name.c_str(ctx),
ofx0_0->driver.port.c_str(ctx));
continue;
}
if (ctx->verbose)
log_info(" mux '%s' forms part of a LUT6\n", cell.first.c_str(ctx));
replace_port(ci, ctx->id("D0"), slice1, id_FXA);
replace_port(ci, ctx->id("D1"), slice1, id_FXB);
replace_port(ci, ctx->id("SD"), slice1, id_M1);
replace_port(ci, ctx->id("Z"), slice1, id_OFX1);
slice0->constr_z = 1;
slice0->constr_x = 0;
slice0->constr_y = 0;
slice0->constr_parent = slice1;
slice1->constr_z = 0;
slice1->constr_abs_z = true;
slice1->constr_children.push_back(slice0);
if (lutffPairs.find(ci->name) != lutffPairs.end()) {
CellInfo *ff = ctx->cells.at(lutffPairs[ci->name]).get();
ff_to_slice(ctx, ff, slice1, 1, true);
packed_cells.insert(ff->name);
sliceUsage[slice1->name].ff1_used = true;
lutffPairs.erase(ci->name);
fflutPairs.erase(ff->name);
}
packed_cells.insert(ci->name);
}
}
flush_cells();
// Pack LUT7s
for (auto cell : sorted(ctx->cells)) {
CellInfo *ci = cell.second;
if (is_l6mux(ctx, ci)) {
NetInfo *ofx1_0 = ci->ports.at(ctx->id("D0")).net;
if (ofx1_0 == nullptr)
log_error("L6MUX21 '%s' has disconnected port 'D0'\n", ci->name.c_str(ctx));
NetInfo *ofx1_1 = ci->ports.at(ctx->id("D1")).net;
if (ofx1_1 == nullptr)
log_error("L6MUX21 '%s' has disconnected port 'D1'\n", ci->name.c_str(ctx));
CellInfo *slice1 = net_driven_by(ctx, ofx1_0, is_lc, ctx->id("OFX1"));
CellInfo *slice3 = net_driven_by(ctx, ofx1_1, is_lc, ctx->id("OFX1"));
if (slice1 == nullptr)
log_error("L6MUX21 '%s' has D0 driven by cell other than a SLICE OFX ('%s.%s')\n",
ci->name.c_str(ctx), ofx1_0->driver.cell->name.c_str(ctx),
ofx1_0->driver.port.c_str(ctx));
if (slice3 == nullptr)
log_error("L6MUX21 '%s' has D1 driven by cell other than a SLICE OFX ('%s.%s')\n",
ci->name.c_str(ctx), ofx1_1->driver.cell->name.c_str(ctx),
ofx1_1->driver.port.c_str(ctx));
NetInfo *fxa_0 = slice1->ports.at(id_FXA).net;
if (fxa_0 == nullptr)
log_error("SLICE '%s' has disconnected port 'FXA'\n", slice1->name.c_str(ctx));
NetInfo *fxa_1 = slice3->ports.at(id_FXA).net;
if (fxa_1 == nullptr)
log_error("SLICE '%s' has disconnected port 'FXA'\n", slice3->name.c_str(ctx));
CellInfo *slice0 = net_driven_by(ctx, fxa_0, is_lc, ctx->id("OFX0"));
CellInfo *slice2 = net_driven_by(ctx, fxa_1, is_lc, ctx->id("OFX0"));
if (slice0 == nullptr)
log_error("SLICE '%s' has FXA driven by cell other than a SLICE OFX0 ('%s.%s')\n",
slice1->name.c_str(ctx), fxa_0->driver.cell->name.c_str(ctx),
fxa_0->driver.port.c_str(ctx));
if (slice2 == nullptr)
log_error("SLICE '%s' has FXA driven by cell other than a SLICE OFX0 ('%s.%s')\n",
slice3->name.c_str(ctx), fxa_1->driver.cell->name.c_str(ctx),
fxa_1->driver.port.c_str(ctx));
replace_port(ci, ctx->id("D0"), slice2, id_FXA);
replace_port(ci, ctx->id("D1"), slice2, id_FXB);
replace_port(ci, ctx->id("SD"), slice2, id_M1);
replace_port(ci, ctx->id("Z"), slice2, id_OFX1);
for (auto slice : {slice0, slice1, slice2, slice3}) {
slice->constr_children.clear();
slice->constr_abs_z = false;
slice->constr_x = slice->UNCONSTR;
slice->constr_y = slice->UNCONSTR;
slice->constr_z = slice->UNCONSTR;
slice->constr_parent = nullptr;
}
slice3->constr_children.clear();
slice3->constr_abs_z = true;
slice3->constr_z = 0;
slice2->constr_children.clear();
slice2->constr_abs_z = true;
slice2->constr_z = 1;
slice2->constr_x = 0;
slice2->constr_y = 0;
slice2->constr_parent = slice3;
slice3->constr_children.push_back(slice2);
slice1->constr_children.clear();
slice1->constr_abs_z = true;
slice1->constr_z = 2;
slice1->constr_x = 0;
slice1->constr_y = 0;
slice1->constr_parent = slice3;
slice3->constr_children.push_back(slice1);
slice0->constr_children.clear();
slice0->constr_abs_z = true;
slice0->constr_z = 3;
slice0->constr_x = 0;
slice0->constr_y = 0;
slice0->constr_parent = slice3;
slice3->constr_children.push_back(slice0);
if (lutffPairs.find(ci->name) != lutffPairs.end()) {
CellInfo *ff = ctx->cells.at(lutffPairs[ci->name]).get();
ff_to_slice(ctx, ff, slice2, 1, true);
packed_cells.insert(ff->name);
sliceUsage[slice2->name].ff1_used = true;
lutffPairs.erase(ci->name);
fflutPairs.erase(ff->name);
}
packed_cells.insert(ci->name);
}
}
flush_cells();
}
// Create a feed in to the carry chain
CellInfo *make_carry_feed_in(NetInfo *carry, PortRef chain_in)
{
std::unique_ptr<CellInfo> feedin = create_ecp5_cell(ctx, ctx->id("CCU2C"));
feedin->params[ctx->id("INIT0")] = Property(10, 16); // LUT4 = 0; LUT2 = A
feedin->params[ctx->id("INIT1")] = Property(65535, 16);
feedin->params[ctx->id("INJECT1_0")] = std::string("NO");
feedin->params[ctx->id("INJECT1_1")] = std::string("YES");
carry->users.erase(std::remove_if(carry->users.begin(), carry->users.end(),
[chain_in](const PortRef &user) {
return user.port == chain_in.port && user.cell == chain_in.cell;
}),
carry->users.end());
connect_port(ctx, carry, feedin.get(), id_A0);
std::unique_ptr<NetInfo> new_carry(new NetInfo());
new_carry->name = ctx->id(feedin->name.str(ctx) + "$COUT");
connect_port(ctx, new_carry.get(), feedin.get(), ctx->id("COUT"));
chain_in.cell->ports[chain_in.port].net = nullptr;
connect_port(ctx, new_carry.get(), chain_in.cell, chain_in.port);
CellInfo *feedin_ptr = feedin.get();
IdString feedin_name = feedin->name;
ctx->cells[feedin_name] = std::move(feedin);
IdString new_carry_name = new_carry->name;
ctx->nets[new_carry_name] = std::move(new_carry);
return feedin_ptr;
}
// Create a feed out and loop through from the carry chain
CellInfo *make_carry_feed_out(NetInfo *carry, boost::optional<PortRef> chain_next = boost::optional<PortRef>())
{
std::unique_ptr<CellInfo> feedout = create_ecp5_cell(ctx, ctx->id("CCU2C"));
feedout->params[ctx->id("INIT0")] = Property(0, 16);
feedout->params[ctx->id("INIT1")] = Property(10, 16); // LUT4 = 0; LUT2 = A
feedout->params[ctx->id("INJECT1_0")] = std::string("NO");
feedout->params[ctx->id("INJECT1_1")] = std::string("NO");
PortRef carry_drv = carry->driver;
carry->driver.cell = nullptr;
connect_port(ctx, carry, feedout.get(), ctx->id("S0"));
std::unique_ptr<NetInfo> new_cin(new NetInfo());
new_cin->name = ctx->id(feedout->name.str(ctx) + "$CIN");
new_cin->driver = carry_drv;
carry_drv.cell->ports.at(carry_drv.port).net = new_cin.get();
connect_port(ctx, new_cin.get(), feedout.get(), ctx->id("CIN"));
if (chain_next) {
// Loop back into LUT4_1 for feedthrough
connect_port(ctx, carry, feedout.get(), id_A1);
carry->users.erase(std::remove_if(carry->users.begin(), carry->users.end(),
[chain_next](const PortRef &user) {
return user.port == chain_next->port && user.cell == chain_next->cell;
}),
carry->users.end());
std::unique_ptr<NetInfo> new_cout(new NetInfo());
new_cout->name = ctx->id(feedout->name.str(ctx) + "$COUT");
connect_port(ctx, new_cout.get(), feedout.get(), ctx->id("COUT"));
chain_next->cell->ports[chain_next->port].net = nullptr;
connect_port(ctx, new_cout.get(), chain_next->cell, chain_next->port);
IdString new_cout_name = new_cout->name;
ctx->nets[new_cout_name] = std::move(new_cout);
}
CellInfo *feedout_ptr = feedout.get();
IdString feedout_name = feedout->name;
ctx->cells[feedout_name] = std::move(feedout);
IdString new_cin_name = new_cin->name;
ctx->nets[new_cin_name] = std::move(new_cin);
return feedout_ptr;
}
// Split a carry chain into multiple legal chains
std::vector<CellChain> split_carry_chain(CellChain &carryc)
{
bool start_of_chain = true;
std::vector<CellChain> chains;
const int max_length = (ctx->chip_info->width - 4) * 4 - 2;
auto curr_cell = carryc.cells.begin();
while (curr_cell != carryc.cells.end()) {
CellInfo *cell = *curr_cell;
if (start_of_chain) {
chains.emplace_back();
start_of_chain = false;
if (cell->ports.at(ctx->id("CIN")).net) {
// CIN is not constant and not part of a chain. Must feed in from fabric
PortRef inport;
inport.cell = cell;
inport.port = ctx->id("CIN");
CellInfo *feedin = make_carry_feed_in(cell->ports.at(ctx->id("CIN")).net, inport);
chains.back().cells.push_back(feedin);
}
}
chains.back().cells.push_back(cell);
bool split_chain = int(chains.back().cells.size()) > max_length;
if (split_chain) {
CellInfo *passout = make_carry_feed_out(cell->ports.at(ctx->id("COUT")).net);
chains.back().cells.back() = passout;
start_of_chain = true;
} else {
NetInfo *carry_net = cell->ports.at(ctx->id("COUT")).net;
bool at_end = (curr_cell == carryc.cells.end() - 1);
if (carry_net != nullptr && (carry_net->users.size() > 1 || at_end)) {
boost::optional<PortRef> nextport;
if (!at_end) {
auto next_cell = *(curr_cell + 1);
PortRef nextpr;
nextpr.cell = next_cell;
nextpr.port = ctx->id("CIN");
nextport = nextpr;
}
CellInfo *passout = make_carry_feed_out(cell->ports.at(ctx->id("COUT")).net, nextport);
chains.back().cells.push_back(passout);
}
++curr_cell;
}
}
return chains;
}
// Pack carries and set up appropriate relative constraints
void pack_carries()
{
log_info("Packing carries...\n");
// Find all chains (including single carry cells)
auto carry_chains = find_chains(
ctx, [](const Context *ctx, const CellInfo *cell) { return is_carry(ctx, cell); },
[](const Context *ctx, const CellInfo *cell) {
return net_driven_by(ctx, cell->ports.at(ctx->id("CIN")).net, is_carry, ctx->id("COUT"));
},
[](const Context *ctx, const CellInfo *cell) {
return net_only_drives(ctx, cell->ports.at(ctx->id("COUT")).net, is_carry, ctx->id("CIN"), false);
},
1);
std::vector<CellChain> all_chains;
// Chain splitting
for (auto &base_chain : carry_chains) {
if (ctx->verbose) {
log_info("Found carry chain: \n");
for (auto entry : base_chain.cells)
log_info(" %s\n", entry->name.c_str(ctx));
log_info("\n");
}
std::vector<CellChain> split_chains = split_carry_chain(base_chain);
for (auto &chain : split_chains) {
all_chains.push_back(chain);
}
}
std::vector<std::vector<CellInfo *>> packed_chains;
// Chain packing
std::vector<std::tuple<CellInfo *, CellInfo *, int>> ff_packing;
for (auto &chain : all_chains) {
int cell_count = 0;
std::vector<CellInfo *> tile_ffs;
std::vector<CellInfo *> packed_chain;
for (auto &cell : chain.cells) {
if (cell_count % 4 == 0)
tile_ffs.clear();
std::unique_ptr<CellInfo> slice =
create_ecp5_cell(ctx, ctx->id("TRELLIS_SLICE"), cell->name.str(ctx) + "$CCU2_SLICE");
ccu2c_to_slice(ctx, cell, slice.get());
CellInfo *ff0 = nullptr;
NetInfo *f0net = slice->ports.at(ctx->id("F0")).net;
if (f0net != nullptr) {
ff0 = net_only_drives(ctx, f0net, is_ff, ctx->id("DI"), false);
if (ff0 != nullptr && can_add_ff_to_tile(tile_ffs, ff0)) {
ff_packing.push_back(std::make_tuple(ff0, slice.get(), 0));
tile_ffs.push_back(ff0);
packed_cells.insert(ff0->name);
}
}
CellInfo *ff1 = nullptr;
NetInfo *f1net = slice->ports.at(ctx->id("F1")).net;
if (f1net != nullptr) {
ff1 = net_only_drives(ctx, f1net, is_ff, ctx->id("DI"), false);
if (ff1 != nullptr && (ff0 == nullptr || can_pack_ffs(ff0, ff1)) &&
can_add_ff_to_tile(tile_ffs, ff1)) {
ff_packing.push_back(std::make_tuple(ff1, slice.get(), 1));
tile_ffs.push_back(ff1);
packed_cells.insert(ff1->name);
}
}
packed_chain.push_back(slice.get());
new_cells.push_back(std::move(slice));
packed_cells.insert(cell->name);
cell_count++;
}
packed_chains.push_back(packed_chain);
}
for (auto ff : ff_packing)
ff_to_slice(ctx, std::get<0>(ff), std::get<1>(ff), std::get<2>(ff), true);
// Relative chain placement
for (auto &chain : packed_chains) {
chain.at(0)->constr_abs_z = true;
chain.at(0)->constr_z = 0;
for (int i = 1; i < int(chain.size()); i++) {
chain.at(i)->constr_x = (i / 4);
chain.at(i)->constr_y = 0;
chain.at(i)->constr_z = i % 4;
chain.at(i)->constr_abs_z = true;
chain.at(i)->constr_parent = chain.at(0);
chain.at(0)->constr_children.push_back(chain.at(i));
}
}
flush_cells();
}
// Pack distributed RAM
void pack_dram()
{
for (auto cell : sorted(ctx->cells)) {
CellInfo *ci = cell.second;
if (is_dpram(ctx, ci)) {
// Create RAMW slice
std::unique_ptr<CellInfo> ramw_slice =
create_ecp5_cell(ctx, ctx->id("TRELLIS_SLICE"), ci->name.str(ctx) + "$RAMW_SLICE");
dram_to_ramw(ctx, ci, ramw_slice.get());
// Create actual RAM slices
std::unique_ptr<CellInfo> ram0_slice =
create_ecp5_cell(ctx, ctx->id("TRELLIS_SLICE"), ci->name.str(ctx) + "$DPRAM0_SLICE");
dram_to_ram_slice(ctx, ci, ram0_slice.get(), ramw_slice.get(), 0);
std::unique_ptr<CellInfo> ram1_slice =
create_ecp5_cell(ctx, ctx->id("TRELLIS_SLICE"), ci->name.str(ctx) + "$DPRAM1_SLICE");
dram_to_ram_slice(ctx, ci, ram1_slice.get(), ramw_slice.get(), 1);
// Disconnect ports of original cell after packing
disconnect_port(ctx, ci, id_WCK);
disconnect_port(ctx, ci, id_WRE);
disconnect_port(ctx, ci, ctx->id("RAD[0]"));
disconnect_port(ctx, ci, ctx->id("RAD[1]"));
disconnect_port(ctx, ci, ctx->id("RAD[2]"));
disconnect_port(ctx, ci, ctx->id("RAD[3]"));