Incorrectly instantiated DUT ports in the auto generated testbench when using SystemVerilog interface

[dh73]

When using SBY+SystemVerilog with a module that uses an interface as module ports, the auto generated testbench instantiates the DUT using the flattened view of the interface (the netlist after prep command) instead of using the interface, causing a SystemVerilog violation as it appears that the interface is left unconnected.

Module with Interface	Module after prep	Module in the DUT
module testcase (clk, rstn, intf.generic i);	module testcase(clk, rstn, i_foo, i_bar);	testcase UUT ( .clk(PI_clk), .rstn(PI_rstn), .i_bar(PI_i_bar) );

The user can manually edit the auto generated testbench or use the netlist after prep for simulation, but that limits the functionality of this feature.

Adding a testcase:
testcase_intf.gz

[dh73]

It is probably better to dump the netlist after the synthesis ( prep ) and use that with the testbench for simulation. That netlist is what is verified with SBY anyway.