HIGH time and LOW time for the clock signal #1
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zeekhuge
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zeekhuge
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Jul 11, 2016
In earlier versions, the configuration data is divided into 2 parts. The CYCLE_BTWN_SAMPLE and MISC_CONFIG_DATA part. The first one containing the number of delay cycles between each sample, and the second one containing miscellaneous configuration data like the SAMPLING_START_BIT or the SAMPLING_WIDTH. This commit add 2 more constants CYCLE_BEFORE_SAMPLE and CYCLE_AFTER_SAMPLE that use the SAMPLING_CONFIG_1 the lower word and the higher word of the register respectively. The CYCLE_BEFORE_SAMPLE value is the number of cycles to be delayed after the CLK_PIN is high, but before the sample is take. The CYCLE_AFTER_SAMPLE value is the number of cycles to be delayed after the sample is taken, but before the CLK_PIN is back to low. This commit is basically the first step to solve the #1 issue.
zeekhuge
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Jul 21, 2016
In the previous version, the sampling was done by using the TAKE_SAMPLE_8 macro. The TAKE_SAMPLE_8 macro performed following steps : - Toggle clock pin and thus make it HIGH - Take the input from GPIs and stores it in one of the register - Toggle clock pin and thus changes its state to LOW Thus there was no way to make the clock duty cycle configurable. This commit adds support for configurable duty cycle. Thus this commit finally closes #1. The sampling procedure, that is followed inside the SAMPLE_CYCLE_8 macro is as : - Toggle clock and thus make it HIGH - Wait for 'CYCLE_BEFORE_SAMPLE' number of cycles - Take the input sample and store it in one of the registers - Wait for 'CYCLE_AFTER_SAMPLE' number of cycles - Toggle clock and thus make it LOW - Waits for 'CYCLE_BTWN_SAMPLE' number of cycles - Checks if there is any interrupt using CHECK_INT macro or is used for some house keeping instruction - Instruction to transfer data, or for the counter, or to reset values - 2nd Instruction to transfer data or any such task The value of the CYCLE_BTWN_SAMPLE, CYCLE_BEFORE_SAMPLE and CYCLE_AFTER_SAMPLE comes from the configuration data. The above steps are performed in loop to allow continuous sampling
zeekhuge
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Aug 12, 2016
1 [ 133.886685] [parallel_interface] parallel_interface_driver_init 2 [ 133.887012] [parallel_interface] pi_rpmsg_probe 3 [ 133.970161] [beaglescope_driver] beaglescope_driver_init 4 [ 137.723822] pru-rproc 4a338000.pru1: pru_rproc_remove: removing rproc 4a338000.pru1 5 [ 137.723884] pru-rproc 4a338000.pru1: stopping the manually booted PRU core 6 [ 137.724056] ti-pruss 4a300000.pruss: unconfigured system_events = 0xffffffffffffffff host_intr = 0x00000001 7 [ 137.724091] remoteproc2: stopped remote processor 4a338000.pru1 8 [ 137.724312] remoteproc2: releasing 4a338000.pru1 9 [ 137.725324] pru-rproc 4a334000.pru0: pru_rproc_remove: removing rproc 4a334000.pru0 10 [ 137.725795] [parallel_interface] pi_rpmsg_remove 11 [ 137.734547] [parallel_interface] pi_release 12 [ 137.742868] ti-pruss 4a300000.pruss: unconfigured system_events = 0x00000000000b0000 host_intr = 0x00000007 13 [ 137.742920] remoteproc1: stopped remote processor 4a334000.pru0 14 [ 137.743417] remoteproc1: releasing 4a334000.pru0 15 [ 137.745638] remoteproc1: 4a338000.pru1 is available 16 [ 137.745683] remoteproc1: Note: remoteproc is still under development and considered experimental. 17 [ 137.745708] remoteproc1: THE BINARY FORMAT IS NOT YET FINALIZED, and backward compatibility isn't yet guaranteed. 18 [ 137.758358] pru-rproc 4a338000.pru1: booting the PRU core manually 19 [ 137.758412] remoteproc1: powering up 4a338000.pru1 20 [ 137.758849] remoteproc1: Booting fw image am335x-pru1-fw, size 28436 21 [ 137.758981] remoteproc1: remote processor 4a338000.pru1 is now up 22 [ 137.759057] pru-rproc 4a338000.pru1: PRU rproc node /ocp/pruss@4a300000/pru1@4a338000 probed successfully 23 [ 137.761139] remoteproc2: 4a334000.pru0 is available 24 [ 137.761184] remoteproc2: Note: remoteproc is still under development and considered experimental. 25 [ 137.761209] remoteproc2: THE BINARY FORMAT IS NOT YET FINALIZED, and backward compatibility isn't yet guaranteed. 26 [ 137.767669] remoteproc2: powering up 4a334000.pru0 27 [ 137.767748] remoteproc2: Booting fw image am335x-pru0-fw, size 75816 28 [ 137.768107] ti-pruss 4a300000.pruss: configured system_events = 0x00000000000b0000 intr_channels = 0x00000007 host_intr = 0x00000007 29 [ 137.774496] remoteproc2: remote processor 4a334000.pru0 is now up 30 [ 137.775713] virtio_rpmsg_bus virtio0: rpmsg host is online 31 [ 137.775822] virtio_rpmsg_bus virtio0: creating channel parallel_interface addr 0x1e 32 [ 137.776822] [parallel_interface] pi_rpmsg_probe 33 [ 137.776859] kobject (bfa4f2f8): tried to init an initialized object, something is seriously wrong. 34 [ 137.786124] CPU: 0 PID: 955 Comm: irq/198-remotep Tainted: G O 4.4.12-ti-r31 #1 35 [ 137.786151] Hardware name: Generic AM33XX (Flattened Device Tree) 36 [ 137.786240] [<c0015b81>] (unwind_backtrace) from [<c00123f9>] (show_stack+0x11/0x14) 37 [ 137.786300] [<c00123f9>] (show_stack) from [<c03c9363>] (dump_stack+0x73/0x80) 38 [ 137.786346] [<c03c9363>] (dump_stack) from [<c03caa3b>] (kobject_init+0x5f/0x6c) 39 [ 137.786397] [<c03caa3b>] (kobject_init) from [<c048fe39>] (device_initialize+0x25/0x80) 40 [ 137.786445] [<c048fe39>] (device_initialize) from [<c049141f>] (device_register+0xf/0x18) 41 [ 137.786515] [<c049141f>] (device_register) from [<bfa4f0cd>] (pi_rpmsg_probe+0x24/0x50 [parallel_interface]) 42 [ 137.786659] [<bfa4f0cd>] (pi_rpmsg_probe [parallel_interface]) from [<bf9e590d>] (rpmsg_dev_probe+0x50/0x10c [virtio_rpmsg_bus]) 43 [ 137.786745] [<bf9e590d>] (rpmsg_dev_probe [virtio_rpmsg_bus]) from [<c049341b>] (driver_probe_device+0x193/0x344) 44 [ 137.786793] [<c049341b>] (driver_probe_device) from [<c0491d91>] (bus_for_each_drv+0x51/0x80) 45 [ 137.786839] [<c0491d91>] (bus_for_each_drv) from [<c04931c9>] (__device_attach+0x81/0xe8) 46 [ 137.786885] [<c04931c9>] (__device_attach) from [<c04929bf>] (bus_probe_device+0x5b/0x60) 47 [ 137.786930] [<c04929bf>] (bus_probe_device) from [<c04912e3>] (device_add+0x303/0x430) 48 [ 137.786998] [<c04912e3>] (device_add) from [<bf9e53ef>] (__rpmsg_create_channel+0xc2/0x128 [virtio_rpmsg_bus]) 49 [ 137.787092] [<bf9e53ef>] (__rpmsg_create_channel [virtio_rpmsg_bus]) from [<bf9e5bb9>] (rpmsg_ns_cb+0x11c/0x148 [virtio_rpmsg_bus]) 50 [ 137.787186] [<bf9e5bb9>] (rpmsg_ns_cb [virtio_rpmsg_bus]) from [<bf9e5d1f>] (rpmsg_recv_done+0xf2/0x294 [virtio_rpmsg_bus]) 51 [ 137.787267] [<bf9e5d1f>] (rpmsg_recv_done [virtio_rpmsg_bus]) from [<c041dd43>] (vring_interrupt+0x33/0x74) 52 [ 137.787349] [<c041dd43>] (vring_interrupt) from [<bf9dd28f>] (pru_rproc_vring_interrupt+0x22/0x44 [pru_rproc]) 53 [ 137.787432] [<bf9dd28f>] (pru_rproc_vring_interrupt [pru_rproc]) from [<c0078389>] (irq_thread_fn+0x15/0x24) 54 [ 137.787480] [<c0078389>] (irq_thread_fn) from [<c0078615>] (irq_thread+0x101/0x18c) 55 [ 137.787529] [<c0078615>] (irq_thread) from [<c00483a7>] (kthread+0xaf/0xc4) 56 [ 137.787582] [<c00483a7>] (kthread) from [<c000ed15>] (ret_from_fork+0x11/0x1c) 57 [ 137.792769] remoteproc2: registered virtio0 (type 7) 58 [ 137.793025] pru-rproc 4a334000.pru0: PRU rproc node /ocp/pruss@4a300000/pru0@4a334000 probed successfully
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firmware code - https://github.com/ZeekHuge/BeagleScope/blob/port_to_4.4.12-ti-r31%2B/firmware/main_pru1_def.asm#L222
The clock signal being generated by the firmware code is in form of tiny pulses, as there is just one instruction gap between the two toggles
`TAKE_SAMPLE_8 .macro RX
This may not work with all ADC as the timing characteristics change from converter to converter. The HIGH and LOW time of the clock signal should actually be configurable or at least should have around 50% duty cycle. This will help covering a larger number of converters.
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