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Star.c
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Star.c
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/*
** Starscream 680x0 emulation library
** Copyright 1997, 1998, 1999 Neill Corlett
**
** Refer to STARDOC.TXT for terms of use, API reference, and directions on
** how to compile.
*/
#define VERSION "0.26c"
/***************************************************************************/
/*
** NOTE
**
** All 68020-related variables and functions are currently experimental, and
** unsupported.
*/
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <stdarg.h>
/***************************************************************************/
/*
** Register Usage
** --------------
**
** This is fairly consistent throughout the file. Occasionally, EAX or EDX
** will be used as a scratch register (in some cases the x86 instruction set
** demands this).
**
** EAX: Bit 0 : V flag
** Bit 1-7 : MUST BE ZERO
** Bit 8 : C flag
** Bit 14 : Z flag
** Bit 15 : N flag
** Bit 16-31: undefined
** EBX: Lower 16 bits: Current instruction word or register number
** Upper 16 bits: zero
** ECX: Primary data
** EDX: Primary address
** EBP: Current base offset of PC
** ESI: Current PC, including base offset
** EDI: Cycle counter
*/
/***************************************************************************/
/*
** 68010 Loop Mode Timing
** ----------------------
**
** Loop mode is implemented entirely in the DBRA instruction. It will
** detect when it's supposed to be in loop mode, and adjust its timing when
** applicable.
**
** The __loopmode variable controls when loop mode is active. It is set to
** 1 after an eligible loop is completed. It is set to 0 when the loop
** terminates, or when an interrupt / exception occurs.
**
** Loop info byte:
**
** Bits 1-3: Continuation cycles / 2
** Bits 4-6: Termination cycles / 2
** Bits 7-0: (Expiration cycles - continuation cycles) / 2
** (bit 7 wraps around to bit 0)
**
** With the loop info byte in AL:
** To get the continuation cycles:
** and eax,byte 0Eh
** To get the termination cycles:
** shr al,3
** and eax,byte 0Eh
** To get the continue/expire difference:
** rol al,2
** and eax,byte 06h
**
** Default = DBh
** (11011011)
** 101 : 101 = 5 2*5 = 10 continuation cycles
** 101 : 101 = 5 2*5 = 10 termination cycles
** 1 1: 11 = 3 2*3 = 6 10+6 = 16 expiration cycles
**
** (10/10/16 corresponds to the normal DBRA timing behavior)
*/
/***************************************************************************/
/*
** Algorithm for trace checkpoint in s680x0exec:
**
** If the SR trace flag is set {
** Set the trace trickybit. This differentiates us from the out-of-time
** case above.
** Set cycles_leftover = cycles_needed.
** Force a context switch.
** } otherwise {
** Clear the trace trickybit.
** }
** Begin the fetch/decode/execute loop as usual.
**
**
** In selected ret_timing routines:
**
** Subtract usual number of cycles from edi
** If I'm out of time (edi is negative) {
** Jump to execend with SF set, as usual.
** } otherwise (guaranteed at least one more instruction) {
** Jump to the s680x0exec trace checkpoint.
** }
**
**
** Make sure that the group 1 exception handler clears the trace trickybit.
**
**
** Upon reaching execend:
**
** If the trace trickybit is set {
** Set cycles_needed = cycles_leftover.
** Add cycles_needed to edi.
** Generate a trace exception (clearing the SR trace flag in the process).
** Clear the trace trickybit.
** If edi is positive, resume the fetch/decode/execute loop.
** Otherwise, fall through to the usual epilogue code.
** }
*/
/***************************************************************************/
/*
** Rebasing notes
** --------------
**
** Cached rebase happens on:
** * JMP, JSR, RTS, RTE, RTR, RTD
** * Exceptions (except hardware interrupts)
**
** Uncached rebase happens on:
** * Entry to s680x0exec()
** * Hardware interrupts
** * Supervisor flag change
** * Cache disable/invalidate (68020+)
**
** I can't think of any good reason why the hardware interrupt case should be
** uncached, except it happens to be convenient.
*/
typedef unsigned char byte;
typedef unsigned short word;
typedef unsigned int dword;
static int use_stack = -1;
static int hog = -1;
static int addressbits = -1;
static int cputype = -1;
static char *sourcename = NULL;
/* This counts the number of instruction handling routines. There's not much
** point to it except for curiosity. */
static int routine_counter = 0;
/* Misc. constants */
static char *x86ax [5] = {"?", "al" , "ax" , "?", "eax" };
static char *x86bx [5] = {"?", "bl" , "bx" , "?", "ebx" };
static char *x86cx [5] = {"?", "cl" , "cx" , "?", "ecx" };
static char *x86dx [5] = {"?", "dl" , "dx" , "?", "edx" };
static char *sizename[5] = {"?", "byte", "word", "?", "dword"};
static int quickvalue[8] = {8, 1, 2, 3, 4, 5, 6, 7};
static char direction[2] = {'r','l'};
/* Output file where code will be emitted */
static FILE *codefile;
/* Line number - used to make temporary labels i.e. "ln1234" */
static int linenum;
/* Effective address modes */
enum eamode {
dreg, areg, aind, ainc, adec, adsp,
axdp, absw, absl, pcdp, pcxd, immd
};
/* Loop information (68010) */
static int loop_c_cycles;
static int loop_t_cycles;
static int loop_x_cycles;
static unsigned char loopinfo[0x10000];
/*
** Misc. global variables which are used while generating instruction
** handling routines. Some of these may assume more than one role.
*/
static enum eamode main_eamode; /* EA mode, usually source */
static enum eamode main_destmode; /* EA mode, destination (for MOVE) */
static int main_size; /* Operand size (1, 2, or 4) */
static int sizedef; /* Size field in instruction word */
static int main_reg; /* Register number */
static int main_cc; /* Condition code (0-F) */
static int main_dr; /* Direction (right or left) */
static int main_ir; /* Immediate or register (for shifts) */
static int main_qv; /* Quick value */
/* Emit a line of code (format string with other junk) */
static void emit(const char *fmt, ...) {
va_list a;
va_start(a, fmt);
if(codefile) {
vfprintf(codefile, fmt, a);
} else {
fprintf(stderr, "Bad news: Tried to emit() to null file\n");
exit(1);
}
}
/* Dump all options. This is delivered to stderr and to the code file. */
static void optiondump(FILE *o, char *prefix) {
fprintf(o, "%sCPU type: %d (%d-bit addresses)\n", prefix,
cputype, addressbits);
fprintf(o, "%sIdentifiers begin with \"%s\"\n", prefix,
sourcename);
fprintf(o, "%s%s calling conventions\n", prefix,
use_stack ? "Stack" : "Register");
fprintf(o, "%sHog mode: %s\n", prefix,
hog ? "On" : "Off");
}
static void gen_banner(void) {
emit("; Generated by STARSCREAM version " VERSION "\n");
emit("; For assembly by NASM only\n");
emit(";\n");
emit("; Options:\n");
optiondump(codefile, "; * ");
emit(";\n");
emit("bits 32\n");
}
static void align(int n) {
emit("times ($$-$)&%d db 0\n", n - 1);
}
static void maskaddress(char *reg) {
if(addressbits < 32) {
emit("and %s,%d\n", reg, (1 << addressbits) - 1);
}
}
static void begin_source_proc(char *fname) {
emit("global _%s%s\n", sourcename, fname);
emit("global %s%s_\n", sourcename, fname);
emit("_%s%s:\n", sourcename, fname);
emit("%s%s_:\n", sourcename, fname);
}
/* Generate variables */
static void gen_variables(void) {
emit("section .data\n");
emit("bits 32\n");
emit("global _%scontext\n", sourcename);
align(8);
emit("_%scontext:\n", sourcename);
emit("contextbegin:\n");
/*
** CONTEXTINFO_MEM16
** CONTEXTINFO_MEM16FC
**
** 16-bit memory interface
*/
if(cputype <= 68010) {
emit("__fetch dd 0\n");
emit("__readbyte dd 0\n");
emit("__readword dd 0\n");
emit("__writebyte dd 0\n");
emit("__writeword dd 0\n");
emit("__s_fetch dd 0\n");
emit("__s_readbyte dd 0\n");
emit("__s_readword dd 0\n");
emit("__s_writebyte dd 0\n");
emit("__s_writeword dd 0\n");
emit("__u_fetch dd 0\n");
emit("__u_readbyte dd 0\n");
emit("__u_readword dd 0\n");
emit("__u_writebyte dd 0\n");
emit("__u_writeword dd 0\n");
if(cputype == 68010) {
emit("__f_readbyte dd 0\n");
emit("__f_readword dd 0\n");
emit("__f_writebyte dd 0\n");
emit("__f_writeword dd 0\n");
}
/*
** CONTEXTINFO_MEM32
**
** 32-bit memory interface
*/
} else {
emit("__fetch dd 0\n");
emit("__readbus dd 0\n");
emit("__writebus dd 0\n");
emit("__s_fetch dd 0\n");
emit("__s_readbus dd 0\n");
emit("__s_writebus dd 0\n");
emit("__u_fetch dd 0\n");
emit("__u_readbus dd 0\n");
emit("__u_writebus dd 0\n");
emit("__f_readbus dd 0\n");
emit("__f_writebus dd 0\n");
}
/*
** CONTEXTINFO_COMMON
**
** Registers and other info common to all CPU types
**
** It should be noted that on a double fault, bit 0 of both __pc and
** __interrupts will be set to 1.
*/
if(cputype >= 68000) {
emit("__resethandler dd 0\n");
emit("__reg:\n");
emit("__dreg dd 0,0,0,0,0,0,0,0\n");
emit("__areg dd 0,0,0,0,0,0,0\n");
emit("__a7 dd 0\n");
emit("__asp dd 0\n");
emit("__pc dd 0\n");
emit("__odometer dd 0\n");
/* Bit 0 of __interrupts = stopped state */
emit("__interrupts db 0,0,0,0,0,0,0,0\n");
emit("__sr dw 0\n");
}
/*
** CONTEXTINFO_68000SPECIFIC
*/
if(cputype == 68000) {
emit("__contextfiller00 dw 0\n");
}
/*
** CONTEXTINFO_68010
**
** Registers used on the 68010 and higher
*/
if(cputype >= 68010) {
emit("__sfc db 0\n");
emit("__dfc db 0\n");
emit("__vbr dd 0\n");
emit("__bkpthandler dd 0\n");
}
/*
** CONTEXTINFO_68010SPECIFIC
**
** Registers used only on the 68010
*/
if(cputype == 68010) {
emit("__loopmode db 0\n");
emit("__contextfiller10 db 0,0,0\n");
}
/*
** CONTEXTINFO_68020
**
** Registers used on the 68020 and higher
*/
if(cputype >= 68020) {
/*
** 68020 stack pointer rules (tentative)
**
** First of all, the 68000/68010 stack pointer behavior has
** not changed:
**
** 1. In supervisor mode, __a7 contains the supervisor stack
** pointer and __asp contains the user stack pointer.
** 2. In user mode, __a7 contains the user stack pointer and
** __asp contains the supervisor stack pointer.
**
** The only difference is that the "supervisor stack pointer"
** can be either ISP or MSP. __xsp contains whichever stack
** pointer is _not_ the current "supervisor stack pointer".
**
** Here's a table summarizing the above rules:
**
** S M | __a7 __asp __xsp
** ----+-----------------
** 0 0 | USP ISP MSP
** 0 1 | USP MSP ISP
** 1 0 | ISP USP MSP
** 1 1 | MSP USP ISP
**
** As usual, whenever SR changes, we have to play Stack
** Pointer Switcheroo:
**
** * If S changes: swap __asp and __a7 (as usual)
** * If M changes:
** - If S=0, swap __xsp and __asp
** - If S=1, swap __xsp and __a7
*/
emit("__xsp dd 0\n");
}
/* align(4);*/
emit("contextend:\n");
emit("__cycles_needed dd 0\n");
emit("__cycles_leftover dd 0\n");
emit("__fetch_region_start dd 0\n");/* Fetch region cache */
emit("__fetch_region_end dd 0\n");
emit("__xflag db 0\n");
/*
** Format of __execinfo:
** Bit 0: s680x0exec currently running
** Bit 1: PC out of bounds
** Bit 2: Special I/O section
**
** "Special I/O section" is enabled during group 0 exception
** processing, and it means a couple things:
** * Address and bus errors will not be tolerated (the CPU will
** just keel over and die). Therefore, information such as the
** current PC is not relevant.
** * Registers are not necessarily live. Since special I/O
** sections are guaranteed not to cause exceptions, this is not a
** problem.
*/
emit("__execinfo db 0\n");
emit("__trace_trickybit db 0\n");/* Pending trace exception */
emit("__filler db 0\n");
emit("__io_cycle_counter dd -1\n");/*always -1 when idle*/
emit("__io_fetchbase dd 0\n");
emit("__io_fetchbased_pc dd 0\n");
emit("__access_address dd 0\n");
emit("save_01 dd 0\n"); // Stef Fix (Gens)
}
/* Prepare to leave into the cold, dark world of compiled C code */
static void airlock_exit(void) {
emit("mov [__io_cycle_counter],edi\n");
emit("mov [__io_fetchbase],ebp\n");
emit("mov [__io_fetchbased_pc],esi\n");
emit("push ebx\n");
emit("push eax\n");
}
/* Prepare to return to the warm fuzzy world of assembly code
** (where everybody knows your name) */
static void airlock_enter(void) {
emit("pop eax\n");
emit("pop ebx\n");
emit("mov edi,[__io_cycle_counter]\n");
emit("mov ebp,[__io_fetchbase]\n");
emit("mov esi,[__io_fetchbased_pc]\n");
}
enum { airlock_stacksize = 8 };
static void cache_ccr(void) {
emit("mov al,[__sr]\n"); /* read CCR -> AL */ /* ????????000XNZVC */
emit("mov ah,al\n"); /* copy to AH */ /* 000XNZVC000XNZVC */
emit("and ax,0C10h\n"); /* isolate NZ...X */ /* 0000NZ00000X0000 */
emit("shl ah,3\n"); /* put NZ almost where we want it */ /* 0NZ00000000X0000 */
emit("shr al,4\n"); /* shift X flag into bit 0 */ /* 0NZ000000000000X */
emit("mov [__xflag],al\n"); /* store X flag */ /* 0NZ000000000000X al -> xflag */
emit("mov al,[__sr]\n"); /* read CCR -> AL again */ /* 0NZ00000000XNZVC */
emit("and al,3\n"); /* isolate VC */ /* 0NZ00000000000VC */
emit("shr al,1\n"); /* just V */ /* 0NZ000000000000V carry */
emit("adc ah,ah\n"); /* append C to rest of flags */ /* NZ00000C0000000V */
}
static void writeback_ccr(void) {
emit("shr ah,1\n"); /* C flag -> x86 carry */ /* 0NZ?????0000000V carry */
emit("adc ax,ax\n"); /* append to V flag */ /* NZ?????0000000VC */
emit("and ax,0C003h\n"); /* isolate NZ.......VC */ /* NZ000000000000VC */
emit("or ah,[__xflag]\n"); /* load X flag */ /* NZ00000X000000VC */
emit("ror ah,4\n"); /* now we have XNZ....VC */ /* 000XNZ00000000VC */
emit("or al,ah\n"); /* OR them together */ /* 000XNZ00000XNZVC */
emit("mov [__sr],al\n"); /* store the result */ /* 000XNZ00000XNZVC al -> sr */
}
/*
** This will make edi _very_ negative... far enough negative that the
** leftover cycle incorporation at the end of s68000exec() shouldn't be
** enough to make it positive.
*/
static void force_context_switch(void) {
emit("sub edi,[__cycles_needed]\n");
emit("mov dword[__cycles_needed],0\n");
}
/*
** Put all the unused cycles in the leftover cycle bank, so we can call
** attention to the tricky bit processor.
*/
static void force_trickybit_process(void) {
emit("inc edi\n");
emit("add [__cycles_leftover],edi\n");
emit("or edi,byte -1\n");/* smaller than a mov */
}
/* "newpc" has been renamed to this */
void perform_cached_rebase(void);
/* Copy either __s_* or __u_* memory map pointers */
static void copy_memory_map(char *map, char *reg) {
emit("mov %s,[__%s_fetch]\n", reg, map);
emit("mov [__fetch],%s\n", reg);
if(cputype < 68020) {
emit("mov %s,[__%s_readbyte]\n" , reg, map);
emit("mov [__readbyte],%s\n" , reg);
emit("mov %s,[__%s_readword]\n" , reg, map);
emit("mov [__readword],%s\n" , reg);
emit("mov %s,[__%s_writebyte]\n", reg, map);
emit("mov [__writebyte],%s\n", reg);
emit("mov %s,[__%s_writeword]\n", reg, map);
emit("mov [__writeword],%s\n", reg);
} else {
emit("mov %s,[__%s_readbus]\n" , reg, map);
emit("mov [__readbus],%s\n" , reg);
emit("mov %s,[__%s_writebus]\n" , reg, map);
emit("mov [__writebus],%s\n" , reg);
}
}
/***************************************************************************/
static void gen_interface(void) {
emit("section .text\n");
emit("bits 32\n");
emit("top:\n");
/***************************************************************************/
/*
** s680x0init()
**
** Entry: Nothing
** Exit: Zero
**
** This must be called before anything else. It decompresses the main jump
** table (and loop info, in the case of the 68010).
*/
begin_source_proc("init");
emit("pushad\n");
emit("mov edi,__jmptbl\n");
emit("mov esi,__jmptblcomp\n");
if(cputype == 68010) {
emit("mov ebx,__looptbl\n");
}
emit(".decomp:\n");
emit("lodsd\n");
emit("mov ecx,eax\n");
emit("and eax,0FFFFFFh\n");
emit("shr ecx,24\n");
emit("add eax,top\n");
emit("inc ecx\n");
if(cputype == 68010) {
emit("mov ebp,ecx\n");
}
emit(".jloop:\n");
emit("mov [edi],eax\n");
emit("add edi,byte 4\n");
emit("dec ecx\n");
emit("jnz short .jloop\n");
if(cputype == 68010) {
emit("lodsb\n");
emit(".lloop:\n");
emit("mov [ebx],al\n");
emit("inc ebx\n");
emit("dec ebp\n");
emit("jnz short .lloop\n");
}
emit("cmp edi,__jmptbl+262144\n");
emit("jne short .decomp\n");
emit("popad\n");
emit("xor eax,eax\n");
emit("ret\n");
/***************************************************************************/
/*
** s680x0exec(cycles)
**
** Entry: EAX = # cycles to execute
** Exit: 80000000h: success
** 80000001h: PC out of range
** 80000002h: unsupported stack frame
** FFFFFFFFh: CPU is dead because of a double fault
** < 80000000h: invalid instruction = address of invalid instr.
*/
begin_source_proc("exec");
if(use_stack) emit("mov eax,[esp+4]\n");
/*
** Check for stopped and double-faulted states.
*/
emit("test byte[__interrupts],1\n");
emit("jz .notstopped\n");
emit("test byte[__pc],1\n");
emit("jz .notfaulted\n");
emit("or eax,byte -1\n");
emit("ret\n");
emit(".notfaulted:\n");
emit("add [__odometer],eax\n");
emit("mov eax,80000000h\n");
emit("ret\n");
emit(".notstopped:\n");
emit("push ebp\n");
emit("push ebx\n");
emit("push ecx\n");
emit("push edx\n");
emit("push esi\n");
emit("push edi\n");
emit("mov [__cycles_needed],eax\n");
emit("mov edi,eax\n");/* store # of cycles to execute */
emit("dec edi\n");
emit("xor ebx,ebx\n");
emit("mov esi,[__pc]\n");
cache_ccr();
emit("xor ebp,ebp\n");
emit("mov byte[__execinfo],1\n");
/*
** Force an uncached re-base.
** This fulfills the "Entry to s680x0exec()" case.
*/
emit("call basefunction\n");
emit("add esi,ebp\n");
emit("test byte[__execinfo],2\n"); /* Check for PC out of bounds */
emit("jnz near exec_bounderror\n");
emit("mov dword[__cycles_leftover],0\n");/* an extra precaution */
/* PPL and Trace checkpoint */
emit("exec_checkpoint:\n");
emit("js short execquit\n");
/* Check PPL */
emit("mov cl,[__sr+1]\n");
emit("and ecx,byte 7\n");
emit("inc ecx\n");
emit("mov ch,[__interrupts]\n");
emit("or ch,ch\n");
emit("js short .yesint\n");
emit("shr ch,cl\n");
emit("jz short .noint\n");
emit(".yesint:\n");
emit("call flush_interrupts\n");
/* Force an uncached re-base */
emit("call basefunction\n");
emit("add esi,ebp\n");
emit("test byte[__execinfo],2\n"); /* Check for PC out of bounds */
emit("jnz near exec_bounderror\n");
emit(".noint:\n");
/*
** If the SR Trace flag is set, generate a pending trace exception.
*/
emit("mov ch,[__sr+1]\n");
emit("and ch,80h\n"); /* isolate trace flag */
emit("mov [__trace_trickybit],ch\n");
emit("jz short execloop\n");
/*
** Activate the tricky bit processor.
**
** Because edi isn't checked for negativity before entering the
** fetch/decode/execute loop, we're guaranteed to execute at least
** one more instruction before any trace exception.
**
** If another group 1 exception happens in the course of executing
** this next instruction, then the group_1_exception routine will
** clear the trace tricky bit and re-adjust the cycle counters, and
** we'll pretend none of this ever happened.
*/
force_trickybit_process();
emit("execloop:\n");
/* emit("xor ebx,ebx\n");suffice to say, bits 16-31 should be zero... */
emit("mov bx,[esi]\n");
emit("add esi,byte 2\n");
emit("jmp dword[__jmptbl+ebx*4]\n");
/* Traditional loop - used when hog mode is off */
if(!hog) {
emit("execend:\n");
emit("jns short execloop\n");
}
emit("execquit:\n");
/*
** Tricky Bit Processor
*/
/* Look for trace tricky bit */
emit("cmp byte[__trace_trickybit],0\n");
emit("je short execquit_notrace\n");
/* Generate trace exception */
emit("mov edx,24h\n");
emit("call group_1_exception\n");
perform_cached_rebase();
/* Subtract time used by exception processing */
emit("sub edi,byte %d\n", (cputype == 68010) ? 38 : 34);
emit("execquit_notrace:\n");
/*
** Look for pending interrupts that exceed the current PPL. These
** are higher priority and are therefore processed last (the ISR will
** end up getting control).
*/
emit("mov cl,[__sr+1]\n");
emit("and ecx,byte 7\n");
emit("inc ecx\n");
emit("mov ch,[__interrupts]\n");
emit("or ch,ch\n");
emit("js short execquit_yesinterrupt\n");
emit("shr ch,cl\n");
emit("jz short execquit_nointerrupt\n");
emit("execquit_yesinterrupt:\n");
emit("call flush_interrupts\n");
/*
** Force an uncached re-base.
** This fulfills the "Hardware interrupt" case.
*/
emit("call basefunction\n");
emit("add esi,ebp\n");
emit("test byte[__execinfo],2\n"); /* Check for PC out of bounds */
emit("jnz short exec_bounderror\n");
emit("execquit_nointerrupt:\n");
/*
** Incorporate leftover cycles (if any) and see if we should keep
** running.
*/
emit("add edi,[__cycles_leftover]\n");
emit("mov dword[__cycles_leftover],0\n");
emit("jns short execloop\n");
/* Leave s680x0exec with "Success" code. */
emit("mov ecx,80000000h\n");
/*
** Exit the s680x0exec routine. By this time the return code should
** already be in ecx.
*/
emit("execexit:\n");
emit("sub esi,ebp\n");
writeback_ccr();
emit("mov [__pc],esi\n");
emit("inc edi\n");
emit("mov edx,[__cycles_needed]\n");
emit("sub edx,edi\n");
emit("add [__odometer],edx\n");
emit("mov byte[__execinfo],0\n");
/*
** Remember: __io_cycle_counter is always -1 when idle!
**
** This prevents us from having to check __execinfo during the
** readOdometer / tripOdometer calls.
*/
emit("mov dword[__cycles_needed],0\n");
emit("mov dword[__io_cycle_counter],-1\n");
emit("mov eax,ecx\n");/* return code */
emit("pop edi\n");
emit("pop esi\n");
emit("pop edx\n");
emit("pop ecx\n");
emit("pop ebx\n");
emit("pop ebp\n");
emit("ret\n");
/*
** Leave s680x0exec with "Out of bounds" code.
*/
emit("exec_bounderror:\n");
emit("mov ecx,80000001h\n");
emit("jmp short execexit\n");
/*
** Invalid instruction handler
*/
emit("invalidins:\n");
emit("sub esi,byte 2\n"); /* back up one word */
emit("mov ecx,esi\n");/* get address in ecx */
emit("sub ecx,ebp\n");/* subtract base */
maskaddress("ecx");
if(addressbits == 32) {
emit("and ecx,7FFFFFFFh\n");
}
/* emit("or byte[__stopped],2\n");*/
emit("jmp short execexit\n");
/***************************************************************************/
/*
** s680x0reset()
**
** Entry: Nothing
** Exit: 0 on success
** 1 on failure:
** * if there's no Supervisor Program entry for address 0
** * if s680x0exec() is active
** -1 on double fault
*/
begin_source_proc("reset");
emit("mov eax,1\n");
emit("test [__execinfo],al\n"); /* Ensure s680x0exec() inactive */
emit("jnz near .return\n");
emit("cmp dword[__s_fetch],0\n");
emit("je near .return\n");
emit("dec eax\n");
emit("mov [__execinfo],al\n");
emit("sub eax,byte 16\n");
emit(".gp:\n");
emit("mov dword[__reg+64+eax*4],0\n");
emit("inc eax\n");
emit("jnz short .gp\n");
emit("mov [__asp],eax\n");
if(cputype >= 68020) emit("mov [__xsp],eax\n");
/* Set up SR for no tracing, supervisor mode, ISP, PPL 7 */
emit("mov word[__sr],2700h\n");
if(cputype >= 68010) {
emit("mov [__vbr],eax\n");
emit("mov [__sfc],al\n");
emit("mov [__dfc],al\n");
}
if(cputype == 68010) {
emit("mov [__loopmode],al\n");
}
/* Copy supervisor address space information */
copy_memory_map("s", "eax");
/* Generate Supervisor Program Space reads to get the initial PC and
** SSP/ISP */
emit("mov eax,1\n"); /* assume failure */
emit("mov [__pc],eax\n");
emit("mov [__interrupts],al\n");
emit("push esi\n");
emit("push ebp\n");
emit("xor esi,esi\n");
emit("call basefunction\n");/* will preserve eax */
emit("test byte[__execinfo],2\n");
emit("jnz short .exit\n");
emit("add esi,ebp\n");
emit("mov eax,[esi]\n");
emit("rol eax,16\n");
emit("mov [__a7],eax\n");
emit("mov eax,[esi+4]\n");
emit("rol eax,16\n");
emit("mov [__pc],eax\n");
/* An address error here will cause a double fault */
emit("and eax,byte 1\n");
emit("mov [__interrupts],al\n");
emit("neg eax\n"); /* -1 on double fault, 0 on success */
emit(".exit:\n");
emit("pop ebp\n");
emit("pop esi\n");
emit(".return:\n");
emit("ret\n");
/***************************************************************************/
/*
** s680x0interrupt(level, vector)
**
** Entry: EAX = interrupt level
** EDX = vector (-1 for auto, -2 for spurious)
** Exit: EAX = 0 on success
** 1 on failure, previous vector exists
** 2 on invalid input
*/
begin_source_proc("interrupt");
emit("push edx\n");
if(use_stack) {
emit("mov eax,[esp+8]\n"); /* eax = level */
emit("mov edx,[esp+12]\n"); /* edx = vector */
}
/*
** Verify parameters.
*/
emit("cmp eax,byte 7\n");
emit("ja short .badinput\n");
emit("or eax,eax\n");
emit("jz short .badinput\n");
emit("cmp edx,255\n");
emit("jg short .badinput\n");
emit("cmp edx,byte -2\n");
emit("jl short .badinput\n");
/*
** Calculate the vector number.
*/
emit("jne short .notspurious\n");
emit("mov edx,18h\n");
emit(".notspurious:\n");
emit("or edx,edx\n");
emit("jns short .notauto\n");
emit("lea edx,[eax+18h]\n");
emit(".notauto:\n");
/*
** Test to see if this interrupt level is already pending.
** If it is, return with failure.
*/
emit("push ecx\n");
emit("mov cl,al\n");
emit("mov ah,1\n");
emit("shl ah,cl\n");
emit("pop ecx\n");
emit("test [__interrupts],ah\n");
emit("jnz .failure\n");
/*
** Commit the given interrupt and vector number.
*/
emit("or [__interrupts],ah\n");
emit("mov ah,0\n");
emit("mov [__interrupts+eax],dl\n");
emit("and byte[__interrupts],0FEh\n");
/*
** Notify the tricky bit handler. If we're doing this outside of
** s680x0exec(), then the notification will have no effect, because
** __io_cycle_counter is always -1 when idle.
*/
emit("mov edx,[__io_cycle_counter]\n");
emit("inc edx\n");
emit("add [__cycles_leftover],edx\n");
emit("mov dword[__io_cycle_counter],-1\n");
/*
** Success (0)
*/
emit("pop edx\n");
emit("xor eax,eax\n");
emit("ret\n");
/*
** Failure (1)
*/
emit(".failure:\n");
emit("pop edx\n");
emit("mov eax,1\n");
emit("ret\n");
/*
** Bad input (2)
*/
emit(".badinput:\n");
emit("pop edx\n");
emit("mov eax,2\n");
emit("ret\n");
/***************************************************************************/
/*
** s680x0flushInterrupts()
**
** Flushes all pending interrupts.
**
** Entry: Nothing
** Exit: Nothing
*/
begin_source_proc("flushInterrupts");
/*
** If s680x0exec() is already running, then the interrupts are about
** to get flushed anyway. So ignore this call.
*/
emit("test byte[__execinfo],1\n");
emit("jnz .noflush\n");
/* Make registers "live" */
emit("pushad\n");
emit("mov esi,[__pc]\n");
emit("xor ebp,ebp\n");
cache_ccr();
emit("xor edi,edi\n"); /* well, semi-live */
emit("call flush_interrupts\n");
emit("sub [__odometer],edi\n"); /* edi will be <= 0 here */
emit("mov [__pc],esi\n"); /* PC guaranteed unbased */
writeback_ccr();
emit("popad\n");
emit(".noflush:\n");
emit("ret\n");
/***************************************************************************/
/*
** s680x0GetContextSize()
**
** Entry: Nothing
** Exit: Size of context array (in bytes)
*/
begin_source_proc("GetContextSize");
emit("mov eax,contextend-contextbegin\n");
emit("ret\n");
/***************************************************************************/
/*
** s680x0GetContext(context)
**
** Entry: Address of context in EAX
** Exit: Nothing
*/
begin_source_proc("GetContext");
emit("push edx\n");
emit("push edi\n");
if(use_stack) emit("mov edi,[esp+12]\n");
else emit("mov edi,eax\n");
emit("%%assign i 0\n");
emit("%%rep ((contextend-contextbegin) / 8)\n");
emit(" mov eax,[contextbegin+i+0]\n");
emit(" mov edx,[contextbegin+i+4]\n");
emit(" mov [edi+i+0],eax\n");
emit(" mov [edi+i+4],edx\n");
emit("%%assign i i+8\n");
emit("%%endrep\n");
emit("%%if ((contextend-contextbegin) %% 8)!=0\n");